JP2675742B2 - Clamp circuit with peak detection function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clamp circuit with a peak detecting function for reproducing a low frequency component including direct current of a transmission device and detecting a peak value of a signal amplitude.

[0002]

2. Description of the Related Art A conventional configuration of a clamp circuit with a peak detecting function is shown in FIG. In the figure, a clamp circuit is formed by the diode D1, the capacitor C1, and the resistors R1 and R2, and a peak detection circuit is formed by the diode D2, the capacitor C2, and the resistor R3. I is an input terminal, O1 is an output terminal for the clamped signal, and O2 is a terminal for outputting the peak value of the signal. A high-speed / high-frequency signal corresponding to the signal transmission speed is input / output to / from the terminals I and O1, while a low-frequency signal proportional to the peak value of the signal is output to the output terminal O2.

[0003]

In the circuit of FIG. 5 showing the above-mentioned prior art, the peak detection circuit is directly connected to the output terminal O1 of the high speed signal. Therefore, the diode D
Since the capacitance components of 1 and D2 can be seen from the output terminal O1, the frequency characteristics are limited by the load resistance of the output and the time constant of the input resistance component of the circuit connected to the next stage. In particular, since the parasitic capacitance increases by the amount of the diode D2 in the peak detection circuit as compared with the case where the clamp circuit is used alone, by adding the peak detection function,
There is a drawback that the high frequency performance is deteriorated.

An object of the present invention is to obtain a clamp circuit with a peak detecting function, which does not deteriorate the high frequency performance even if the peak detecting function is added.

[0005]

The above object is to provide a first capacitor whose one end is connected to an input terminal, a series circuit of the first capacitor and a first diode, and a clamp for the first diode. In a clamp circuit with a peak detection function, which includes a basic clamp circuit having a first bias circuit for setting a potential, and a peak detection circuit including a diode, a capacitor, and a resistor, the first input terminal is the first Connected to the connection terminal between the diode and the first capacitance, the second input terminal is connected to the second bias circuit, the first output terminal is connected to the main signal output terminal, and the second output terminal is connected. Is achieved by having a differential circuit connected to the peak detection circuit.

[0006]

The clamp circuit with a peak detecting function according to the present invention does not directly connect the output of the clamp circuit to the peak detecting circuit as in the conventional case, but inputs the output of the clamp circuit to the differential circuit to realize high-speed operation. A main signal output that outputs a data signal and a sub signal output that outputs a peak detection signal are divided and taken out, and a peak detection circuit is connected to the sub signal output to detect the peak value of the signal. . Therefore, in the signal path of the high-speed main signal, only the capacitance component of the clamping diode exists as a parasitic component, and the capacitance component of the peak detection diode is not included. It can be operated at high speed.

[0007]

Next, an embodiment of the present invention will be described with reference to the drawings. 1 is a diagram showing a first embodiment of a clamp circuit with a peak detection function according to the present invention, FIG. 2 is a diagram for explaining the effect of the present invention, (a) is a waveform according to the configuration of the present invention, and (b) is a conventional one. FIG. 3 is a diagram showing waveforms according to the configuration of FIG. 3, FIG. 3 is a diagram showing a second embodiment of the present invention, and FIG.

In FIG. 1 showing the first embodiment of the present invention,
A is a differential circuit, Ia1 and Ia2 are input terminals of the differential circuit A, Oa1 and Oa2 are output terminals of the differential circuit A, and B is a DC bias circuit of the terminal Ia2. Other symbols are the same as those shown in FIG. 5 of the conventional example, and Vss1 is a power source. By the bias circuit B, the input terminal Ia2 of the differential circuit A is biased to Vcl when the amplitude of the input signal of the clamp circuit is Vp and the clamp potential is Vcl, and the input amplitude is small. When the amplitude is large, Vcl-Vp / 2 (upper end clamp circuit), Vcl + Vp /
Biased to 2 (bottom clamp circuit). In the configuration shown in FIG. 1, the output of the clamp circuit composed of C1, D1, R1 and R2 is connected to one input terminal Ia1 of the differential circuit A. The other input terminal Ia2 of the differential circuit A is DC biased by the bias circuit B. One output terminal Oa1 of the differential circuit A is used as a main signal output terminal for sending a high speed data signal to the next stage.
On the other hand, the other output terminal Oa2 of the differential circuit A is D
It is connected to the input of the peak detection circuit composed of 2, C2 and R3. With the above configuration, the high-speed signal input from the input terminal I is output as the clamped high-speed signal from the output terminal O1 of the differential circuit A, and the peak value of the signal is output from the output terminal O2. Is detected.

In the configuration shown in this embodiment, the input signal is divided into the main signal and the sub-signal system for peak detection by the differential circuit A. Therefore, in the signal path of the high-speed main signal, the clamping diode D1 is connected. There is only a capacitive component as a parasitic component,
Since the capacitance component of the diode D2 for peak detection is not in the signal path of the high-speed main signal, it has a feature that it can operate at a higher speed than a conventional clamp circuit having a peak detection function.

FIG. 2 is a diagram showing the effect of the present invention. Actually, the structure of the present invention and the conventional structure are
Fabricated by IC using MESFET, 10Gb /
It is the figure which showed the experimental result which compared the waveform characteristic of the high-speed output signal of s. (A) is due to the constitution of the present invention (b)
Shows a waveform according to the conventional configuration. Comparing the figures, in the configuration (a) according to the present invention, the rise / fall time of the waveform is improved by about 30% as compared with the conventional configuration (b), and the above configuration according to the present invention is effective for high-speed operation. I understand.

FIG. 3 is a diagram showing a second embodiment of the present invention, which shows a configuration in which the differential circuit and the DC bias circuit in the first embodiment of the present invention shown in FIG. 1 are constituted by concrete circuits. ing. In FIG. 3, Q1 and Q2 are transistor pairs of a differential circuit, Q3 is a transistor for a constant current source,
Rl1 and Rl2 are load resistance pairs of the differential circuit, and D2 is the terminal I2.
Biasing diodes, R4, R5, and R6 are terminals I2
Biasing resistors, and Vdd, Vss1, and Vss2 represent power supply voltages, respectively.

Next, the third embodiment of the present invention shown in FIG.
A source follower consisting of transistors Q4 and Q5 and a resistor R7 is connected to the input section of the second embodiment shown in FIG. 3 and the resistor R7 is set to 50Ω, thereby making it possible to match the input of the clamp circuit with 50Ω. In addition, a source follower made up of transistors Q6 and Q7 is added to the peak detection output section of the circuit shown in the second embodiment to reduce the impedance, which is an advantageous configuration for speeding up. The circuit can also obtain the same effect as that of the second embodiment.

In FIGS. 3 and 4 showing the second and third embodiments, the FET is used as the transistor, but a bipolar transistor may be used. In each of the above-described embodiments, the case where the clamp circuit is the lower end clamp is shown, but the same effect can be obtained even when the upper end clamp is performed by inverting the cathode and anode terminals of the diode and inverting the positive and negative of the power supply Vss1. Obtainable.

[0014]

As described above, the clamp circuit with peak detecting function according to the present invention includes the first capacitor having one end connected to the input terminal, the series circuit including the first capacitor and the first diode, A first clamp circuit having a first bias circuit for setting a clamp potential to the first diode, and a peak detection circuit including a diode, a capacitor, and a resistor, and a clamp circuit with a peak detection function, comprising: The input terminal of the first diode and the first diode
The second input terminal is connected to the second
To a bias circuit, the first output terminal is connected to the main signal output terminal, and the second output terminal is connected to the peak detection circuit, the differential circuit has a peak detection function. Nevertheless, it is possible to obtain a clamp circuit with a peak detection function, which has excellent high-speed characteristics and has no deterioration in high-frequency performance, and thus an effect of contributing to speed-up in various transmission devices is obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of a clamp circuit with a peak detecting function according to the present invention.

2A and 2B are diagrams for explaining the effect of the present invention, in which FIG. 2A shows a waveform according to the configuration of the present invention, and FIG. 2B shows a waveform according to a conventional configuration.

FIG. 3 is a diagram showing a second embodiment of a clamp circuit with a peak detecting function according to the present invention.

FIG. 4 is a diagram showing a third embodiment of the clamp circuit with a peak detecting function according to the present invention.

FIG. 5 is a diagram showing a conventional clamp circuit with a peak detection function.

[Explanation of symbols]

 A ... Differential circuit B ... Bias circuit C1, C2 ... Capacitance D1 ... Diode (for clamp) D2 ... Diode (for peak detection) I ... Input terminal Ia1, Ia2 ... Input terminal of differential circuit Oa1, Oa2 ... Differential circuit Output terminal O1 ... Main signal output terminal

Claims (1)

(57) [Claims] 1. A first capacitor, one end of which is connected to an input terminal, and a series circuit of the first capacitor and a first diode,
A first clamp circuit having a first bias circuit for setting a clamp potential to the first diode, and a peak detection circuit including a diode, a capacitor, and a resistor, and a clamp circuit with a peak detection function, comprising:
Input terminal is connected to the connection terminal between the first diode and the first capacitance, the second input terminal is connected to the second bias circuit, and the first output terminal is connected to the main signal output terminal. And a clamp circuit having a peak detecting function, the differential circuit having a second output terminal connected to the peak detecting circuit.