JPH0222567B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a current switching type pulse output circuit.

A current switching type pulse output circuit includes a differential transistor pair to which an input signal is applied to the base of one of the transistors, a current source commonly connected to one terminal of each of the differential transistor pair, and It consists of an output transformer connected between the other terminals of the transistor pair and having the midpoint of the input winding connected to a voltage source, and sends out a pulse output obtained by amplifying the input signal from the output winding of the output transformer. It's becoming like that. Its feature is that large pulse output can be obtained, and it can be applied to repeaters in PCM communication systems, for example.

By the way, this current switching type pulse output circuit is
As will be explained in detail later, when the input signal is cut off, one of the differential transistor pairs that is turned on will generate more heat due to collector loss, and in the end the performance of each transistor will depend on the input signal. This was unreasonable in terms of system design, as it had to be determined not by heat generation during operation, but rather by consideration of heat generation during non-operation. In addition, in order to eliminate the heat generated, it is necessary to take measures such as using a transistor with a heat dissipation stud and attaching it to the board with screws to improve heat dissipation, which increases device size, device cost, and assembly man-hours. You will end up letting it happen. If the large amount of heat generated during non-operation can be reduced, the transistor only needs to have the ability to tolerate heat generation during normal operation, which would make system design easier and reduce the size of the device. It's advantageous.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to propose a current switching type pulse output circuit that can reduce the collector loss described above when the input signal is interrupted.

In accordance with the above object, the present invention is characterized by providing a detection circuit that detects disconnection of an input signal, and a control circuit that reduces collector loss in a differential transistor pair under the control of the detection circuit. .

The present invention will be explained below with reference to the drawings.

FIG. 1 is a circuit diagram showing a general current switching type pulse output circuit. In this figure, 11-1 and 11-2 are a pair of transistors and constitute a differential transistor pair 11. The emitter terminals E1 and E2 of both transistors are commonly connected to the current source 12, and the input winding 13- of the output transformer 13 is connected between the collector terminals C1 and C2 of both transistors.
1 is connected, and a pulse output P _put is taken out from its output winding 13-2. This pulse output P _put is an amplified version of the input signal S _io input to the base terminal of one of the transistor pair 11 (11-1 in the figure). The reference voltage V _R is input to the other base terminal (11-2 in the figure). Further, a voltage source (V _CC ) is connected to the midpoint M of the output winding 13 - 1 in the output transformer 13 . In addition, input winding 1
The resistor Rm connected in parallel to 3-1 is the output winding 1.
This is an impedance matching resistor for a line (not shown) connected to 3-2. Further, the current source 12 is actually formed by a negative voltage source _VEE and a resistor R connected thereto. This current source 12
need not be a constant current source.

The operation of the circuit of FIG. 1 is clear from the waveform diagrams in columns a to f of FIG. 2.

Column a in FIG. 2 shows the input signal _Sio , the respective collector voltages _V1 and _V2 of the transistors 11-1 and 11-2, and the
The waveforms of each emitter voltage Ve, etc. are shown. The horizontal axis is time t. Vp is each collector voltage V ₁ and V ₂
This is the AC amplitude voltage of , and shows the case where it swings around the power supply voltage V _CC . This is the case when the average mark rate of the input signal is 1/2, but in the case of PCM transmission, the average mark rate is generally reduced to 1/2 by inserting a scrambler, etc. However, even when the mark rate deviates from 1/2, the effects of the present invention are not lost. Input signal S _io is “H” (high) level (V _H )
and “L” (low) level (V _L ), and the reference voltage V _R is approximately halfway between V _H and V _L (V _R =
It is fixed at a constant level of V _H +V _L /2). Therefore, when the signal S _io is _VR , the transistor 11-1
turns on (11-2 turns off), and the emitter voltage
Ve becomes a level lower than _VH by _VBE . V _BE is the base-emitter voltage of transistor 11-1 (same for 11-2), typically 0.7-0.8V for silicon transistors. On the other hand, when the input signal _Sio is _VL , the transistor 11-2 is on (11-1 is off), and the emitter voltage
Ve becomes a level lower than V _R by V _BE .

Collector current i ₁ when transistor 11-1 is turned on and collector current i ₂ when transistor 11-2 is turned on are as shown in columns b and c, respectively. Further, the pulse output P _put is as shown in column d. In addition, in the present invention, as an example, the midpoint M
The pulse output P _put
The amplitude of is also approximately V _P. Note that this V _P is expressed as V _P =1/2·1·2Rm·4R _L /2Rm+4R _L =I·2Rm·R _L /Rm+2R _L (1). Rm is the resistance value of the impedance matching resistor mentioned above, R _L is the output transformer 1
This is the load resistance when looking at the load side from the output winding 13-2 of No. 3. The above equation (1) is calculated by multiplying R _L by the square of the ratio of the input winding and output winding of the output transformer 13 (2 in the above example) (4R L ), and the impedance matching resistor (4R _L ). 2Rm) multiplied by the current I. In other words, the amplitude of the voltage across the input winding 13-1, that is, (v ₁
-v ₂ ) (v ₁ and v ₂ have opposite polarities) is I・2Rm・4R _L /2Rm+4R _L , so the amplitude of only the collector voltage v ₁ representing Vp or the collector voltage v The amplitude of only ₂ is I・2Rm・4R _L /2Rm+4R _L multiplied by 1/2,
The above equation (1) is obtained.

Here, if the collector losses of the transistors 11-1 and 11-2 during normal operation while receiving the input signal S _io are P _C1 ′ and P _C2 ′, respectively, then P _C1 ′= ₁・( ₁ −) (2 ) = 1/2・I・(V _CC −V _P /2−V _H +V _BE ) (3) P _C2 ′= ₂・( ₂ −) (4) = 1/2・I・(V _CC −V _P /2−V _R +V _BE ) (5). Note that i ₁・in equations (2) and (4) above
(v ₁ −ve) and i ₂ ·(v ₂ −ve) are each shown with a bar above each term to indicate that they are time averages. Also, the collector voltages v ₁ and v ₂ are
It is only necessary to consider the case where i ₁ and i ₂ are not 0, and the second
From columns a, b, and c in the figure, (V _CC -V _P /2), respectively, and the emitter voltage ve can be determined by considering the case where i ₁ is not 0 and the case where i ₂ is not 0, respectively, so the transistor 11- 1 and 11-2, (V _H −V _BE and (V _R −V _BE ), respectively, are obtained from columns a, b, and c of FIG. 2, and the above equations (3) and (5) are derived. Note that 1/2 added at the beginning of each of equations (3) and (5) is the mark rate of the input signal S _io , and the case where the general mark rate = 1/2 is taken as an example.

Next, consider the collector losses of the transistors 11-1 and 11-2 when the input signal _Sio is disconnected, that is, when the pulse output circuit is not operating. Here, the input signal S _io is disconnected because
This means that the signal S _io is fixed at either the "H" level or "L" level DC level (V _H or V _L ), and the left side of column e in Figure 2 indicates that S _io is "H". The right side shows the case where the level is fixed (transistor 11-1 is on), and the right side shows the case where it is fixed at the "L" level (transistor 11-2 is on).
In this case, the collector voltage v ₁ is applied through the input winding 13-1 (which appears to be a mere conductor under a DC signal).
and v ₂ are both held at V _CC . Column f in Fig. 2 shows the collector currents (i ₁ , i ₂ ); when the "H" level is fixed, i ₁ = I (i ₂ is 0), and when the "L" level is fixed, i ₂ = I (i ₁ is 0). When the input signal _Sio is off, the transistor 11-
1 and 11-2 collector losses respectively as Pc ₁
and Pc ₂ , under a fixed "H" level (only transistor 11-1 is on, Pc ₂ =
0), P _C1 = I (v ₁ −ve) (6) = I・(V _CC −V _H +V _BE (7) Also, when the “L” level is fixed (only transistor 11-2 is on, P ₁ = 0), P _C2 = I・(v ₂ −ve) (8) = I・(V _CC −V _R +V _BE (9). In the above equations (6) and (8), v ₁ = _VCC ,
It is clear from column e in Figure 2 that v ₂ = V _CC , ve = V _H −V _BE in equation (6), and ve = V _R −V _BE in equation (8), and based on these, The above equations (7) and (9) are respectively derived.

Therefore, when the pulse output circuit is in operation (with S _io ), the collector losses Pc ₁ ′ and Pc ₂ ′ (formulas (3) and (5)
(formula) and collector loss _Pc during non-operation (S _io disconnected)
When comparing Pc ₂ and Pc 2 (formulas (7) and (9) above), Pc ₁ and Pc ₂ (when not operating) are more than twice as large as Pc ₁ ′ and Pc ₂ ′ (when operating). I can see that I am getting used to it.

In the end, when designing transistors 11-1 and 11-2, it is important to consider that these transistors are not based on the collector loss during the original operation of the pulse output circuit, but due to the collector loss during non-operation. This creates the unreasonable need to determine the specifications of 11-1 and 11-2, and also causes the problem of requiring measures such as heat dissipation as described above.

Therefore, the present invention reduces at least one, and if necessary, both of V _CC and I in the formulas representing Pc ₁ and Pc ₂ above. For this purpose, first, a signal disconnection detection circuit is required to detect that the input signal is disconnected. FIGS. 3A and 3B are circuit diagrams showing a first example and a second example of a signal disconnection detection circuit, respectively. Which circuit 31,
31' is also a well-known general circuit that receives an AC input signal _Sio through a transformer, performs full-wave rectification or half-wave rectification with a diode, passes through a peak holding circuit consisting of a capacitor and a resistor, and outputs a DC signal. This is to obtain the disconnection detection signal S _S. The signal S _S becomes an "H" level when the signal S _io is present, and becomes an "L" level when the signal S _io is off.

Next, a control circuit is required that receives the signal disconnection detection signal S _S and limits V _CC or I. First, some embodiments of a control circuit that limits the current I will be described with reference to the drawings. This type can be classified into three types: (1) a type that directly blocks the current I, and a type that indirectly blocks the current I and changes the operating point of the transistor.
() and a format in which part of the current is supplied from outside to indirectly reduce the current flowing through the differential transistor pair 11...(). Figures 4A and 4B are circuit diagrams showing first and second embodiments of the above format (), respectively. Note that elements with the same reference numbers or symbols used throughout the drawings are the same components. In FIG. 4A, the control circuit consists of a transistor 42, and when the input signal is cut off, that is, when the signal S _S is at the "L" level, the transistor 42 is turned off via the diode 41 to directly block the flow of the current I. 4th B
In the figure, the control circuit also includes a transistor 42.
It further includes a comparator 43. In this case, the signal disconnection detection signal S _S is the comparator 43
It will be given via. The signal S _S may be provided by various types of circuits, such that the polarity may be completely reversed or the DC level may deviate completely from the desired level. Therefore, these level fluctuations can be made to appear to be zero by adjusting the variable reference voltage Vr.

An embodiment of the current control type control circuit of the type () above, that is, the type that changes the operating point of the transistor, is shown in FIG. In FIG. 5, the control circuit consists of diodes 51 and 52 and receives a signal S _S . When the input signal is disconnected, the signal S _S becomes "L" level, and the diodes 51 and 52
The base potential of each transistor 11-1, 11-2 is lowered through the transistors 11-1 and 11-2. As a result, the operating point of the transistor shifts toward controlling the current I. Note that what is provided on the anode side of the diode 52 is an existing series resistor for generating the reference voltage _VR .

In the above-mentioned form (), a part of the current I is supplied from the outside and indirectly connected to the differential transistor pair 1.
The control circuit of the type that reduces the current flowing in the 6th A
and shown in Figure 6B. In FIG. 6A, this control circuit is formed by a transistor 61, which is turned on by a signal disconnection detection signal S _S at an "L" level, and supplies an external current i to the current source 12 side. Transistor 11-1 turned on here
Or the current flowing through 11-2 is from I (I-i)
will be reduced to FIG. 6B shows a circuit in which a comparator 43 is added to the circuit shown in FIG. 6A, and the effect is as described in FIG. 4B.

On the other hand, a voltage-controlled control circuit attempts to apparently lower the V _CC of the voltage source in order to reduce collector loss. FIG. 7A shows the first embodiment, and the present control circuit consists of a transistor 71,
A voltage V _CC to the midpoint M of the output winding 13 - 1 in the output transformer 13 is applied via the transistor 71 . During normal operation, the signal disconnection detection signal S _S is at the "H" level, and V _CC is applied to the midpoint M as is. On the other hand, when the signal S _S goes to "L" level, the power from V _CC suffers loss in the transistor 71 and is supplied to the midpoint M, so in effect
V _CC decreases. A direct current simply flows through the transistor 71, and a low-cost, high-power transistor can be used without using a transistor with good characteristics. The second embodiment of FIG. 7B is 4B.
A comparator 43 is introduced for the purpose described in the figure. Note that, except for the case shown in FIG. 5, the reference voltage V _R is used as the base input of the transistor 11-2.
Instead, it is also possible to use the inverted signal _io of the input signal _Sio , which is the base input of the transistor 11-1.

As explained above, according to the present invention, by adding a simple circuit, the transistors 11-1, 11- 2 can be designed, and there is no need for means for dissipating the large amount of heat generated.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a general current switching type pulse output circuit, Figure 2 is a waveform diagram used to explain the operation of the circuit in Figure 1, and Figures 3A and 3B are signal disconnection detection used in the present invention. 4A and 4B are circuit diagrams showing a first example and a second example of the circuit, respectively; FIGS. 4A and 4B are circuit diagrams showing a first example and a second example of the first type of current-controlled control circuit, respectively; FIG. 5 is a circuit diagram showing an embodiment of the second type of current-controlled control circuit, and FIGS. 6A and 6B are the first and second embodiments of the third type of current-controlled control circuit, respectively. FIG. 7A and FIG. 7B are circuit diagrams showing a first embodiment and a second embodiment of the voltage-controlled control circuit, respectively. In the figure, 11-1 and 11-2 are transistors, 11 is a differential transistor pair, 12 is a current source, 13 is an output transformer, 13-1 is an input winding, 13-2 is an output winding, 31, 31 ' are signal disconnection detection circuits, 41, 51, 52 are diodes, 42, 61, 71 are transistors, V _CC is a voltage source, S _io is an input signal, S _S is a signal disconnection detection signal, P _put is a pulse This is the output.

Claims (1)

[Claims] 1 A transistor 11-1 whose base input is an input signal (S _io ) alternating between an "H" (high) level and an "L" (low) level, and a reference voltage (V A differential transistor pair 11 consists of a transistor 11-2 whose base input is _R ), one of which is on and the other is off, and one terminal E1 of each of the differential transistor pair 11,
A current source 12 commonly connected to E2, and each other terminal C1 of the differential transistor pair 11,
An output transformer 13 includes an input winding 13-1 connected between C2 and an output winding 13-2 that sends out a pulse output (P _put ), and a midpoint (M ), and outputs a pulse output (P _{put )} that is an amplified input signal (S _{io )} . signal disconnection detection circuits 31, 31' for detecting that the base level of the transistor 11-1 is fixed at a DC level of "H" or "L"; and signal disconnection detection circuits 31, 31'. and a control circuit that reduces the collector loss occurring in the transistor 11-1 or transistor 11-2 that turns on when the signal disconnection detection signal S _S is received, and the control circuit includes two diodes 51, The anodes of the diode 51 and the diode 52 are connected to the bases of the transistor 11-1 and the transistor 11-2, respectively, and the cathode of the diode 51 and the diode 52 is commonly connected to a signal disconnection detection signal (S _S ). A current switching type pulse output circuit characterized by applying . 2. The pulse output according to claim 1, wherein a series resistor for generating a reference voltage (V _R ) is provided at a voltage dividing point, and both the base of the transistor 11-2 and the anode of the diode 52 are connected to the voltage dividing point. circuit. 3 A transistor 11-1 whose base input is an input signal (S _io ) that alternately changes between "H" (high) level and "L" (low) level, and a reference voltage (V _R ) as its base input. A differential transistor pair 11 consisting of transistors 11-2, one of which is on and the other is off, and one terminal E1 of each of the differential transistor pair 11,
A current source 12 commonly connected to E2, and each other terminal C1 of the differential transistor pair 11,
An output transformer 13 includes an input winding 13-1 connected between C2 and an output winding 13-2 that sends out a pulse output (P _put ), and a midpoint (M ), and outputs a pulse output (P _{put )} that is an amplified input signal (S _{io )} . signal disconnection detection circuits 31, 31' for detecting that the base level of the transistor 11-1 is fixed at a DC level of "H" or "L"; and signal disconnection detection circuits 31, 31'. the current source 12 _; The transistor 61 supplies a current (i) to the
1 is turned on by the signal disconnection detection signal ( _SS ), a current (I-i) obtained by subtracting the current (i) from the current (I) of the current source 12 flows through the differential transistor pair 11. A current-switchable pulse output circuit featuring: 4 Signal disconnection detection signal (S _S ) and reference voltage (V _r )
4. The pulse output circuit according to claim 3, further comprising a comparator 43 whose input is a comparator 43, whose output is used as a control input to the control circuit, and whose reference voltage (V _r ) is variable.