JP2673054B2 - Color page printer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color page printer provided with a memory for storing print data for each color.

[0002]

2. Description of the Related Art Conventionally, as a color page printer of this type, for example, as shown in FIG. 4, a plurality of memories 1 each having a capacity of about half the amount of data printed on one page of paper are provided for each color. For the print data of a certain color, store the print data in memory 1 as shown by the thin solid line in FIGS. 5 (a) and 5 (b), and recall the print data in the part shown by the dotted line previously stored. While printing, the memory area of the called part is managed by software, and when the print data is stored in the memory 1 to the end, as shown by the thick solid line in (c) of FIG. It is known to deal with the problem by sequentially storing print data following the memory area.

Further, normally, the printing area on the paper is the paper 1.
It is known that a memory having a capacity slightly smaller than the capacity for printing one page of paper is provided in anticipation of being smaller than the entire page and cost reduction.

[0004]

In the former case, in order to prevent the data stored in the memory 1 from overflowing, the data storage speed in the memory 1 and the data calling speed from the memory 1, that is, the print data Since it is necessary to synchronize the reception speed and the printing speed, there is a problem that control is troublesome. In the latter case, the printing area is narrower than the entire area of one page of the paper, so that it is inconvenient that printing cannot be performed on the entire area of one page of the paper.

Therefore, according to the present invention, it is not necessary to synchronize the receiving speed with the printing speed, and it is possible to surely print the entire paper without much space on the paper, and the memory is effective. It is intended to provide a color page printer that can be used for.

[0006]

SUMMARY OF THE INVENTION According to the present invention, there are provided a plurality of basic memories corresponding to respective colors for storing print data of an amount which is slightly less than that required to print one page of paper, and for each of these basic memories. provided commonly Te, and a small extended memory relatively capacity to store by dividing the excess printing data for each base memory when the amount of print data to be stored in each basic memory exceeds the capacity of the basic memory, each For each basic memory,
Addressing means for performing a linear addressing respectively divided area corresponding to the base memory of the extended memory and the base memory provided, various colors on the basis of addressing by addressing means from each base memory and extended memory Print data is called.

[0007]

In the present invention having such a configuration, when color printing is performed in an area narrower than the area of one page of paper, color printing can be performed while storing print data of various colors in each basic memory. When color printing is performed on the entire area of one page of the paper, the print data of various colors is stored in each basic memory, and the area of the extended memory is divided corresponding to each basic memory. The print data overflowing from each basic memory is stored in. At this time, linear addressing is performed for the corresponding divided areas of the basic memory and the extended memory.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, 11 is a CPU (central processing unit) that constitutes the main body of the control unit, and 12 is an RO that stores program data for the CPU 11 to control each unit.
M (read only memory), 13 is a RAM (random access memory) for storing various data other than print data for processing, 14 is an address change logic constituting an address designating means, and 15 is data・
Transceiver, 16 is decoder, 17 is base RAM1
, 18 are base RAM2, 19 are base RAM3, 2
0 is base RAM4, 21 is expansion R as expansion memory
AM and 22 are I / O ports. The base RAM1
17, the base RAM2 18, the base RAM3 19 and the base RAM4 20 constitute a basic memory, for example, a 1 Mbyte DRAM. In addition, the expansion RAM
Reference numeral 21 is composed of, for example, a 256-byte DRAM.

The CPU 11, the ROM 12, and the RAM
13, address change logic 14, decoder 1
6 is connected via an address bus line 23, a data bus line 24 and a control bus line 25, and the CPU 11 and the data transceiver 15 are connected via a data bus line 24 and a control bus line 25. Connected to the CPU 11 and the I / O
It is connected to the port 22 via a control bus line 25.

The address change logic 14
Are the base RAM 117, the base RAM 218, the base RAM3 19, the base RAM4 20 and the expansion RAM.
21 and the RAM address lines 26 of A0 to A23, and supply the chip select signal CS respectively.

The data transceiver 15 includes the base RAM 117, the base RAM 218, and the base RAM 3
19, the base RAM 420 and the expansion RAM 21 are connected via a data bus line 27.

The print data is input from the host device (not shown) to the I / O port 22 through the interface, and the CPU 11 outputs the print data to the decoder 16, the address change logic 14, and the data transceiver 15. Is controlled and stored in a desired base RAM.

As shown in FIG. 2, the address change logic 14 comprises a decoder 31, a selector 32 and various gate circuits, and addresses of 24 address lines (0) to (23) from the CPU 11 With lines (0)-(15)
(18) to (23) are connected to the RAM address line 26 as RAM addresses A0 to A15 and A18 to A23.

The address line (16) is connected to the input terminal B1 of the selector 32, the address line (17) is connected to the input terminal B2 of the selector 32, and the address line (21) is connected to the input terminal A1 of the selector 32. Then, the address line (22) is connected to the input terminal A2 of the selector 32.

The address line (20) is connected to the input terminal A of the decoder 31, the address line (21) is connected to the input terminal B of the decoder 31, and the address line (22) is connected to the input terminal C of the decoder 31. doing.

The decoder 31 converts the signals from the input terminals A, B and C into 8-bit data and outputs the output terminals Y0 to Y.
It outputs from 7. The signal from the output terminal Y0 is used as the select signal of the base RAM 117, and the output terminal Y2
The signal from is used as the select signal of the base RAM 218,
A signal from the output terminal Y4 is used as a select signal for the base RAM319, and a signal from the output terminal Y6 is used as the base RAM4.
20 select signals.

The address lines (16) to (19) are input to the 4-negative input type AND gate circuit 33 and the decoder 31
The signals from the output terminals Y1, Y3, Y5, and Y7 are input to the 4-negative input type OR gate circuit 34. The outputs of the gate circuits 33 and 34 are input to the 2-input NAND gate circuit 35.

The output of the NAND gate circuit 35 is inputted to one input terminal of a 2-negative input type NAND gate circuit 36 and also inputted to one input terminal of a 2-negative input type AND gate circuit 37. Further, the signal from the output terminal Y1 of the decoder 31 is inputted to one input terminal of the 2-negative input type AND gate circuit 38.

RA is applied to the other input terminal of the NAND gate circuit 36 and the other input terminal of the AND gate circuit 37.
The M mode signal is input, and the AND gate circuit 3
R to the other input terminal of 8 through the inverter circuit 39.
The AM mode signal is input. The output of the NAND gate circuit 36 is connected to the select terminal of the selector 32.
It is supplied to SEL, and the outputs of the AND gate circuits 37 and 38 are output as an extended RAM select signal via a 2-input NOR gate circuit 40.

The selector 32 has input terminals A1, A2 and input terminal B according to the input level to the select terminal SEL.
Either 1 or B2 is selected and output from the output terminals Y1 and Y2 as address signals A16 and A17.

That is, as shown in FIG. 3, when the RAM mode signal is at a high level, the linear address continuing from the base RAM 117 is allocated to the expansion RAM 21. That is, the decoder 31 has four address lines (20) to (2
From 3), the select signal Y0 of the area of the base RAM 117 and the area of the CPU address "000000 (HEX)" to "0FFFFF (HEX)" is output. Further, since the RAM mode signal is at the high level, the selector 32 outputs the extended R from the decoder 31.
When the select signal Y1 of the AM21 is output, the signals of the address lines (16) and (17) are selected and the address signals A16 and A17 are selected.
Is output and the CPU address “10
Allocate "0000 (HEX)" to "13FFFF (HEX)". At this time, the other base RAMs 18 to 20 are not used.

When the RAM mode signal is at a low level, the linear addresses continuing from the base RAMs 17 to 20 are assigned to the expansion RAM 21. That is, the decoder 31 receives the base RA from the four address lines (20) to (23).
M1 17 area, CPU address is "000000 (HEX)" ~
The select signal Y0 in the area "0FFFFF (HEX)" is output. Further, since the RAM mode signal is at the low level, the selector 32 selects the signal of the address line (21) (22) when the decoder 31 outputs the select signal Y1, Y3, Y5 or Y7 of the expansion RAM 21 to select the address. Signal A16,
A17 is output and the CPU address for the expansion RAM 21 is assigned. At this time, the CPU address for the base RAM 117 is "000000 (HEX)" to "0FFFFF (HEX)".
, And the CPU addresses for the expansion RAM 21 are “100000 (HEX)” to “10FFFF (HEX)”. The CPU address for the base RAM218 is "200000".
(HEX) "to" 2FFFFF (HEX) ", and the CPU address for the expansion RAM 21 is" 300000 (HEX) "to" 30FFFF (HEX) ".
EX) ”. C for the base RAM319
The PU address is "400000 (HEX)" to "4FFFFF (HEX)", and the CPU address for the expansion RAM 21 is "5000".
00 (HEX) ”to“ 50FFFF (HEX) ”. Further, the CPU address for the base RAM 420 is "600000 (HE
X) "to" 6FFFFF (HEX) ", and the CPU address for the expansion RAM 21 is" 700000 (HEX) "to" 70FFFF (HEX) ".
X) ”.

In this embodiment having such a structure, for example, print data for one page of black, red, blue, and yellow is printed for each base R.
RA when storing in AM17-20 and printing in color
Set the M-mode signal to low level.

As a result, C is added to the base RAM 117.
PU addresses “000000 (HEX)” to “0FFFFF (HEX)” are assigned, and CPU addresses “100000 (HEX)” to “10FFFF (HEX)” are assigned to the expansion RAM 21. Therefore, the black print data for one page is stored in the base RAM11.
The capacity of print data when stored in 7 is base RAM1
Even if the area of 17 is exceeded, the area is stored in the address areas "100000 (HEX)" to "10FFFF (HEX)" of the expansion RAM 21. The address at this time changes linearly from the base RAM 117 to the expansion RAM 21.

Therefore, even if the capacity of the base RAM 117 is set to be slightly smaller than the capacity for printing one page of the paper, the entire page of the paper is not printed, that is, a certain space is opened before and after the paper. In normal printing, the print data can be stored only in the base RAM 117, and when printing one page of paper, the base RAM 117 and expansion RAM are used.
Both 21 can store print data.

This is because the base RAM218, the base R
The same applies to the case of storing print data of various colors of red, blue, and yellow in the AM3 19 and the base RAM 420. When the print data for one page is stored in the base RAM 18 to 20, the capacity of the print data is from the base RAM 18 to 20. 20 address areas "200000 (HEX)" to "2FFFFF (HEX)", "400000 (HE
X) '' to `` 4FFFFF (HEX) '', `` 600000 (HEX) '' to `` 6FFFFF
Even if it exceeds (HEX) ", the corresponding amount will be" 300000 (HEX) "to" 30FFFF (HEX) "and" 500000 (HEX) in the expansion RAM 21.
EX) '' to `` 50FFFF (HEX) '', `` 700000 (HEX) '' to `` 70FF
FF (HEX) ”. The address at this time changes linearly from the base RAMs 18 to 20 to the expansion RAM 21.

The table below shows the allocation of CPU addresses to the base RAM and expansion RAM 21 when the above RAM mode is high level and low level.

[0029]

[Table 1]

In the case of color printing as described above, print data for one page of various colors can be reliably stored by using the base RAMs 17 to 20 and the expansion RAM 21 in common. Therefore, it is not necessary to synchronize the reception speed and the printing speed, and the processing speed can be increased. Further, the expansion RAM 21 can be used even when printing with almost no space left and right on one sheet. Moreover, one expansion RAM 21 can be effectively used, and the CPU address for the expansion RAM 21 can be linearly assigned.

For example, when printing one color, if the RAM mode is set to the high level, the base RAM 117 and the extended R
CPU address "000000 (HEX)" for AM21 ~
"13FFFF (HEX)" can be assigned linearly.
Therefore, in this case also, the print data for one page is stored in the base RAM1.
17 and expansion RAM 21 can be used for reliable storage.

[0032]

As described above in detail, according to the present invention, it is not necessary to synchronize the receiving speed and the printing speed, and printing can be performed on the entire sheet without opening much space. It is also possible to provide a color page printer that can surely perform the above and can effectively use the memory.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a specific circuit diagram of the address change logic shown in FIG.

FIG. 3 is a base RAM and an expansion RAM in the same embodiment.
The figure which shows the relationship between selection and an address.

FIG. 4 is a memory diagram showing a conventional example.

FIG. 5 is a diagram for explaining a storage process of print data in a memory of the conventional example.

[Explanation of symbols]

11 ... CPU (central processing unit), 14 ... Address change logic (address designation means), 17-20 ... Base RAM (basic memory), 21 ... Extended RAM (extended memory).

Claims (1)

(57) [Claims] 1. A plurality of basic memories corresponding to respective colors for storing print data of an amount which is slightly less than printing for one page of paper, and a common memory provided for each basic memory. When the amount of print data to be stored in the basic memory exceeds the capacity of the basic memory, the expansion memory with a relatively small capacity that stores the print data that exceeds the basic memory is stored in each basic memory, and as each of the elementary memories the divided area corresponding provided addressing means for performing a linear addressing, each basic memory and the expansion memory based on addressing by said addressing means of said extended memory and memory A color page printer that calls print data of various colors from the printer.