JPS6282442A - Memory circuit - Google Patents
Memory circuitInfo
- Publication number
- JPS6282442A JPS6282442A JP22302685A JP22302685A JPS6282442A JP S6282442 A JPS6282442 A JP S6282442A JP 22302685 A JP22302685 A JP 22302685A JP 22302685 A JP22302685 A JP 22302685A JP S6282442 A JPS6282442 A JP S6282442A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- circuit
- main body
- control
- expansion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、情報処理装置のメモリ回路に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a memory circuit for an information processing device.
従来の技術
例えば、ＭＳＸ２パーソナルコンピュータのメモリの拡
張で、本体コストの低減のため、特に外部に着脱可能な
拡張メモリとＩ１０領域にレジスタが有り、このレジス
タとＣＰＵで発生したアドレスを基にしてアドレスの拡
張を行なう着脱可能なアドレス拡張回路と着脱可能な拡
張メモリ制御回路を装着する場合、第３図に示す様にＣ
ＰＵ２０１の信号から本体メモリ制御回路２０２でメモ
リの制御信号を発生し本体メモリ２０３に与えメモリを
アクセスする。又、同様にしてＣＰＵ２０１の信号から
アドレス拡張回路２０４と拡張メモリ制御回路２０６で
制御信号を発生し拡張メモリ制御回路２０６に与えメモ
リをアクセスする。Conventional technology For example, when expanding the memory of an MSX2 personal computer, in order to reduce the cost of the main unit, there is an externally removable expansion memory and a register in the I10 area, and the address is calculated based on this register and the address generated by the CPU. When installing a removable address expansion circuit and a removable expansion memory control circuit, the C
The main body memory control circuit 202 generates a memory control signal based on the signal from the PU 201 and supplies it to the main body memory 203 to access the memory. Similarly, a control signal is generated by the address expansion circuit 204 and the expansion memory control circuit 206 from the signal of the CPU 201 and is applied to the expansion memory control circuit 206 to access the memory.
３ べ−・
発明が解決しようとする問題点
本体メモリと拡張メモリが別々の制御回路で制御され各
々でアドレスが決まり、第４図に示す様に本体メモリ領
域３０１と拡張メモリ領域３０２のアドレスの連続性を
保つ事が出来なく、全てのメモリの活用がしにくい。3. Problems to be Solved by the Invention The main body memory and the extended memory are controlled by separate control circuits, and addresses are determined for each, and as shown in FIG. Continuity cannot be maintained, making it difficult to utilize all memory.
問題点を解決するための手段
拡張メモリが存在する事を検出した時点か、もしくはユ
ーザが目的に合わせマニュアルで、制御信号切り換え回
路に切り換え信号を与え、拡張メモリ制御回路で本体メ
モリを制御する。こうする事により本体メモリと拡張メ
モリは同一制御部で制御できアドレス拡張回路で発生し
たアドレスを本体メモリと拡張メモリに割り当てる事が
可能となる。Means for Solving the Problem When detecting the presence of an extended memory, or manually by the user according to the purpose, a switching signal is given to the control signal switching circuit, and the extended memory control circuit controls the main body memory. By doing so, the main body memory and the extended memory can be controlled by the same control section, and the addresses generated by the address expansion circuit can be assigned to the main body memory and the extended memory.
作用
本発明は着脱可能なアドレス拡張回路と着脱ｉｑ能な拡
張メモリ制御回路で本体メモリと拡張メモリの制御を可
能とすることにより、第２図に示す様に本体メモリ領域
４０１と拡張メモリ領域４０２にアドレス拡張回路の連
続したアドレスを割り当てる事が可能となる。Operation The present invention enables control of the main body memory and extended memory using a removable address extension circuit and a removable extended memory control circuit, thereby controlling the main body memory area 401 and the extended memory area 402 as shown in FIG. It becomes possible to allocate consecutive addresses of the address expansion circuit to the address expansion circuit.
実施例
以下、図面に基づいて本発明の詳細な説明する。第１図
に一実施例の構成図を示す。ｃｐｔｙｌｏｌ、メモリ制
御回路１０２、制御切り換え回路１０３、本体メモリ１
０４、制御切り換え信号発生回路１０５ばＭＳＸ２パー
ソナル・コンビ。EXAMPLES Hereinafter, the present invention will be explained in detail based on the drawings. FIG. 1 shows a configuration diagram of an embodiment. cptylol, memory control circuit 102, control switching circuit 103, main body memory 1
04, control switching signal generation circuit 105 MSX2 personal combination.
−ター内で構成されており、アドレス拡張回路１０６、
拡張メモリ制御回路１０７、拡張メモリ１０８はメモリ
拡張ボード上で構成されている。- an address extension circuit 106;
The expansion memory control circuit 107 and expansion memory 108 are configured on a memory expansion board.
拡張メモリボードを挿入していない時、メモリアクセス
の制御信号は、ＣＰＵ１０１の信号からメモリ制御回路
１０２で制御信号を発生させ制御切り換え回路１０３を
介し本体メモリ１０４に制御信号を与えメモリをアクセ
スする。When an expansion memory board is not inserted, a memory access control signal is generated by a memory control circuit 102 from a signal from a CPU 101, and a control signal is applied to a main body memory 104 via a control switching circuit 103 to access the memory.
拡張メモリボードを挿入した時は、本体側の制御切り換
え信号発生回路１０６から制御信号を制御切り換え回路
１０３に与え、拡張メモリ制御回路１０了で本体メモリ
１０４を制御する。この事５、−３−１
によりＣＰＵ１０１の信号からアドレス拡張回路１０６
と拡張メモリ制御回路１０７で発生するメモリを制御す
る信号を本体メモリ１０４と拡張メモリ１０８に与える
事ができ、本体メモリ１０４と拡張メモリ１０８にアド
レス拡張回路１０６の連続アドレスを割り当てる事がで
きる。When an expansion memory board is inserted, a control signal is applied from the control switching signal generation circuit 106 on the main body side to the control switching circuit 103, and the main body memory 104 is controlled by the expansion memory control circuit 10. Due to this fact 5, -3-1, from the signal of the CPU 101 to the address extension circuit 106
A memory control signal generated by the extended memory control circuit 107 can be given to the main body memory 104 and the extended memory 108, and consecutive addresses of the address extension circuit 106 can be assigned to the main body memory 104 and the extended memory 108.
発明の効果
以上の説明より本発明では、メモリ拡張ボード上の拡張
メモリだけではなく、本体メモリも拡張メモリ制御回路
で制御する事が可能となり、全メモリにアドレス拡張回
路の連続アドレスを与えることができメモリを有効に活
用することが出来る。Effects of the Invention From the above explanation, in the present invention, not only the expansion memory on the memory expansion board but also the main body memory can be controlled by the expansion memory control circuit, and it is possible to give consecutive addresses of the address expansion circuit to all memories. memory can be used effectively.
第１図は本発明の一実施例におけるメモリ回路のブロッ
ク図、第２図は本発明のメモリのアドレス構成例を示す
図、第３図は従来のメモリ回路のブロック図、第４図は
従来のメモリのアドレス構成例を示す図である。
１０１・・・・・・ＣＰＵ、１０２・・・・・本体メモ
リ、１０３・・・・・・制御切り換え回路、１０４・・
・・・・本体メ６ペー／
モリ、１０５・・・・・・アドレス拡張回路、１０６・
・・・・制御切シ換え信号発生回路、１０７・・・・・
・拡張メモリ制御回路、１０８・・・・・・拡張メモリ
。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第２図
第３図FIG. 1 is a block diagram of a memory circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of the address structure of the memory of the present invention, FIG. 3 is a block diagram of a conventional memory circuit, and FIG. 4 is a conventional memory circuit. FIG. 2 is a diagram illustrating an example address configuration of a memory. 101... CPU, 102... Body memory, 103... Control switching circuit, 104...
...Main body memory page 6/Mory, 105...Address expansion circuit, 106.
...Control switching signal generation circuit, 107...
- Expansion memory control circuit, 108...extension memory. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3
Claims (1)
したアドレスを基にしてアドレスの拡張をする着脱可能
なアドレス拡張回路と、本体メモリの制御を行なう信号
を発生するメモリ制御回路と、前記本体メモリと前記拡
張メモリを制御する信号を発生する着脱可能な拡張メモ
リ制御回路と、前記本体メモリに与える制御信号を切り
換える制御切り換え回路と、この制御切り換え回路に切
り換え信号を与える制御切り換え信号発生回路とを有し
、前記拡張メモリと前記アドレス拡張回路と前記拡張メ
モリ制御回路が接続されている場合には、前記制御切り
換え信号発生回路が切り換え信号を発生し前記制御切り
換え回路を動作させ、前記本体メモリと前記拡張メモリ
を前記拡張メモリ制御回路で前記アドレス拡張回路のア
ドレスを用い制御する事により前記本体メモリと前記拡
張メモリを連続アドレス空間に割り当てることを特徴と
するメモリ回路。a main body memory, a removable expansion memory, a removable address expansion circuit that extends an address based on an address generated by the CPU, a memory control circuit that generates a signal for controlling the main body memory, and the main body. a removable expansion memory control circuit that generates signals for controlling the memory and the expansion memory; a control switching circuit that switches control signals to be applied to the main body memory; and a control switching signal generation circuit that provides a switching signal to the control switching circuit. and when the expansion memory, the address expansion circuit, and the expansion memory control circuit are connected, the control switching signal generation circuit generates a switching signal to operate the control switching circuit, and the main body memory and the expansion memory is controlled by the expansion memory control circuit using an address of the address expansion circuit, thereby allocating the main body memory and the expansion memory to a continuous address space.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22302685A JPS6282442A (en) | 1985-10-07 | 1985-10-07 | Memory circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22302685A JPS6282442A (en) | 1985-10-07 | 1985-10-07 | Memory circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6282442A true JPS6282442A (en) | 1987-04-15 |
Family
ID=16791673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22302685A Pending JPS6282442A (en) | 1985-10-07 | 1985-10-07 | Memory circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6282442A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04344271A (en) * | 1991-05-22 | 1992-11-30 | Tokyo Electric Co Ltd | Color page printer |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60134947A (en) * | 1983-12-23 | 1985-07-18 | Matsushita Graphic Commun Syst Inc | Memory extension system |
-
1985
- 1985-10-07 JP JP22302685A patent/JPS6282442A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60134947A (en) * | 1983-12-23 | 1985-07-18 | Matsushita Graphic Commun Syst Inc | Memory extension system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04344271A (en) * | 1991-05-22 | 1992-11-30 | Tokyo Electric Co Ltd | Color page printer |
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