JP2670075B2 - Image full scale determination device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image scanner represented by a facsimile machine, a digital copying machine or the like, which automatically sets a reference voltage of an analog / digital converter (A / D converter). Full scale determination device.

2. Description of the Related Art A typical example of a device using an analog / digital converter is a digital image scanner. FIG. 10 shows a basic schematic circuit configuration thereof. An optical image by reflected light from the document surface is formed on an image sensor, for example, a CCD light receiving surface, photoelectrically converted by the CCD 1 and read.
The analog image signal read by this CCD1 undergoes analog processing by the sample and hold (S / H) circuit & amplifier circuit 2, and then the analog / digital converter (A / D converter) 3
And is converted into a digital signal and output.

Here, the A / D converter 3 is generally configured as shown in FIG. This A / D converter 3 has a power supply terminal
One analog input pin in addition to V _DD and ground pin V _SS
V _IN , multiple, for example, 8 bit digital output terminals B _{1 to} B
₈ , Clock terminal CLK, A / D to determine A / D conversion timing
Upper limit terminal V as the terminal that determines the reference voltage above and below the conversion
_{REF +} and a lower limit terminal V _REF- are provided, and further, depending on the converter, an overflow terminal OFW for digital output is provided. In terms of circuitry, a comparator group 4, a latch 5, an encoder 6, a flip-flop 7 and a 3-state buffer group 8 are provided in this order from the input side to the output side. Reference numeral 9 is a clock generator which outputs clock signals φ1 and φ2. Then, the sum of the digital outputs ΣBi
Is determined by V _IN and V _{REF +} , V _REF- . If FS is the full scale of digital output, Expressed as, with a resolution of 8 bits (i = 8), V _REF-
Is ground GND, V _REF− = 0, FS = 255,
The above formula is Becomes That is, it is determined by the ratio of V _IN and V _{REF +} .

Here, the problem is V _{REF +} , which is the upper limit of the reference voltage.
Is the setting of the voltage value of. This is because if it is lower than V _IN , the digital output will output 255, which is full scale, and if it is too high with respect to V _IN , gradation will be wasted. Therefore, it is desirable to set the value of V _{REF +} to be equal to the maximum value of V _IN .

Then, the processing in the image data processing circuit in the general image scanner specifically shown in FIG. 12 will be described. First, a timing pulse for transfer or shift is given to the CCD 11 which reads an optical image, and under the self-scanning of the CCD 11, the CCD 11 outputs an image signal output OS and a dark signal output DOS. These image signal output OS and dark signal output DOS are differentially amplified by the buffer circuit 12,
The buffer circuit 12 outputs an image signal obtained by removing CCD reset noise and the like. Since it is a pulsed signal at this stage and has a DC offset, first, the switch 13 is closed by the zero clock ZCLK to perform zero clamp. This is for determining the 0 level of the image signal output from the buffer circuit 12, and is normally performed by turning on the switch 13 by the zero clock ZCLK at the timing immediately after the reset pulse of the CCD 11. Next, the sample hold is performed by the switch 14 and the capacitor Cs. That is, CC
Only when the output of D11 correctly shows the image level proportional to the reflectance of the document, the sampling clock
This is performed by turning on the switch 14 by SCLK and charging the capacitor Cs. The charging voltage of such a capacitor Cs is input to the buffer of the high impedance FET, whereby an analog image signal with 0V as a reference is obtained as the source output of the FET 15.

The image signal output from the FET 15 is set to a predetermined voltage Vo by the operational amplifier 16 and input to the reference voltage terminal REF of the digital / analog converter (D / A converter) 17 in the next stage. On the other hand, the digital input terminal of the D / A converter 17 is supplied with the shading correction data SDATA processed as described later. As a result, the output signal V _DA output from the D / A converter 17 is proportional to the value obtained by multiplying the shading correction data SDATA, and is shown as V _DA ∝ Vo × SDATA.

The output V _DA from the D / A converter 17 is directly input to the operational amplifier 19 on the one hand and indirectly via the switch 18 on the other hand. The operational amplifier 19 is a dummy pixel in the CCD 11 in order to compensate the dark current output of the CCD 11 (that is, a pixel provided outside the effective pixel of the CCD 11 in a light-shielded state,
The dark current component is sampled and held by turning on the switch 18 by the dummy signal DS which is turned on at the timing of (pixels which always output only dark current component). And
The subtraction processing for subtracting the dark current component from the image signal V _DA is performed by the operational amplifier 19. As a result, a signal V _IN which is an input image signal to the analog / digital converter (A / D converter) 10 from the operational amplifier 19, that is, a true analog image signal obtained by removing the dark current component of the CCD 11 is also obtained. Is output.

On the other hand, through the switch 21 which is turned on by the white reference signal WS generated at the timing when the CCD 11 reads the white reference plate 25 (see FIG. 13), the output side of the operational amplifier 19 and the A / D Two-stage operational amplifiers 22 and 23 are connected between the converter 20 and the reference voltage terminal REF. That is, for the analog image signal V _IN output from the operational amplifier 19, the white reference output is sampled and held at the timing of the white reference signal WS at which the switch 21 is turned on, and the operational amplifier 22 and the variable resistor VR are connected.
Thus, the level-adjusted voltage is obtained as V _REF . This reference value signal voltage V _REF is for determining the full scale of the image signal.

In FIG. 13, reference numeral 26 is a contact glass, 27 is an imaging lens, 28 is an exposure lamp, and 1 is an effective image range.

Here, the image clock VCLK is input to the A / D converter 20, and the analog image signal V _IN is used as the image clock VCL with the reference value signal voltage V _REF as a reference (full scale).
A / D conversion is performed in synchronization with K. That is, considering the case of 8 bits, the output from the A / D converter 20 is V _IN / V _REF × 255. As a result, the analog image signal V _IN is first converted into a digital image signal by the A / D converter 20, and the digital image data VDATA is obtained after the data conversion is performed in the ROM 14.

However, the method of determining the reference reference voltage V _REF by the method shown in FIG. 12 is based on the combination of analog circuits such as the operational amplifiers 22 and 23 and the variable resistance VR. However, the stability of the system may be impaired. In addition, the adjustment is performed by the manual operation of the variable resistor VR, which may cause variations in the configuration. Furthermore, the angle of view of the CCD 11 is expanded outside the effective image range, and the number of pixels allocated in the effective image is reduced.
It is also said that the effective scanning rate of D11 is reduced.

These points will be further described. First, in the case of a conventional analog circuit configuration, noise is a major cause of system instability. For example, when noise is mixed in the power supply, particularly when pulsed noise having a fixed cycle is mixed, the noise suppression effect of the amplifier or the like is significantly reduced, and noise is mixed in the output. In addition, noise may be mixed depending on the ambient conditions.
Since the reference voltage value for the A / D converter is determined by peak hold or sample hold in such an unstable state that noise can be mixed in, the stability of the entire system is also impaired. Further, since the level may fluctuate due to temperature, the image may gradually deteriorate over a long period of time. On the other hand, in the variable resistor VR, the level variation generally occurs, and this is due to the manual adjustment, and the variation among the devices becomes large.

Also, consider the shading correction. Generally, in this type of original image reading scanner, the illuminance distribution characteristic of the light source (the illuminance at the center is higher than both ends of the light source) and the condensing characteristic of the lens (so-called cosine fourth law in which light is collected at the center of the lens) The sensitivity correction called shading correction is mainly performed for the three reasons that the sensitivity unevenness is present in each pixel of the sensor CCD (the sensitivity unevenness is ± 10% at maximum).

For example, FIG. 14 (a) shows a CCD output waveform for one line in the main scanning direction when an image of white uniform density is read. As shown in the figure, the central part is high and the period is short (pixel period).
The output is uneven. On the other hand, after the shading correction using the shading data, a uniform flat output is produced as shown in FIG. here,
The dotted line in FIG. 14 shows each V _{REF +} .

There are various methods for the shading correction method. However, among them, the following electrical correction methods are relatively effective. First, as shown in FIG. 13, a white reference plate 25 is provided outside the image effective area 1 on the reading start side.
This white reference plate 25 is provided prior to normal image reading.
Is read to obtain an output waveform as shown in FIG. Next, along a path indicated by a broken line in FIG.
A / D converter 29 (same configuration as A / D converter 3) performs A / D conversion,
The converted data is stored in the RAM 30 for shading. Then, during normal image reading, the A / D converted digital data is output via the A / D converter 29 according to the path shown by the solid line in FIG. At this time, the passing shading correction circuit 31 is mainly a digital / analog multiplier.
It is composed of a ROM, and as a result, by dividing the image signal by the white output digitized by being stored in the RAM 30, it is possible to correct the sensitivity unevenness due to the reason described above.

In any case, the reference voltage upper limit value V for reading the correction data and normal correction for the A / D converter 30
You need to set _{REF +} in some way. In this respect, conventionally, two analog switches are used as shown in FIG.
Using 32 and 33, the analog switch 32 is turned on only when reading the shielding data, and the analog switch 33 is turned on only during normal reading. Therefore, first, when reading the shading correction data, the scanner is stopped so as to read the white reference plate, and the output waveform is viewed with an oscilloscope so that V _{REF +} becomes equal to the maximum value of V _IN (see FIG. 14 (a)). Turn the volume VR1 while adjusting. Similarly during normal reading, adjust the volume VR2 while observing the output waveform on the oscilloscope so that V _{REF +} becomes equal to the maximum value of V _IN (see FIG. 14 (b)).

However, such a conventional method has the following drawbacks. First, it is necessary to turn the volume VR1 and VR2 to make adjustments, which is troublesome and time-consuming.In addition, since adjustments are made while looking at the oscilloscope, it is not practical to exactly match the maximum value of V _IN. It is possible. Furthermore, as described above, the light quantity of the light source changes due to fluctuations in the power supply voltage, rising characteristics when the power is turned on, deterioration of the light source over time, etc., and therefore the voltage value of V _IN also changes. Therefore, even if adjustments are made once and then adjusted, in a few minutes, it may actually go wrong.

Object The present invention has been made in view of such a point, the automatic setting of the reference voltage value for the A / D converter that can eliminate the instability of the system when the output fluctuates due to noise etc. Furthermore, it is possible to cope with the fluctuation of the analog input voltage so that the gradation of the digital output is most effective, and
It is an object of the present invention to obtain an image full-scale determination device capable of processing in a short time.

Configuration The present invention, in order to achieve the above object, a reading unit for reading a document image, a density reference plate facing the reading unit, and an A / D conversion of an image signal read by the reading unit according to a reference signal. An image full scale having a D conversion means and determining the reference signal so that the image signal when the reading means reads the density reference plate is A / D converted at the full scale of the A / D conversion means. In the determination device, a generation unit that detects a match between a plurality of predetermined values corresponding to a plurality of desired densities and an output value from the A / D conversion unit, and generates one selected detection result; The reference signal changing means changes the reference signals one after another when the reading of the means is started, and stops changing the reference signal when the detection result is output from the generating means.

Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 to 7. First, it is assumed that the signal processing from the CCD 11 to the operational amplifier 19 shown in FIG. 12 is performed in the same manner as in the conventional case and the analog image signal V _IN is obtained by the operational amplifier 19. An analog / digital converter (A / D converter) 4 that uses such an analog image signal V _IN as one input
0 is provided. As will be described later, the A / D converter 40 digitally converts the analog image signal V _IN using the reference voltage V _REF , which is a reference value signal, as full scale to output data V
_It is output as _OUT . That is, considering 8 bits, V _OUT = V _IN / V _REF × 255. The output data V _OUT from the A / D converter 40 is output to the shading correction data storage section and the like, while being output to the comparison means 41. here,
The comparing means 41 has three comparing circuits 42, 4 for setting three kinds of density.
It is composed of 3,44. The comparison circuit 42 is dark (Dar
k) The comparison circuit, the comparison circuit 43 is a normal comparison circuit, and the comparison 44 is a light comparison circuit, and different output data control values PRD, PRN, PRL are preset. These output data limit values are (PRL)>(PRN)>
(PRD) is set.

Further, all of these comparison circuits 42, 43, 44 can operate simultaneously, but only one of the outputs is selected by the selector 25. That is, the output sides of the comparison circuits 42, 43 and 44 are connected to the selector 45 which performs a selection operation by the density selection signal DNL according to the density selection switch operation. The selector 45 serves as a control means and receives the coincidence signal from the selected comparison circuit 42, 43 or 44 and inputs a stop signal to the enable terminal ENBL of the down counter 46 which is a counter.

Here, the down counter 46 is a pre-set counter initial value, and sequentially counts down from the initial value for each line at the timing of the line synchronization signal LSYNC, and the selector 45 is connected to the enable terminal ENBL.
The down-count operation is stopped when the stop signal is output from. The count value output DC _OUT from the down counter 46 is input to the digital / analog converter (D / A converter) 47. This D / A converter 47 converts the digital count value output DC _OUT into a reference value signal voltage V _REF as an analog value with a voltage value corresponding to it and outputs it to the reference input terminal of the A / D converter 40. To do. That is, considering the A / D converter 40 as a center,
A feedback loop having a logic configuration is formed by the comparison circuit 41, the selector 45, the down counter 46, and the D / A converter 47, and the full scale (reference value signal voltage) V _REF is determined by digital processing. ing.

In such a structure, first, when the reading operation is started, the reading operation is performed on the white reference plate. When such a read operation starts, the line sync signal LSYNC
Occurs, the down counter 46 reads the counter initial value as a preset value. Then, the counting operation of counting down is performed for each line in which the line synchronization signal LSYNC is generated. Then, the output data DC _OUT according to the count value of the down counter 46 is converted into an analog reference value signal voltage V _REF by the D / A converter 47 and changes for each line as shown in FIG. It is input to the A / D converter 40 in the state. In the A / D converter 40, the analog image data V _IN read on the white reference plate is digitally converted according to the reference reference voltage V _REF at that time and output as output data V _OUT .

Here, in the comparison circuit 41, if the light setting is performed by the density setting switch operation, for example, the output of only the write comparison circuit 44 of the comparison circuits 42, 43, 44 becomes effective by the L signal of the DNL signal. So that the selector 45 operates. Here, the operation of the write comparison circuit 44 and the selector 45 will be described with reference to FIG. 2 by taking the case where the write comparison circuit 44 is selected as an example. First, in the write comparison circuit 44, the output data V _OUT is input to the input terminal A and the input terminal B is input.
The output data limit value PRL is preset in. The write comparison circuit 44 compares the output data V _OUT with the output data limit value PRL to determine whether A = B or A> B, that is, when the output data V _OUT matches or exceeds the data limit value PRL. Sometimes, a latch circuit 49 is connected through an OR gate 48.
Is output to The latch circuit 49 performs a latch operation by being regulated by a frame signal FGATE representing the period from the start to the end of reading one document (that is, the frame signal FGATE passes through the inverter 50). It is input to the reset terminal and is reset at the end of one original document). The output from the latch circuit 49 is input to the enable terminal ENBL of the down counter 46 as a stop signal. That is, when the write comparison circuit 44 determines that the output data V _OUT matches based on the write density output data limit value PRL, the count value of the down counter 46 is latched to the value at that time. And the down count operation stops. In this way, the reference value provided for the A / D converter to be obtained by performing analog conversion by the D / A converter 47 based on the output data DC _OUT based on the count value latched in the down counter 46. The signal voltage V _REF is obtained.

Note that such a setting operation is restricted by the scanning signal SCAN so that it is not performed in the normal reading mode even during the period when the frame signal FGATE is being output (see FIG. 5). Yes, inverters 51 and 52 and an AND gate 53 are provided as shown in FIG.

By the way, FIG. 4 shows the voltage relationship at the time of input / output of the A / D converter 40 and the input of the white reference plate in the three modes of dark, normal and light. In the figure, V _IN (W) is the input voltage to the A / D converter 40 when reading the white reference plate, V _REF
(D), V _REF (N) and V _REF (L) are reference voltage values (full scale value of image signal) to be obtained in the dark, normal and light modes, respectively.

Here, the operation according to the present embodiment will be described in more detail. The operation is the same in any of the dark, normal, and light modes, and therefore the description will be made by taking the light mode as an example. First, when the white reference plate is read, the waveform data after the shading correction as shown in FIG. 3 is input to V _IN for the A / D converter 40. When the reading is started, the down counter 46 sequentially counts down from the preset counter initial value. At this time, since A <B in the write comparison circuit 44,
The output state is L level. Therefore, the latch circuit 49 is not yet latched, and the enable terminal EN of the down counter 46 is
The countdown operation proceeds with BL kept at H level. Then, when the operation progresses and the write output data limit value PRL and the output data V _OUT match for only one pixel, or the output data V _OUT side slightly exceeds, the write comparison circuit 44 sets the H level. Signal is output. Then, the latch circuit 49 maintains the H level state. That is, the stop signal is output to the down counter 46 (= enable terminal ENBL is at L level)
Therefore, the down counter 46 stops the counting operation and maintains the count value at that time. In other words, considering FIG. 4, it means that the slope of the characteristic line as shown by the solid line initially becomes steep gradually with the countdown by the down counter 46 and becomes the write mode characteristic line state. (The same applies to other normal modes and dark modes).

Such processing will be considered more specifically with reference to FIG. In the figure, ADmax is the maximum output of the A / D converter 40 = full scale = 255 (= 11111111 = FF _H ). Also,
The output data limit value for write mode is PRL = 120 (By the way, it is actually set as PRL = 255, PRN = 253, PRD = 239), and V _RFE max shown by the broken line is the A / D converter 40. The maximum value of the down counter output DCo (=
(Initial value = 255). Then, when the output of the down counter 46, and accordingly the reference voltage signal to the A / D converter 40, fluctuates from the broken line state together with the down counter, and PRL = V _IN (W) as shown by the solid line state, The reference voltage value is the reference voltage value V _REF (L) for _writing .
In this way, by holding the digital value, the reference voltage of the A / D converter 40 is determined.

Then, for example, when reading an actual document image, etc., A /
An example of an analog waveform output from the D converter 40 is shown in FIG. FIG. 7 shows a state in which one line reading includes four lines as image data A, B, C, D. However, since the output data limit value PRL corresponding to the reference voltage in the write mode is 120 with respect to the full scale 255, the data of 120 to 255 is regarded as a white image, and the data of the level of 0 to 120 is the actual image data. Becomes In the case of FIG. 7, the image data A and C are made white, while the image data B and D are processed as valid image data and become data of a certain gradation.

According to the reference voltage determination method of the A / D converter 20 of the present embodiment, the maximum initial value V _REF max to be given as the reference value first, as can be seen from FIG. 6 (or FIG. 4). _May be a value higher than the reference voltage V _REF (D) for the dark mode. Considering such a point, the initial reference voltage by the D / A converter 27 is fixed to an appropriate value, and the preset reference value V _REF (for dark mode) is set by presetting the initial value of the down counter 26. It only needs to approach D) and does not require manual adjustment. At this time, since it is a digital processing by a logic system, it is less susceptible to the influence of noise and the like as compared with the peak hold or sample hold method in the analog system, and the output, and accordingly the system stability is excellent.

Next, a second embodiment of the present invention will be described with reference to FIGS. This embodiment is a modification of the above embodiment. First, to summarize the above-described embodiment, the reading density range is automatically set by changing the voltage value of V _{REF +} of the A / D converter 40. Therefore, until the digital output value reaches the set value, V _{REF +}
Is to be gradually increased. Therefore, depending on the step (raising range), it may be necessary to repeat the process many times until it matches the set value.

The present embodiment improves such a point. FIG. 8 shows a basic structure therefor, and the same parts as in FIG. 15 are designated by the same reference numerals. Explaining in comparison with Fig. 15, A / D
For the converter 29 (same configuration as the A / D converter 3 shown in FIG. 11), in addition to the shading correction circuit 31, a peak hold circuit (= maximum value detection) as means for detecting the range of digital output values. Circuit) 60 and a digital / analog multiplier (D /
A converter) 61 and. In the figure, the broken line shows the path for reading the shading data, and the solid line shows the path for normal reading.

Here, the D / A converter 61 functions similarly to the D / A converter used in the shading correction circuit 31, and the analog input V _H , V _L , the digital input ΣD _i, and the analog output A _{Between OUT} There is a relationship. Now, if _VL is ground GND and _VH is Vcc with a resolution of 8 bits, the above formula becomes Becomes

An outline of the operation in such a configuration will be described. First, A / A is read at the beginning of each reading of the shielding data where the reading position is located at the position of the white reference plate and the normal reading.
The voltage value of V _{REF +} of the D converter 29 is set to a certain value. The peak hold circuit 60 detects the maximum value of the digital output of one line obtained by this. Then, the voltage value of V _{REF +} of the A / D converter 29 is reset through the D / A converter 61 so that the maximum value of this digital output becomes the full scale of the A / D conversion.

More specifically, first, the digital input of the D / A converter 61 is set to full scale (2
55). As the voltage value of V _{REF +} of the A / D converter 29, the voltage Vcc set sufficiently higher than the level of V _IN is input as it is from the above equation. In this state, read the white reference plate and
Convert to D. The peak hold circuit 60 holds the maximum digital output in one line, and is specifically constructed as shown in FIG. That is, a latch 62 such as LS374 and L
It is composed of magnitude comparators 63 and 64 based on S85 and the like. This compares the output of the latch 62 with the digital output from the A / D converter 29, and rewrites the data of the output of the latch 62 only when the digital output from the A / D converter 29 side is larger. . In this way, the maximum value up to now is always held in the output of the latch 62. In the next line, the maximum value is input from the latch 62 to the digital input of the D / A converter 61. Now, assuming that the maximum value is ΣPi, the voltage value of Vcc · ΣPi / 255 appears at A _OUT from the above formula. This is V
It is the voltage value applied to _{REF +} and also the maximum value for one line of V _IN . For example, the maximum value is full scale
Assuming that 1/2 is 128, the voltage value of V _{REF +} is reset to Vcc / 2, which is the maximum value of V _IN . Therefore, the first
4 V _IN at the time of shading correction shown in Fig.
An ideal relationship with V _{REF +} is obtained. In this state, the shading data is read and stored in the RAM 30. The same applies to resetting V _{REF +} during normal reading. The white reference plate is read in the first line, the peak hold circuit 60 detects the maximum digital output, and the normal value shown in Fig. 14 (b) is read. V _IN and V _{REF +} at the time of reading (= after shading correction)
Get an ideal relationship with. The reading of the document image may be performed in such a state.

In this embodiment, the peak hold circuit 60 is used to detect the range = upper limit of the digital output value, but the A / D converter 29
If the minimum value detection circuit that detects the lower limit of the digital output based on the reading of the black reference plate is connected to the lower reference terminal V _REF- , the lower limit value for A / D conversion is automatically adjusted. Can be set.

In any case, according to the present embodiment, the reference voltage of the A / D converter 29 can be automatically set, the time and effort required for setting the analog input voltage V _IN can be saved. The reference voltage can be automatically corrected even when the range to be obtained changes. In particular, by always automatically setting such a reference voltage setting within a range that the analog input voltage V _IN can take, the gradation of digital output can be used most effectively. Furthermore, such automatic resetting of the reference voltage can be performed in the shortest possible time, and compared with the method of gradually changing until the set value is matched as in the first embodiment, You can eliminate time waste.

Effect As described above, the present invention detects a match between a plurality of predetermined values corresponding to a plurality of desired densities and an output value from the A / D conversion means, and generates one selected detection result. Means and a reference value changing means for changing the reference signal one after another at the start of reading by the reading means and stopping the change of the reference signal when the detection result is output from the generating means. Since the reference signal for A / D conversion is determined, it is possible to automatically set the reference signal for A / D conversion that can eliminate the instability of the system when the output fluctuates due to noise etc. Moreover, the gradation of the digital output is most effective, and it is possible to deal with the fluctuation of the analog input voltage, and the processing can be performed in a short time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG.
Figure is a block diagram of a part of it, Figure 3 is a timing chart, Figure 4 is a characteristic chart, Figure 5 is a timing chart, Figure 6 is a characteristic chart, Figure 7 is an analog waveform chart, and Figure 8 is a book. A block diagram showing a second embodiment of the invention, FIG. 9 is a block diagram of its peak hold circuit, FIG. 10 is a schematic block diagram of a general image scanner, and FIG. 11 is its A / D converter. Block diagram, FIG. 12 is an analog circuit diagram showing a conventional example,
FIG. 13 is a schematic side view of a conventional reading section, FIG. 14 is a digital output characteristic diagram, FIG. 15 is a block diagram, and FIG. 16 is a circuit diagram showing reference voltage setting. 29 ... Analog / digital converter, 40 ... Analog / digital converter, 41 ... Comparison circuit, 45 ... Control means, 46 ...
… Counter, 47 …… Digital / analog converter, 60 ……
Digital output value range detection means, 61 ...... reference voltage input resetting means

Claims (1)

(57) [Claims] 1. A reading means for reading an original image, a density reference plate facing the reading means, and an A / D converting means for A / D converting an image signal read by the reading means according to the reference signal. , An image full-scale determination device that determines the reference signal so that the image signal when the reading unit reads the density reference plate is A / D converted at the full scale of the A / D conversion unit, Generating means for detecting a match between a plurality of predetermined values corresponding to the density of the output and the output value from the A / D converting means, and generating one selected detection result; An image full-scale determining apparatus, comprising: a reference value changing unit that changes signals one after another and stops changing the reference signal when a detection result is output from the generating unit.