JP2921837B2 - Image reading device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to an image scanner, a digital copying machine, a facsimile, and the like, and particularly relates to a document reading apparatus characterized by signal processing for an image reading signal.

(Prior art)

FIG. 7 shows an analog processing circuit of an image scanner according to a conventional example.

The optical image of the document formed on the light receiving surface of the CCD1 is read by the CCD1. When a timing pulse P for transfer and shift is applied to the CCD 1, a read image signal output OS and a dark output DOS are output. The OS and DOS are differentially amplified by the buffer 2 to become image signals from which reset noise and the like of the CCD 1 have been removed. However, since it is still a pulse signal and has a DC offset, zero clamp is first performed by the switch SW1. This is to determine the 0 level of the image signal, and is usually performed by turning on the switch SW1 at a timing immediately after the CCD reset pulse. Further, switch SW2 and capacitor C _S
Perform sample hold. This turns ON switch SW2 only at the timing when the CCD output is (proportional to the reflectance of the original) image level shows correctly, so as to Chiyaji the capacitor C _S. The next FET3 is connected to the capacitor C _S
This is a buffer for receiving the voltage at high impedance, and becomes the analog image signal based on 0V for the first time as the source output of FET3. This is further set to a predetermined voltage level by the amplifier A1 and supplied to the reference voltage terminal rf of the D / A converter 4. The digital input of the D / A converter 4, is given a Shiedeingu correction data SDATA to be described later, as the output _{V DA, V DA ∞V 0 ×} SDATA is given.

In the A2 and A5 stages, to compensate for the dark current output DOS of the CCD1, a signal that turns ON only at the timing of the dummy pixel of CCD1 (a light-shielded pixel outside the effective pixel and outputs only the dark current component) samples and holds the dark current component with DS, performs a process of subtracting it from the image signal V _DA. A
As the output V _IN 2, a true analog image signal from which the dark current component of CCD 1 has been removed is obtained.

On the other hand, at the timing when the CCD 1 reads the white reference plate portion, the white reference output is sampled and held by the WS signal which is turned on, and the voltage whose level is adjusted by A3 and the variable resistor VR is obtained as the reference voltage Vref. The reference voltage Vref determines the full scale of the image signal. In the next stage, the reference voltage
Image clock V based on V _IN with Vref as reference (full scale)
A / D conversion is performed by the A / D converter 5 in synchronization with CLK. A digital image signal can be obtained for the first time as an A / D output. This A /
The D output is subjected to data conversion in the ROM 6 to obtain VDATA.

Digital image signal VDAT obtained by the above process
A is a line synchronization signal (LSYNC) and image clock (CLK) after processing such as MTF correction and density conversion as necessary.
Is output from the image scanner.

In the conventional example described above, a CCD including a pulse waveform is used.
Since the analog image information is latched in analog from the output based only on the timing based on the timing to generate an analog image signal, the following problem occurs.

(1) Ringing due to pulse voltage occurs, and this is CC
It goes into the image signal part of D output.

(2) The timing of sampling the image signal portion and the timing of zero clamping are very small, and there is a risk that the ringing of the item (1) will be caught.

(3) Slight jitter of clock pulse for sample timing and zero clamp timing (temporal fluctuation)
However, this leads to fluctuations in the amplitude of the obtained analog image signal.

All of the above problems appear as noise components on the analog image signal and significantly degrade the S / N ratio of the image data. In order to reduce this, it is necessary to consider a low-pass filter, matching of transmission impedance, and the like. However, this causes the complexity of the circuit, and also causes the deterioration of the image frequency characteristic as a side effect.

〔Purpose〕

The present invention has been made in view of such a point, and an object of the present invention is to provide an image reading apparatus that outputs an image signal from an image sensor as high-quality image data without noise.

〔Constitution〕

In order to achieve the above object, the first means is an image reading apparatus which reads an image with an image sensor and outputs image data in accordance with an image clock, and which responds to an AD clock which is sufficiently fast with respect to the image clock. A / D conversion means for A / D converting and outputting a signal output from the image sensor at a timing, and a signal output from the A / D conversion means during a period in which a 0 level of the output of the image sensor occurs. A first holding unit for accumulating a predetermined number of signals and holding a result of the operation, and a second holding unit for holding a signal output from the A / D conversion unit during a period when an image signal is generated from the image sensor. Holding means, and calculating means for calculating an output from the first holding means and an output from the second holding means, and outputting image data at a timing corresponding to the image clock. And wherein the door.

Further, the second means is an image reading device which reads by an image image sensor and outputs image data in accordance with an image clock, wherein the image sensor outputs the image data at a timing sufficiently high with respect to the image clock in accordance with an AD clock. A / D conversion means for A / D converting and outputting the output signal, and a first holding means for holding the signal output from the A / D conversion means during a period in which the 0 level of the output of the image sensor is generated. Holding means, and a second holding means for accumulating a predetermined number of signals output from the A / D conversion means during a period in which an image signal is generated from the image sensor and holding a calculation result, A calculating means for calculating an output from the first holding means and an output from the second holding means, and outputting image data at a timing corresponding to the image clock.

In the following embodiments, the image sensor in each of the above means is a CCD, the A / D conversion means is an A / D converter, the first holding means is a latch L1, and the second holding means is a latch L2. ,
The arithmetic means corresponds to the subtractor SUB1 and the latch L3, respectively. The image clock is input to VCLK input to the latch L3, the image data is input to VDATA, and the high-speed AD clock is input to the A / D converter.
The output of the first holding means corresponds to DATA, and the output of the second holding means corresponds to SDATA. Further, the first and second holding units are configured to hold the outputs (operation results) from the adder ADD and the latches LCH1 and LCH2.

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First, FIG. 5 shows an internal circuit of a CCD [TCD105C (Toshiba)] as an image sensor used in the document reading apparatus according to the present invention. FIG. 6 shows the drive pulse timing of the CCD.

The photocurrent generated by the photodiode of each pixel is stored in the storage electrode, and when the shift pulse SH is applied, the stored charges of all the pixels are transferred to the analog shift register. In the shift register, the charges are sequentially transferred by transfer clocks 01 and 02 and sent to an output unit. The output unit converts the electric charge of each pixel into a voltage and sequentially outputs the voltage from the OS terminal. The output unit has a reset function, and applies a reset pulse RS to eliminate the mixture between pixels.

The actual CCD output waveform is as shown by OS in FIG.

First, during application of the reset pulse RS (t _r ), a component called reset noise is mixed. t _r period tz immediately after the because the output unit is empty, but representative of a zero level of the image signal actually has a level of the DC offset voltage V _DC1. Thereafter, an image signal appears by the transition of 01 and 02. This image signal is generated in the negative direction, and its amplitude v ₀ is proportional to the accumulated charge amount of the pixel. This v ₀ is the image signal you want to retrieve. Thus, the CCD output OS has a waveform in which a pulse-like voltage is mixed in the analog image signal level. Also this CC
D has a compensation output DOS. This is an output from the dummy output section, and has a DC offset V at almost the same level as OS.
_{Has DC2} and reset noise levels. However, no image signal is output.

As described above, the CCD output contains many pulse-like components, and it is necessary to accurately extract image information (v _{0 in} FIG. 6) therefrom.

In the present invention, an image signal is extracted from such a CCD output (OS) by completely digital processing, and furthermore,
The digital signal conversion of the analog image signal by the CCD is performed at the same time, so that an image signal with an excellent S / N ratio can be obtained.

FIGS. 1 (a) and 1 (b) show an image data extraction circuit block from an image sensor output according to one embodiment, and FIGS. 2 (a) and 2 (b) show timing diagrams thereof.

In FIG. 1A, the CCD output OS and the compensation output DOS
Are input to the impedance conversion circuit of the emitter follower by the transistors Tr1 and Tr2, respectively. This is CC
The influence of the impedance and the influence of the transmission line inside D is reduced, and may not be necessary depending on the situation.
The OS directly inputs the output of Tr1 to the analog input terminal V _IN of the A / D converter (A / D). DOS side samples and holds the output of Tr2 at the timing pulses ZSP, giving one of the V _RT of the reference voltage terminal of the A / D. ZSP may be given at a timing other than the timing at which the reset noise of DOS is generated, and the margin for the timing variation is sufficient. A constant reference voltage Ref is applied to the other reference voltage terminal V _RB of the A / D. A / D
Means that A / D conversion of V _IN is performed with reference to V _RT −V _RB . Here, as the clock ADCLK for A / D conversion, a clock having a speed sufficiently higher than the CCD transfer clock (01, 02) is used as shown in FIG. 2 (b). If so the timing basis is at least occurred in the period of t _a and t _z shown in FIG. 6 need not be synchronized with the particular CCD transfer clock. Since the A / D output obtained in this way is compensated by DOS, the influence of the DC offset component included in the CCD output is removed to some extent. However, since it is not perfect (V _DC1 and V _DC2 shown in FIG. 6 are not completely the same), the next zero clamp and sample hold processing is performed. However, digital processing can be performed instead of the conventional analog processing.

The zero clamp pulse ZCP is generated immediately after the reset pulse RS and immediately before the change of 01 and 02. That is, this period t
_This is because a zero level of the CCD output occurs at _z (see FIG. 6). The A / D output is latched to the latch L1 by the ZCP.

After Subsequently 01, 02 transition, the image signal is appearing period t _a of FIG. 6, the sample pulses SCLK is generated substantially at the center of the period t _a, to latch the A / D output latch L2. At this point, the image signal SDATA is applied to L2, and the zero level ZDATA is applied to L1.
Are each latched. Next, by the subtractor SUB1
SDATA-ZDATA is calculated, and the result is latched on the latch L3 by the image clock VCLK. VCLK is a pulse that rises when both SDATA and ZDATA rise, and is given as one pulse per CCD pixel (see the timing chart shown in FIG. 2B). L3 output VDATA1 is CCD
The electrical offset has been removed, and the pulse signal has also been removed from the image signal. However, there is still a problem of dark current of the CCD. This is a CCD output generated even when the CCD is not irradiated with light, and has a considerably strong temperature characteristic. This correction is similar to the concept of the conventional analog processing, and the image data VDATA1 is latched at the latch L4 at the timing of the dummy pixel of the CCD to obtain dark current data DRK. Then, by subtracting DRK from VDATA1 by the subtractor SUB2, image data VDATA2 in which the dark current component has been corrected is obtained. The shading correction shown in FIG. 11B is different from the case of analog processing.

The shading mode signal FSHD becomes active with respect to the reference white plate which the CCD reads before the document (it goes to the low level in FIG. 1 (b)).

As a result, the three-state gate G is turned on and the memory RAM is in the write mode, and VDATA2 at that time is stored in the RAM in accordance with the dot address DA. When the shading mode ends and the FSHD returns to the high level, the normal reading mode is set, G is OFF, and the RAM is in the reading mode. That is, the stored white board read data SHDATA is read in accordance with the dot address, and applied to the address of the ROM 1 for shading correction together with the image data VDATA2. ROM1
In the table, data corrected for non-uniformity at the time of reading a white board is written, and output according to the address.

VDATA3 is image data that has undergone such shading correction. ROM2 is density conversion, gradation conversion (r conversion)
And the like in accordance with the selection signal SLD.

As described above, it has been shown that all functions for extracting true image data from a CCD output signal which has been conventionally processed in an analog manner can be digitally realized. The advantages of using digital processing are as follows: (1) Operational amplifiers, transistors, and FETs for analog processing
Temperature characteristics compensation, offset voltage compensation, etc., and proper biasing can be avoided. (2) The noise margin can be increased. (3) The higher the speed, the more the selection of analog elements is limited. Digital devices are relatively easy (general purpose) for high-speed use. (4) Since digital data is digital data, storage is easy, and noise removal function by averaging and the like can be performed with frequency characteristics (resolution). ) Can be performed without deterioration.

By the way, the actual CCD output often includes pulse-like random noise, ringing due to a transient, waveform rounding, etc., instead of the waveform schematically shown in FIGS.

In such a case, in a zero clamp or a sample hold, a sample signal obtained by a slight shift of the sample timing varies, and a portion having much noise may be sampled. In addressing this problem, conventional analog processing methods
In order to provide a smoothing effect, a low-pass filter is used to cope with such a problem. However, any of these causes deterioration of frequency characteristics (reduction of horizontal resolution).

The digital method according to the present invention can easily cope with this.
An example is shown in FIG. 3 and FIG.

FIG. 3 shows a block diagram of an example in which the zero clamp portion of FIG. 1 (a) is improved. However, the same method can be applied to the sample hold portion and the like. FIG. 4 shows the timing chart. The output of the A / D is supplied to the A input of the adder ADD, and the output ZL2 of the latch LCH2 is supplied to the B input. As a result, A + B is obtained at the output S of the ADD, which is latched to the latch LCH1 at a predetermined timing. LCH1 output
ZL1 is provided to LCH2 and latched again.

FIG. 4 shows this state, and it can be seen that the accumulated value of the A / D output is obtained as ZL1.

When a predetermined number of AD outputs are accumulated, a zero clamp pulse ZCP is generated, and the accumulated value is latched on a latch L1. The output of L1 is ZDATA, as in FIG.
It is given to UB1 and subjected to a subtraction process together with SDATA obtained in the same manner. In L1, if the accumulated value is latched as it is, the number of bits increases as compared with the output of the A / D. Therefore, the lower bits may be dropped and the average value may be used.

As described above, the averaging effect within one pixel can be obtained by the accumulation operation, so that the transient and noise components included in the CCD output can be removed, and the processing is completed within one pixel by the digital operation. Therefore, the frequency characteristics do not deteriorate.

Such an arithmetic processing can be applied not only to the zero clamp section but also to the sample data hold of image data, and the dark current detection and correction. In the above description, an example of the average value processing is shown, but processing for detecting the maximum value or the minimum value may be performed.

The timing pulses ZLC1, ZLC2, ZCP, etc. in FIG.
A pulse synchronized with the / D conversion clock ADCLK [FIG. 2 (b)] must be used, and the phase must be in an appropriate relationship with the CCD output OS [FIG. 2 (b)].

Therefore, ADCLK, image clock VCLK and CCD drive pulse
It is desirable that the frequencies of 01, 02, etc. all have an integer relationship. For example, the frequency of ADCLK may be divided to generate VCLK, 01, 02, and the like.

If ADCLK can be performed at a speed 10 times or more higher than VCLK, for example, it is not necessary to divide the frequency, but it is necessary to precisely control the phase of the timing pulse for each process with respect to the CCD output.

〔effect〕

According to the present invention, it is possible to provide an image reading apparatus that outputs an image signal from an image sensor as high-quality image data without noise.

[Brief description of the drawings]

FIGS. 1 (a) and 1 (b) are block diagrams of main parts of a document reading apparatus according to an embodiment of the present invention, and FIGS.
(B) is a timing chart showing the operation of the original reading apparatus, FIG. 3 is a block diagram showing an improved example of the zero clamp section, FIG. 4 is a timing chart thereof, FIG. 5 is an internal circuit diagram of the CCD, and FIG. FIG. 6 is a timing chart of the driving pulse, and FIG. 7 is a diagram showing an analog processing circuit of an image scanner according to a conventional example. 1 ... CCD, A / D ... A / D converter, L1, L2, L3, L4 ... Latch, SUB1, SUB2 ... Subtractor, G ... Gate, ROM1, ROM2 ...
… Read only memory, RAM …… Random access memory.

Claims (2)

(57) [Claims] 1. An image reading apparatus for reading an image by an image sensor and outputting image data in accordance with an image clock, wherein the image data is output from the image sensor at a timing corresponding to an AD clock which is sufficiently fast with respect to the image clock. A / D conversion means for A / D-converting and outputting the output signal, and during a period in which the 0 level of the output of the image sensor occurs, a predetermined number of signals output from the A / D conversion means are accumulated, A first holding unit that holds a result of the calculation; a second holding unit that holds a signal output from the A / D conversion unit during a period when an image signal is generated from the image sensor; Image reading means for calculating an output from the holding means and an output from the second holding means, and outputting image data at a timing corresponding to the image clock. Taking device. 2. An image reading apparatus which reads an image with an image sensor and outputs image data in accordance with an image clock, wherein the image data is output from the image sensor at a timing corresponding to an AD clock which is sufficiently fast with respect to the image clock. A / D conversion means for A / D converting the output signal and outputting the first signal, and a first holding means for holding the signal output from the A / D conversion means during a period when the 0 level of the output of the image sensor is generated. Means, during a period when an image signal is generated from the image sensor, a predetermined number of signals output from the A / D conversion means are accumulated,
A second holding unit for holding a result of the operation, an operation of calculating an output from the first holding unit and an output from the second holding unit, and outputting image data at a timing corresponding to the image clock And an image reading device.