JP2669116B2 - Signal processor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a signal processing device that temporarily stores an input signal, processes the signal in a form suitable for a communication mode, and outputs the signal. The present invention relates to a signal processing device provided with a relief measure.

[Conventional technology]

Conventionally, in a communication device, signal processing such as replacement of a time slot of a transmission signal is performed.
dom Access Memory), an operation of temporarily storing the input signal in the RAM and reading the input signal in a desired order is performed.

For example, as shown in FIG. 3, a pair of RAMs 1 and 2 for storing an input signal and a pair of RAMs
A switch 3 for switching between the RAMs 1 and 2; a switch 4 for switching the output from the RAMs 1 and 2; an address counter 5 for controlling addresses in the RAMs 1 and 2;
It is composed of a circuit 6 composed of M (Read Only Memory) and the like, which controls an input side or output side address according to a prewritten procedure, and a switching circuit 7 which switches between writing and reading with respect to the RAMs 1 and 2. There is.

In this signal processing device, the input signal is written and stored in the RAMs 1 and 2 and read out in a required order,
A required signal can be output. At this time, a pair of
By operating the RAMs 1 and 2 complementarily in the writing / reading mode at regular intervals (for example, the frame period of the transmission signal), continuous processing can be performed.

[Problems to be solved by the invention]

In a signal processing device using such a storage element, the reliability of the signal processing device decreases in proportion to the number of cells of the storage element. Therefore, it is particularly necessary to monitor the failure of the storage element.

As a fault monitoring means, a parity check method in which an input signal and an output signal are counted by counting the number of 1s or 0s in a fixed period and compared, or by inserting a known monitoring pattern into a part of a transmission signal Means for issuing an alarm or switching to a spare circuit in the event of a failure using a method of checking the output at an output point is employed.

However, there is a problem that the communication device becomes unusable until the repair is performed only by issuing an alarm. In addition, there is a problem in that the apparatus having the spare configuration requires the same configuration, and thus the apparatus becomes expensive.

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal processing apparatus which operates a device to secure communication even when the device does not have a spare configuration and until repair is performed.

[Means for solving the problem]

The signal processing device according to the present invention includes a storage element for storing an input signal, which is composed of a pair of a working signal storage area and a working monitoring area, and another pair of a spare signal storage area and a protection monitoring area. It has a storage area and is configured to store input signals in the four storage areas simultaneously. A means for selecting one of the working signal storage area and the spare signal storage area; a means for selecting one of the working monitoring area and the spare monitoring area; and the paired storage selected by the selecting means. Means for comparing the output read from the area or the output read from the other pair of storage lily bit by bit, and an input corresponding to the bit by operating each of the selecting means when there is a mismatch. A configuration is provided including means for changing the storage area of one pair storing signals to the storage area of the other pair.

[Action]

According to the present invention, a failure can be detected by comparing the signals stored in the two storage areas of the active system, and in that case, the storage area is instantly changed by changing the storage area to the two storage areas of the standby system. It is possible to switch to the standby system.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of the first embodiment of the present invention. In the figure, RAM11 is divided into four areas,
Input ports PI1 to PI4 and output ports PO in each area
1 to PO4 are provided. The four areas are paired for the active system and the standby system, respectively, and include an active signal storage area A1, an active monitoring area A2, an auxiliary signal storage area A3, and an auxiliary monitoring area.
A4, and each area is provided with an address up to address N. The input signals are simultaneously input to the input ports PI1 to PI4 of each area.
In addition, each output port PO1-PO4 is a switch between working and standby.
It is configured to be selectively switched by 12A and 12B.

An address counter 13 that repeats at the frame period of the input signal and an EEPROM (Electrical Erasable) in which an address conversion table for replacing time slots is written.
PROM), and a comparison circuit 15 that compares the output signal and the monitoring signal with each other, and generates a control pulse to the address control circuit 14 when they do not match.
It has.

According to this configuration, an input signal is simultaneously input to the four input ports PI1 to PI4 of the RAM 11. Address counter 13
Sequentially generates addresses that repeat at the frame period of the transmission signal, and the input signal is stored at the same address in each area in order from address 0 in each of four areas for one frame.

When the writing of one frame is completed, the address of the RAM 11 is switched to the reading side. This address is generated by the address control circuit 14. Then, signals written simultaneously to the areas A1 and A2 are output to the output ports PO1 and PO2, respectively. A normal signal is read and output from the switch 12A, and a monitoring signal is read and output from the switch 12B. And both outputs are comparison circuits
15 are successively compared, and when they match, the signal is output as it is.

On the other hand, when they do not match, a control pulse is generated to output the mismatched address to the address control circuit 14. The address control circuit 14 receives this control pulse, and thereafter outputs an output port for the address.
Switch from PO1, PO2 to PO3, PO4. At the same time, switch 12A,
12B is also switched to output signals from the standby output ports PO3 and PO4 correspondingly.

In this embodiment also, as in the conventional case, a pair of RA
Since M is continuously operated by operating the write / read mode complementarily at regular intervals (for example, the frame period of the transmission signal), the RAM 11 and the switches 12A, 12B shown in FIG. Needless to say, there is another.

FIG. 2 is a block diagram of a second embodiment of the present invention, in which parts equivalent to those of the first embodiment are denoted by the same reference numerals.

In this embodiment, the RAM 11A has four addresses from 0 to M.
After dividing into one area A1 to A4, one input port PI
And it has only one output port PO and the output signal is RAM11A
The latch circuit 16 is configured to latch the output of the above. In addition, 13 is an address counter that repeats at the frame period of the transmission signal, and 14 is an EE in which an address conversion table for time slot replacement is written.
An address control circuit composed of a PROM, 15 is a comparison circuit that compares the outputs of the signals stored twice and generates a control pulse when they do not match, and 17 is a latch timing generation circuit that controls the latch timing. .

In this embodiment, since the port of the RAM 11A has only one port for input and output, the input signal is applied to the four areas A of the RAM shown in FIG.
The same signal is written in 1 to A4 at a speed four times as high as the input signal speed. Further, the address counter 13 sequentially generates addresses repeated at the frame period of the transmission signal at four times the speed of the input signal, and the input signal is sequentially written twice from the address 0 to the active area for one frame. In addition, it is also written in the spare area twice.

When one frame is written, the RAM address is switched to the read side. This address is generated by the address control circuit 14. The double-written signal is output to the output port PO at a quadruple speed in the order of the current signal, the monitoring signal, the standby signal, and the monitoring signal. Normally, the output for the current signal and the output for monitoring are latched by the latch circuit 16 to obtain the output.

The two outputs are successively compared by the comparison circuit 15. If they do not match, a control pulse is generated to transmit the mismatched address to the address control circuit 14. Thereafter, the address control circuit 14 issues a latch timing generation circuit 17 so as to switch the output latch timing from the working state to the standby state for the address.
Control.

Therefore, in the event of a failure, the output for standby signal and the output for monitoring are latched by the latch circuit 16 to obtain an output.

Also in the present embodiment, a pair of RAMs are operated in a complementary manner in a write / read mode at regular intervals to perform continuous processing, and another RAM is present.

〔The invention's effect〕

As described above, the present invention is configured such that two storage areas each forming a pair are provided in a storage element, and input signals are simultaneously stored in these storage areas.
A failure can be detected by comparing the signals stored in the two storage areas of the active system, and in that case, the storage area is changed to the two storage areas of the standby system so that the switching to the standby system is instantaneous. It is possible to operate the device even when the device does not have a spare configuration and even before the repair is performed, thereby avoiding disconnection of communication, and obtaining an economical and highly reliable signal processing device. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the present invention, and FIG. 3 is a block diagram of a conventional signal processing device. 1,2 ... RAM, 3,4 ... Switcher, 5 ... Address counter, 6 ... Address control circuit, 7 ... Switching circuit, 11, 11A
… RAM, 12A, 12B… Switcher, 13… Address counter, 14… Address control circuit, 15… Comparison circuit, 16…
Latch circuit, 17 ... Latch timing generation circuit.

Claims (1)

(57) [Claims] 1. A signal processing apparatus comprising a storage element for storing a signal inputted in a fixed state, and outputting the stored signal in a predetermined state, wherein said storage element is a pair. It has a total of four storage areas consisting of a working signal storage area and a working monitoring area to be formed and a spare signal storage area and a spare monitoring area forming another pair, and is configured to simultaneously store input signals in the four storage areas. Means for selecting one of the working signal storage area and the protection signal storage area; means for selecting one of the working monitoring area and the protection monitoring area; and the pair selected by the selection means. Means for comparing the output read from the storage area or the output read from the other pair of storage lilia bit by bit; Signal processing apparatus characterized by comprising means for changing the storage area of one pair storing an input signal corresponding to the bit by work in a storage area of the other pair.