JP2666761B2 - Semiconductor wafer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer, and more particularly to an alignment mark used after a wiring process.

[0002]

2. Description of the Related Art In general, a semiconductor wafer is printed with a chip pattern on its surface by a moving exposure apparatus (stepper). An alignment mark is provided on a chip to be printed by the sequential exposure apparatus, and is used for alignment (alignment) when processing a semiconductor wafer.

There are two types of alignment methods, one for alignment on a semiconductor wafer basis and the other for chip alignment on a semiconductor wafer. The outline of each is described below.

(1) In the case of wafer alignment, several alignment marks on a chip region formed at an arbitrary position on a semiconductor wafer are measured. At this time, in consideration of the chip size, the design position of the alignment mark, the chip arrangement, and the like, for example, the orientation flat (hereinafter, referred to as the orientation flat) is set downward, and the top, bottom, left, right,
Measure the center 5 points. The positions of all chip regions on the semiconductor wafer are calculated by measuring the amount of displacement of each chip region and performing statistical processing. The advantage of this method is that measurement is not performed in units of chips, so that the number of times of alignment is small, and as a result, alignment can be performed at high speed. The disadvantage is that a high value is required for the positioning accuracy (minimum resolution, repetition accuracy, step feed accuracy, etc.) of the stage itself.

(2) In the case of chip alignment, alignment marks of all chip areas on a semiconductor wafer are measured. The amount of displacement of each chip area is measured, and the device recognizes the position of each chip area. The disadvantage of this method is that since the measurement is performed on a chip basis, the number of alignments is equal to the number of chip regions to be processed, so that the number of alignments increases, and as a result, alignment cannot be performed at high speed. The advantage is that a high value is not required for the positioning accuracy (minimum resolution, repetition accuracy, step feed accuracy, etc.) of the stage itself.

Further, as a specific alignment method, there is the following method.

(1) Irradiate the alignment mark with light,
A method of detecting the center point of the alignment mark based on the reflected light and performing positioning.

(2) irradiating the alignment mark with light,
A method of detecting and positioning the central axes of a plurality of alignment marks arranged based on the intensity of diffracted light from the alignment marks.

(3) A method of capturing an image of an alignment mark, detecting the minute displacement amount of the alignment mark by aligning the captured image with a previously stored image, and positioning.

Actually, regarding the shape of an alignment mark when performing chip alignment by reflected light, when performing reflected light alignment, as a design example of the mark shape, a laser beam is scanned in a scanning direction. It is necessary to have a dimension that is at least 1.5 times the diameter, and at least (accuracy when placing a semiconductor wafer on an apparatus stage + laser beam radius) in a direction perpendicular to the scanning direction. Considering the actual numerical values, the laser beam diameter is 3 μm,
± 1 accuracy when placing semiconductor wafer on equipment stage
If it is 0 μm, it will be a rectangle of 4.5 μm × 23 μm. Naturally, a preliminary value is added, so 4.5 μm × 23 μm
Dimensions exceeding

The alignment mark may be arranged on a circuit pattern in the chip area or on a scribe area around the chip area. An advantage of disposing the alignment mark on the scribe area is that a wider circuit area on the chip area can be secured. This is different if the circuit pattern in the chip area can be used when arranging the alignment mark.
This is to ensure a large circuit area on the chip area even if a little.

FIG. 5 is a partial plan view of a semiconductor wafer for explaining a first example of a conventional alignment mark.

As shown in FIG. 5, a grid-like scribe region 2 formed between the chip regions 1 arranged in a matrix extends radially on the center line 3 from the intersection 4 of each center line 3 of the scribe region 2. A cross-shaped alignment mark 21 is formed, and a central axis of the alignment mark is calculated from a signal of the alignment mark detected by a scanning beam that scans a laser beam in two directions of X direction 9a and Y direction 9b. The center point of the mark (in this case, coincident with the intersection of the center line 3 of the scribe area 2) is determined and used for alignment of the chip area 1 located at the shortest distance from this center point.

FIGS. 6A and 6B are schematic plan views for explaining the configuration of the alignment mark of FIG.

As shown in FIG. 6A, L-shaped alignment mark patterns 21a, 21b, 21c and 21d formed in association with the wiring forming patterns in each chip area are collected at the intersection of the center lines of the scribe area. As shown in FIG. 6B, a cross-shaped alignment mark 21 is formed by synthesis, and a free area 22 where no signal is generated by the laser light is formed in a portion of the alignment mark 21 which is in contact with the laser beam scanning directions 9a and 9b. Is provided.

FIG. 7 is a schematic plan view for explaining a method for detecting an alignment mark according to a first example of a conventional alignment mark.

As shown in FIG. 7, in order to determine where each chip region 1 is located with respect to the device, at least two alignment marks 21 formed on the chip region 1 are selected from the semiconductor wafer. It is necessary to measure its position. Two alignment marks 21
By measuring the position, the shift amount in the X direction, the shift amount in the Y direction, and the shift amount in the θ direction from the device coordinate reference point can be determined. When positioning the chip area 1a, the alignment mark 23 located at the upper left in the chip area 1a is scanned with laser light in two directions of the scanning direction 9a and the scanning direction 9b.
The reflection waveform is measured, the center of each of the alignment mark 23 in the X direction and the Y direction is obtained, and the intersection point is set as the measurement position of the alignment mark 23.
Scanning direction 9
The laser beam is scanned in the scanning direction 9a and the scanning direction 9b, the reflected waveform is measured, the center of each of the alignment mark 24 in the X direction and the Y direction is obtained, and the intersection point is set as the measurement position of the alignment mark 24. When the positions of the alignment mark 23 and the alignment mark 24 in the apparatus coordinate system can be measured, the amount of deviation in the X direction, the amount of deviation in the Y direction, and the amount of deviation in the θ direction from the apparatus coordinate reference point can be determined. Next, when positioning the chip area 1b, the alignment mark 24 located at the upper left in the chip area 1b is scanned with laser light in the scanning directions 9a and 9b, its reflection waveform is measured, and the X direction of the alignment mark 24 is measured. And the center of each in the Y direction are determined, and the intersection is defined as the measurement position of the alignment mark 24. Similarly, the laser beam in the scanning directions 9a and 9b is scanned over the alignment mark 25 located at the upper right in the chip area 1b, and the reflected waveform has a half of the width of the alignment mark 24 in the scanning direction 9a. , The center axis thereof is shifted by １ ／ of the width of the alignment mark 24.

Further, a reflected waveform in the scanning direction 9b cannot be detected. Therefore, the measurement position of the alignment mark 25 cannot be determined. Since there is no help for it, the chip area 1 obtained earlier
The chip size, which is a known value, is added or subtracted based on the measurement position of “a” to obtain the measurement position of the chip area 1b. In this case, since the measured amount of the chip region 1a is used as a reference, the chip region 1b
Position accuracy is inferior to the case where the above chip alignment is performed.

FIG. 8 is a partial plan view of a semiconductor wafer for explaining a second example of a conventional alignment mark.

As shown in FIG. 8, four corner vertices of a frame-shaped alignment mark 31 arranged so as to surround the intersection 4 of each center line 3 of the scribe area 2 are formed in contact with the vertices of the chip area 1. The center point 32 of the alignment mark 31 can be obtained in each of the divided areas 2a, 2b, 2c, 2d defined by the center line 3 of the scribe area 2, and one of the alignment marks 31 is located at the end of the array of the chip area 1.
Even if / 2 or 3/4 is missing, the center point of the alignment mark attached to each chip region 1 can be obtained, and there is an advantage that the accuracy of chip alignment can be maintained. However, as shown in FIG. There is a problem that the alignment mark 31 protruding from the dicing region 8 to be deleted at the time of division remains at the corner of the divided chip and comes into contact with the bonding wire to cause a short circuit.

[0021]

In the prior art semiconductor wafer, in the first example, when the alignment mark segment in the chip region arranged at the outermost periphery of the semiconductor wafer is insufficient, the center point of the alignment of that portion is detected. Since it cannot be performed, the center point estimated from the alignment center point of another part is calculated and processed, so that there is a problem that accuracy is reduced.

Further, in the second example, there is a problem that an alignment mark made of a metal film remaining by dicing comes into contact with a bonding wire to cause a short circuit accident.

An object of the present invention is to provide a semiconductor wafer on which an alignment mark is formed which does not lower the position detection accuracy even if a part of the alignment mark is insufficient due to the arrangement of the chip area and which can prevent a short circuit accident. is there.

[0024]

According to a first aspect of the present invention, there is provided a semiconductor wafer comprising chip regions arranged in a matrix and scribe regions formed in a grid pattern in regions sandwiched between the chip regions adjacent to each other. And an L-shaped first section formed along the center line in the vicinity of the intersection of the first sectioned area defined by each center line of the scribe area and having an apex angle relationship about the intersection of the center lines. A first alignment mark, and an I-shaped second alignment mark formed along each of the center lines of a second divided region orthogonal to the first divided region, and the first and second alignment marks are formed. Two alignment marks are arranged in a dicing area for dividing the chip area.

The second semiconductor wafer according to the present invention comprises: a chip region arranged in a matrix; a scribe region formed in a lattice in a region sandwiched between the adjacent chip regions;
A first alignment mark and an I-shaped second alignment mark, each of which is formed by a diffraction grating formed along each of the center lines in a divided area defined by each center line of the scribe area, and The first and second alignment marks are arranged and arranged in a dicing area for dividing the chip area.

[0026]

Next, the present invention will be described with reference to the drawings.

FIGS. 1A and 1B are partial plan views of a semiconductor wafer for explaining a first embodiment of the present invention, and FIGS.
FIG. 4 is a schematic cross-sectional view taken along line -A ′.

As shown in FIGS. 1 (a) and 1 (b), a center line 3 of a 100 μm-wide grid-like scribe region 2 formed in a region sandwiched between chip regions 1 arranged in a matrix. And formed along the center line 3 in the first regions 2a, 2c having an apex angle relationship centered on the intersection 4 of the divided regions 2a, 2b, 2c, 2d adjacent to each other at the intersection 4 of the center line 3. L-shaped alignment mark 5 and second region 2 having an apex angle perpendicular to first regions 2a and 2c
b and 2d are provided with an I-shaped alignment mark 6 formed along the center line 3. The alignment marks 5 and 6 are made of the same material as the metal wiring layer and are patterned and formed simultaneously with the patterning of the metal wiring layer. You. here,
Since an empty area is required in an area adjacent to the alignment marks 5 and 6 in the scanning direction of the laser beam for detecting the position of the alignment marks, the alignment marks 5 and 6 are required.
Are arranged out of phase.

The laser beam for detecting the position of the alignment mark is scanned along the X direction and the Y direction of the scribe area 2, and the signals obtained by scanning the widths of the alignment marks 5 and 6 are used. Each of the intersections 7a, 7b, 7c, 7d of the center line passing through the center of the width is detected and used for the alignment in the probing process, the repair process, and the dicing process.

As shown in FIG. 2, the alignment marks 5 and 6 are formed by grinding the scribe area 2 to divide the chip area 1 of the semiconductor wafer and forming a dicing area having a width of 60 μm for forming individual semiconductor chips (by dicing). The semiconductor chip divided by dicing prevents a short circuit with a bonding wire caused by a part of the alignment marks 5 and 6 remaining on the semiconductor chip divided by dicing.

FIGS. 3A and 3B are diagrams showing examples of the shape and size of the alignment mark according to the first embodiment of the present invention.

As shown in FIGS. 3A and 3B, the width 10
A free area 10 where no signal is generated by the laser light is provided in a portion of the μm L-shaped alignment mark 5 and I-shaped alignment mark 6 in contact with the laser light scanning directions 9a and 9b, and the free area 10 is scanned. The width of the alignment mark is read based on the signal at the time and the signal when the alignment mark 5 or 6 is scanned, and the center line thereof is detected.

FIG. 4 is a partial plan view of a semiconductor wafer for explaining a second embodiment of the present invention.

As shown in FIG. 4, similarly to the first embodiment, the divided area 2 divided by each center line 3 of the scribe area 2
In each of a, 2b, 2c, and 2d, an alignment mark 11 for a dicer formed of a diffraction grating and an I-shaped alignment mark 6 are formed along the center line 3, respectively. The center point 7 detected by the center line can be used for positioning of repair or the like. The center axis of the alignment mark 11 is detected based on the intensity of the diffracted light of the alignment mark 11, and the dicer is aligned.

[0035]

As described above, according to the present invention, the center point of the alignment mark can be accurately detected even in the alignment mark where a part of the segment is insufficient by being arranged at the outermost peripheral portion of the semiconductor wafer. In addition, there is an effect that a short circuit accident can be prevented by eliminating residual conductive alignment marks on the scribe region.

[Brief description of the drawings]

FIG. 1 is a partial plan view and a schematic cross-sectional view taken along line AA ′ of a semiconductor wafer for explaining a first embodiment of the present invention.

FIG. 2 is a plan view showing a positional relationship between dicing regions in FIG. 1;

FIG. 3 is a view showing an example of the shape and dimensions of the alignment mark of FIG. 1;

FIG. 4 is a partial plan view of a semiconductor wafer for explaining a second embodiment of the present invention.

FIG. 5 is a partial plan view of a semiconductor wafer for describing a first example of a conventional semiconductor wafer.

FIG. 6 is a schematic plan view illustrating the configuration of the alignment mark of FIG. 5;

FIG. 7 is a schematic plan view for explaining a method for detecting the position of an alignment mark according to a first example of a conventional semiconductor wafer.

FIG. 8 is a partial plan view of a semiconductor wafer for describing a second example of a conventional semiconductor wafer.

FIG. 9 is a plan view showing the positional relationship between the dicing regions in FIG. 8;

[Explanation of symbols]

1, 1a, 1b Chip area 2 Scribe area 2a, 2b, 2c, 2d Division area 3 Center line 4 Intersection point 5, 6, 11, 21, 23, 24, 25, 31 Alignment marks 7a, 7b, 7c, 7d, 32 Center point 8 Dicing area 9a, 9b Scanning direction of laser beam 10 Empty area 21a, 21b, 21c, 21d Segment

Claims (2)

(57) [Claims] 1. A chip area arranged in a matrix, a scribe area formed in a lattice shape in an area sandwiched between adjacent chip areas, and each center line of the scribe area, An L-shaped first alignment mark formed along the center line in the vicinity of the intersection of a first segmented region having an apex angle centered at the intersection of the center lines, and orthogonal to the first segmented region I-shaped second sections formed along each of the center lines of the second divided areas
Wherein the first and second alignment marks are arranged in a dicing area for dividing the chip area. 2. A chip region arranged in a matrix, a scribe region formed in a lattice shape in a region sandwiched between the chip regions adjacent to each other, and a section divided by each center line of the scribe region. A first alignment mark formed of a diffraction grating formed along each of the center lines in a region, and an I-shaped second alignment mark, respectively, and the first and second alignment marks are formed by the chip. A semiconductor wafer arranged in a dicing area for dividing an area.