CN113421874A - Wafer assembly - Google Patents
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- CN113421874A CN113421874A CN202110705726.5A CN202110705726A CN113421874A CN 113421874 A CN113421874 A CN 113421874A CN 202110705726 A CN202110705726 A CN 202110705726A CN 113421874 A CN113421874 A CN 113421874A
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- 235000012431 wafers Nutrition 0.000 description 119
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- 230000008569 process Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
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- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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Abstract
The invention provides a wafer assembly, comprising: a first wafer and a first alignment mark on the first wafer; a second wafer and a second alignment mark on the second wafer; at least one of the first alignment mark and the second alignment mark extends from the intersection region to the non-intersection region of the cutting channel on the wafer on which the first alignment mark and the second alignment mark are located. The length of the pattern (e.g., stripe pattern) in the first alignment mark and/or the second alignment mark may be greater than the width of the scribe line, and is no longer limited by the width of the scribe line. On the basis of the existing wafer bonding machine and the processing conditions, the invention can make the alignment mark with larger size under the condition of a certain width of the cutting channel, thereby improving the wafer bonding identification efficiency and precision.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a wafer assembly.
Background
In integrated circuit technology, three-dimensional integration (3D-IC) is a solution to improve chip performance while maintaining prior art nodes. The performance of the chips can be improved by three-dimensionally integrating two or more chips with the same or different functions, and meanwhile, the metal interconnection among the functional chips can be greatly shortened, and the heat generation, the power consumption and the delay are reduced. In the 3D-IC technology, the bonding process between wafers is a very critical technology, and the quality of the bonding process between two wafers determines the success of the whole process, wherein the alignment mark used in the bonding process plays a crucial role. Wherein the efficiency of identifying the alignment mark is the key focus of the production speed of the wafer-to-wafer bonding process.
In the current bonding technology between wafers, an alignment mark for wafer bonding is usually designed on a dicing channel, and in general, the larger the size of the alignment mark, the higher the recognition efficiency of a bonding machine and the higher the recognition accuracy. As the 3D-IC design scribe line width becomes smaller, the pattern size that must be left for alignment marks becomes smaller, thereby affecting wafer bonding recognition efficiency and accuracy.
Disclosure of Invention
The invention aims to provide a wafer assembly, which is characterized in that an alignment mark is reasonably arranged at the intersection of cutting channels, and the alignment mark with larger size is made, so that the wafer bonding identification efficiency and precision are improved.
The invention provides a wafer assembly, comprising:
a first wafer and a first alignment mark on the first wafer;
a second wafer and a second alignment mark on the second wafer;
at least one of the first alignment mark and the second alignment mark extends from the intersection region of the cutting channel to the non-intersection region on the wafer where the first alignment mark and the second alignment mark are located; and the second alignment mark is matched with the first alignment mark to achieve alignment of the first wafer and the second wafer.
Further, when the first wafer is aligned with the second wafer, the center of the second alignment mark and the center of the first alignment mark coincide with each other.
Further, at least one of the first alignment mark and the second alignment mark includes a bar pattern extending from the intersection region to the non-intersection region of the scribe line on the wafer on which the bar pattern is located.
Furthermore, the bar patterns are provided with characteristic patterns at intervals, and the characteristic patterns comprise at least one of circles, triangles, squares and diamonds.
Further, the pattern of the first alignment mark and/or the pattern of the second alignment mark are/is a rotationally symmetric pattern, and the rotational symmetry center of the rotationally symmetric pattern is located in the intersection region of the scribe line on the wafer on which the rotationally symmetric pattern is located.
Further, the first alignment mark and/or the second alignment mark comprise bar patterns distributed in the rotationally symmetric pattern, the bar patterns comprise bar patterns in a first direction and bar patterns in a second direction, and the bar patterns in the first direction extend from the intersection area of the cutting street in the first direction and the cutting street in the second direction to two sides of the cutting street in the first direction; the bar patterns in the second direction extend from the intersection region of the cutting street to both sides of the cutting street in the second direction.
Further, when the first wafer is aligned with the second wafer, the intersection area of the scribe lines of the first wafer at least partially coincides with the intersection area of the scribe lines of the second wafer.
Further, the first wafer and the second wafer both include transverse cutting streets and longitudinal cutting streets which are perpendicular to each other.
Furthermore, the width of the transverse cutting line and the width of the longitudinal cutting line are both in the range of 60-80 μm.
Further, one of the first alignment mark and the second alignment mark has a cross-shaped pattern, a cross-shaped area of the cross-shaped pattern is located in an intersection area of the cutting lanes, and a horizontal bar and a vertical bar of the cross-shaped pattern are distributed along the transverse cutting lanes and the longitudinal cutting lanes respectively; the other pattern includes alignment patterns distributed at the four corners of the cross pattern. Further, the alignment patterns are distributed in the crossing regions of the cutting lines or extend from the crossing regions of the cutting lines to the non-crossing regions.
Further, the alignment pattern is a triangular pattern extending from the intersection region to the non-intersection region of the scribe line.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a wafer assembly, comprising: a first wafer and a first alignment mark on the first wafer; a second wafer and a second alignment mark on the second wafer; at least one of the first alignment mark and the second alignment mark extends from the intersection region to the non-intersection region of the cutting channel on the wafer on which the first alignment mark and the second alignment mark are located. The length of the pattern (e.g., stripe pattern) in the first alignment mark and/or the second alignment mark may be greater than the width of the scribe line, and is no longer limited by the width of the scribe line. On the basis of the existing wafer bonding machine and the processing conditions, the invention can make the alignment mark with larger size under the condition of a certain width of the cutting channel, thereby improving the wafer bonding identification efficiency and precision. The invention is suitable for cutting channels with smaller size (width), namely, is suitable for the alignment marks of narrow cutting channels, improves the bonding precision and can obtain larger effective area of a chip.
Drawings
FIG. 1 is a schematic diagram of alignment mark matching on a wafer device.
FIG. 2a is a schematic view of a first wafer according to a first embodiment of the present invention.
FIG. 2b is a diagram illustrating a first alignment mark on a first wafer according to a first embodiment of the present invention.
FIG. 3 is a diagram illustrating a second alignment mark on a second wafer according to the first embodiment of the present invention.
FIG. 4 is a diagram illustrating the matching of the second alignment mark and the first alignment mark according to the first embodiment of the present invention.
FIG. 5 is a diagram illustrating the matching of the second alignment mark and the first alignment mark according to the second embodiment of the present invention.
FIG. 6 is a diagram illustrating the matching of the second alignment mark and the first alignment mark according to the third embodiment of the present invention.
FIG. 7 is a diagram illustrating the matching of the second alignment mark and the first alignment mark according to the fourth embodiment of the present invention.
FIG. 8 is a diagram illustrating the matching of the second alignment mark and the first alignment mark according to a fifth embodiment of the present invention.
FIG. 9 is a diagram illustrating the matching of the second alignment mark and the first alignment mark according to the sixth embodiment of the present invention.
Wherein the reference numbers are as follows:
01-alignment mark; 02-alignment mark; s-cutting a street; 1-a first wafer; 2-a second wafer; 11. 12, 13, 14, 15, 16 — first alignment mark; 21. 22, 23, 24, 25, 26-second alignment mark; p-feature pattern.
Detailed Description
As described in the background, as the scribe line width of 3D-IC designs becomes smaller, the pattern size that must be left for alignment marks becomes smaller, thereby affecting wafer bonding recognition efficiency and accuracy. Specifically, as shown in fig. 1, the wafer assembly includes two wafers, one wafer includes an alignment mark 01 thereon, the other wafer includes an alignment mark 02 thereon, and the alignment mark 01 and the alignment mark 02 are matched for alignment of the two wafers. The line width of the alignment mark 01 is b, the line width of the alignment mark 02 is a, and the line length of the alignment mark 02 is c. The width d of the scribe line S is smaller and smaller, and the line width a of the alignment mark 02, the line width b of the alignment mark 01, and the line length c of the alignment mark 02 need to be smaller than the scribe line width d, i.e., a + b + c is smaller than d. Therefore, the size of the cutting street width d is limited to be smaller, and the line widths (strip widths) and line lengths (strip lengths) of the alignment marks 01 and 02 are both limited to be smaller than the cutting street width d, so that the alignment marks are small, the identification is difficult, and the wafer bonding identification efficiency and precision are influenced.
Based on the above research, embodiments of the present invention provide a wafer assembly. The invention is described in further detail below with reference to the figures and specific examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted, however, that the drawings are designed in a simplified form and are not to scale, but rather are to be construed in an illustrative and descriptive sense only and not for purposes of limitation.
An embodiment of the present invention provides a wafer assembly, including:
a first wafer and a first alignment mark on the first wafer;
a second wafer and a second alignment mark on the second wafer;
at least one of the first alignment mark and the second alignment mark extends from the intersection region of the cutting channel to the non-intersection region on the wafer where the first alignment mark and the second alignment mark are located; and the second alignment mark is matched with the first alignment mark to achieve alignment of the first wafer and the second wafer.
The wafer assembly according to the embodiment of the present invention will be described in detail with reference to fig. 2a to 9.
FIG. 2a is a schematic view of a first wafer according to a first embodiment of the present invention. FIG. 2b is a diagram illustrating a first alignment mark on a first wafer according to a first embodiment of the present invention. FIG. 3 is a diagram illustrating a second alignment mark on a second wafer according to the first embodiment of the present invention. FIG. 4 is a diagram illustrating the matching of the second alignment mark and the first alignment mark according to the first embodiment of the present invention.
Specifically, as shown in fig. 2a to 4, the wafer assembly includes: the first wafer 1 and the second wafer 2 are not limited, and for example, a backside illuminated CMOS image sensor is taken as an example, the first wafer is, for example, a device wafer, the second wafer is, for example, a carrier wafer, where the type of the carrier wafer is not limited, and the carrier wafer may also be a device wafer, a wafer with interconnect function (RDL), or other various functional wafers. The first wafer 1 is provided with scribe lines in different directions, and the first wafer 1 includes, for example, transverse scribe lines a1-a1 'and longitudinal scribe lines B1-B1' that are perpendicular to each other. The intersection area of the cutting channels in the transverse direction and the longitudinal direction of the first wafer 1 is the area where the rectangular EFGH is located; the upper, lower, left and right cutting road areas except the rectangular EFGH are non-crossing areas of the cutting roads in different directions.
The first alignment marks 11 on the first wafer 1 extend from the crossing regions to the non-crossing regions of the scribe lines. The width of the transverse scribe line and the width of the longitudinal scribe line of the first wafer 1 are, for example, 60 μm to 80 μm. The second alignment marks 21 on the second wafer 2 extend from the crossing regions to the non-crossing regions of the scribe lines. The second wafer 2 includes, for example, mutually perpendicular transverse streets a2-a2 'and longitudinal streets B2-B2'. The width of the transverse scribe line and the width of the longitudinal scribe line of the second wafer 2 are, for example, 60 μm to 80 μm. The second alignment mark 21 matches the first alignment mark 11 to achieve alignment of the first wafer 1 and the second wafer 2.
When the first wafer 1 is aligned with the second wafer 2, the center of the second alignment mark 21 and the center of the first alignment mark 11 coincide with each other. Preferably, when the first wafer 1 and the second wafer 2 are aligned, the center of the scribe line where the first wafer 1 crosses with the center of the scribe line where the second wafer 2 crosses with the first wafer coincides. When the first wafer 1 is aligned with the second wafer 2, at least part of the intersection area EFGH of the cutting channel of the first wafer 1 is overlapped with the intersection area EFGH of the cutting channel of the second wafer 2; for example, the intersection area of the scribe lines of the first wafer 1 and the intersection area of the scribe lines of the second wafer 2 may completely coincide. In another embodiment, the intersection region of the scribe line of the first wafer 1 and the intersection region of the scribe line of the second wafer 2 may partially coincide; the scribe line width of the first wafer 1 is designed as required, the scribe line width of the second wafer 2 is designed as required, and the scribe line widths of the first wafer 1 and the second wafer 2 may be different as long as the second alignment mark 21 is aligned with the first alignment mark 11.
The first alignment mark 11 is, for example, a rotationally symmetric pattern. And (3) defining a rotation symmetry graph: a planar figure is rotated by an angle alpha (0 degrees < alpha <360 degrees) around a fixed point on the plane, and then is superposed with an initial figure, the figure is called a rotationally symmetrical figure, the fixed point is called a rotationally symmetrical center, and the rotating angle is called a rotating angle. Illustratively, the first alignment mark 11 includes four bar patterns constituting a rotationally symmetric figure, and the rotation angle α is equal to 90 °. The rotational symmetry center is positioned in the intersection area of the cutting channels of the first wafer 1; preferably, the rotational symmetry center is located at the center of the intersection region of the transverse scribe line A1-A1 'and the longitudinal scribe line B1-B1' of the first wafer 1. Wherein, two bar patterns extend from the crossing region of the cutting street to two sides (non-crossing region) of the transverse cutting street, and the other two bar patterns extend from the crossing region of the cutting street to two sides (non-crossing region) of the longitudinal cutting street; that is, the length direction of the stripe pattern of the transverse cutting street is along the horizontal direction, and the length direction of the stripe pattern of the longitudinal cutting street is along the vertical direction. In the first alignment mark 11, the width of the bar pattern distributed in the transverse street direction and the width of the bar pattern distributed in the longitudinal street direction are slightly smaller than the street width 1/2.
The second alignment mark 21 is, for example, also a rotationally symmetrical pattern, and the second alignment mark 21 matches (corresponds to) the first alignment mark 11. Illustratively, the second alignment mark 21 is formed of four bar patterns constituting a rotationally symmetrical figure, and the rotation angle α is equal to 90 °. Two of the stripe patterns extend from the crossing region of the scribe line to both sides (non-crossing region) of the transverse scribe line a2-a2 ', and the other two stripe patterns extend from the crossing region of the scribe line to both sides (non-crossing region) of the longitudinal scribe line B2-B2'; that is, the length direction of the stripe pattern of the transverse cutting street is along the horizontal direction, and the length direction of the stripe pattern of the longitudinal cutting street is along the vertical direction. In the second alignment mark 21, the width of the bar pattern in the cross street direction and the width of the bar pattern in the longitudinal street direction are both smaller than the street width 1/2. The sum of the width of the bar pattern of the first alignment mark 11 and the width of the bar pattern of the second alignment mark 21 is less than the scribe lane width.
On the basis of the existing wafer bonding machine and the manufacturing process conditions, at least one of the first alignment mark and the second alignment mark extends from the cross area to the non-cross area of the cutting channel on the wafer where the first alignment mark and the second alignment mark are located; the length of the pattern (e.g., stripe pattern) in the alignment mark may be greater than the scribe line width and is no longer limited by the scribe line width. According to the embodiment, the alignment mark with a larger size can be made under the condition that the width of the cutting channel is constant, and the wafer bonding identification efficiency and accuracy are improved. The invention is suitable for cutting channels with smaller size (width), namely, is suitable for the alignment marks of narrow cutting channels, improves the bonding precision and can obtain larger effective area of a chip.
FIG. 5 is a diagram illustrating the matching of the second alignment mark and the first alignment mark according to the second embodiment of the present invention. As shown in fig. 5, the second alignment mark 22 is matched (corresponding) to the first alignment mark 12. The second alignment mark 22 and the first alignment mark 12 are both rotationally symmetric.
It is also understood that the second alignment marks 22 are located closer to the center of the intersection region of the scribe lines than the first alignment marks 12, that is, the starting ends of the four bar patterns of the second alignment marks 22 are located closer to the center of the intersection region of the scribe lines than the starting ends of the four bar patterns of the first alignment marks 12, that the second alignment marks 22 are located closer to the inside, and the first alignment marks 12 are located relatively closer to the outside.
The present invention is not limited to which of the first alignment mark and the second alignment mark is inside and which is outside. Fig. 4 shows that the second alignment marks 21 are arranged outwardly and the first alignment marks 11 are arranged relatively inwardly. Fig. 5 shows that the second alignment marks 22 are located inwardly and the first alignment marks 12 are located relatively outwardly.
The length of the bar-shaped patterns in the first alignment mark and the second alignment mark is not limited, and the bar-shaped patterns can be configured according to actual needs. Fig. 4 shows that the length of the bar pattern in the first alignment mark 11 is greater than the length of the bar pattern in the second alignment mark 21. Fig. 5 shows that the length of the bar pattern in the first alignment mark 12 is smaller than the length of the bar pattern in the second alignment mark 22.
The number of the bar patterns in the first alignment mark and the second alignment mark is not limited, and the alignment mark can be configured according to actual needs and can be a combination of one or more (more than or equal to 2) bars so as to increase the identification capability of the alignment mark. Fig. 4 and 5 show that, in the first and second alignment marks, one stripe pattern is distributed in each of the first and second alignment marks in four directions up, down, left, and right from the rotational symmetry center. FIG. 6 is a diagram illustrating the matching of the second alignment mark and the first alignment mark according to the third embodiment of the present invention. As shown in fig. 6, two bar patterns are distributed in each of the first and second alignment marks 13 and 23 in four directions of up, down, left, and right from the rotational symmetry center among the first and second alignment marks 13 and 23.
In the first alignment mark and the second alignment mark, a characteristic pattern which is convenient to identify can be designed in each pattern. FIG. 7 is a diagram illustrating the matching of the second alignment mark and the first alignment mark according to the fourth embodiment of the present invention. As shown in fig. 7, each of the first alignment mark 14 and the second alignment mark 24 includes, for example, a bar pattern, and features P may be disposed at intervals on the bar pattern, and the shapes of the features P are not limited and may include at least one of a circle, a triangle, a square, and a diamond.
In the wafer assembly described in fig. 4 to 7, the first alignment mark and/or the second alignment mark includes bar patterns distributed in a rotationally symmetric pattern, where the bar patterns include a bar pattern in a first direction (e.g., a horizontal direction) and a bar pattern in a second direction (e.g., a vertical direction), and the bar patterns in the first direction extend from an intersection area of the scribe line in the first direction and the scribe line in the second direction to both sides of the scribe line in the first direction; the bar patterns in the second direction extend from the intersection region of the cutting street to both sides of the cutting street in the second direction.
FIG. 8 is a diagram illustrating the matching of the second alignment mark and the first alignment mark according to a fifth embodiment of the present invention.
The first alignment marks 15 on the first wafer extend from the crossing regions to the non-crossing regions of the scribe lines.
The second alignment marks 25 on the second wafer extend from the crossing regions to the non-crossing regions of the scribe lines. The first alignment mark 15 includes a stripe pattern, and the overall pattern of the first alignment mark 15 formed by the stripe pattern in this embodiment is not a rotationally symmetric pattern. The number of the bar patterns of the first alignment mark 15 is not limited, and it includes 4 bars, for example, two bar patterns extend from the crossing region of the scribe line to both sides of the transverse scribe line (non-crossing region), and the other two bar patterns extend from the crossing region of the scribe line to both sides of the longitudinal scribe line (non-crossing region). The second alignment mark 25 is arranged to match the first alignment mark 15, the second alignment mark 25 also includes a stripe pattern, and the overall pattern of the second alignment mark 25 is not a rotationally symmetric pattern.
FIG. 9 is a diagram illustrating the matching of the second alignment mark and the first alignment mark according to the sixth embodiment of the present invention. One of the first alignment mark and the second alignment mark has a cross-shaped pattern, and the other pattern includes a triangular pattern distributed at four corners of the cross-shaped pattern. The second alignment mark 26 is cross-shaped and the first alignment mark 16 is triangular. The second alignment marks 26 on the second wafer extend from the crossing regions to the non-crossing regions of the scribe lines. The cross-shaped cross-over area OPQR of the second alignment mark 26 is located within the cross-over area EFGH of the cutting street, and the cross-shaped horizontal and vertical bars of the second alignment mark 26 are distributed along the transverse cutting street and the longitudinal cutting street, respectively. The pattern of the first alignment marks 16 includes alignment patterns distributed at four corners of the cross pattern. The alignment patterns are distributed in the crossing regions of the cutting lines or extend from the crossing regions to the non-crossing regions of the cutting lines. In one embodiment, the triangular pattern is distributed within the intersection area of the dicing streets. In another embodiment, the triangular pattern extends from the intersection region to the non-intersection region of the scribe line, i.e., the triangular pattern may be distributed in the intersection region and the non-intersection region near the intersection region.
In summary, the present invention provides a wafer assembly, comprising: a first wafer and a first alignment mark on the first wafer; a second wafer and a second alignment mark on the second wafer; at least one of the first alignment mark and the second alignment mark extends from the intersection region to the non-intersection region of the cutting channel on the wafer on which the first alignment mark and the second alignment mark are located. The length of the pattern (e.g., stripe pattern) in the first alignment mark and/or the second alignment mark may be greater than the width of the scribe line, and is no longer limited by the width of the scribe line. On the basis of the existing wafer bonding machine and the processing conditions, the invention can make the alignment mark with larger size under the condition of a certain width of the cutting channel, thereby improving the wafer bonding identification efficiency and precision. The invention is suitable for cutting channels with smaller size (width), namely, is suitable for the alignment marks of narrow cutting channels, improves the bonding precision and can obtain larger effective area of a chip.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the method disclosed by the embodiment, the description is relatively simple because the method corresponds to the device disclosed by the embodiment, and the relevant points can be referred to the description of the method part.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (12)
1. A wafer assembly, comprising:
a first wafer and a first alignment mark on the first wafer;
a second wafer and a second alignment mark on the second wafer;
at least one of the first alignment mark and the second alignment mark extends from the intersection region of the cutting channel to the non-intersection region on the wafer where the first alignment mark and the second alignment mark are located; and the second alignment mark is matched with the first alignment mark to achieve alignment of the first wafer and the second wafer.
2. The wafer assembly of claim 1, wherein when the first wafer is aligned with the second wafer, a center of the second alignment mark and a center of the first alignment mark coincide with each other.
3. The wafer assembly of claim 1, wherein at least one of the first alignment mark and the second alignment mark comprises a bar pattern extending from an intersection region to a non-intersection region of the scribe line on the wafer on which the bar pattern is located.
4. The wafer assembly of claim 3, wherein the bar pattern is spaced apart by features comprising at least one of circles, triangles, squares, diamonds.
5. The wafer assembly of claim 1, wherein the pattern of the first alignment mark and/or the pattern of the second alignment mark are rotationally symmetric patterns, and a rotational symmetry center of the rotationally symmetric patterns is located at an intersection region of the scribe line on the wafer on which the rotationally symmetric patterns are located.
6. The wafer assembly of claim 5, wherein the first alignment mark and/or the second alignment mark comprises a bar pattern distributed in the rotationally symmetric pattern, the bar pattern comprising a bar pattern in a first direction and a bar pattern in a second direction, the bar pattern in the first direction extending from an intersection area of the scribe lane in the first direction and the scribe lane in the second direction to both sides of the scribe lane in the first direction; the bar patterns in the second direction extend from the intersection region of the cutting street to both sides of the cutting street in the second direction.
7. The wafer assembly of any of claims 1 to 6, wherein when the first wafer is aligned with the second wafer, the intersection of the scribe lanes of the first wafer at least partially coincides with the intersection of the scribe lanes of the second wafer.
8. The wafer assembly of claim 1, wherein the first wafer and the second wafer each include transverse streets and longitudinal streets that are perpendicular to each other.
9. The wafer assembly of claim 8, wherein the width of the transverse scribe line and the width of the longitudinal scribe line each range from 60 μ ι η to 80 μ ι η.
10. The wafer assembly of claim 8, wherein one of the first alignment mark and the second alignment mark is in a cross pattern, a cross area of the cross pattern is located in an intersection area of scribe lanes, and cross bars and vertical bars of the cross pattern are distributed along the lateral scribe lanes and the longitudinal scribe lanes, respectively; the other pattern includes alignment patterns distributed at the four corners of the cross pattern.
11. The wafer assembly of claim 10, wherein the alignment pattern is distributed within or extends from the intersection region of the scribe lines to the non-intersection region.
12. The wafer assembly of claim 10, wherein the alignment pattern is a triangular pattern extending from the intersection region to the non-intersection region of the scribe line.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114346452A (en) * | 2022-01-10 | 2022-04-15 | 江西中弘晶能科技有限公司 | Novel MARK point manufacturing graphic design for improving MARK point subfissure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08264423A (en) * | 1995-03-28 | 1996-10-11 | Nec Corp | Semiconductor wafer |
| US5777392A (en) * | 1995-03-28 | 1998-07-07 | Nec Corporation | Semiconductor device having improved alignment marks |
| JP2007053140A (en) * | 2005-08-15 | 2007-03-01 | Seiko Epson Corp | Semiconductor device |
| US20150380358A1 (en) * | 2014-06-30 | 2015-12-31 | Texas Instruments Incorporated | Methods and Apparatus Using Front-to-Back Alignment Mark and Placement for Narrow Wafer Scribe Lines |
| CN109411449A (en) * | 2018-11-21 | 2019-03-01 | 武汉新芯集成电路制造有限公司 | Wafer assembly and wafer alignment method |
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2021
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08264423A (en) * | 1995-03-28 | 1996-10-11 | Nec Corp | Semiconductor wafer |
| US5777392A (en) * | 1995-03-28 | 1998-07-07 | Nec Corporation | Semiconductor device having improved alignment marks |
| JP2007053140A (en) * | 2005-08-15 | 2007-03-01 | Seiko Epson Corp | Semiconductor device |
| US20150380358A1 (en) * | 2014-06-30 | 2015-12-31 | Texas Instruments Incorporated | Methods and Apparatus Using Front-to-Back Alignment Mark and Placement for Narrow Wafer Scribe Lines |
| CN109411449A (en) * | 2018-11-21 | 2019-03-01 | 武汉新芯集成电路制造有限公司 | Wafer assembly and wafer alignment method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114346452A (en) * | 2022-01-10 | 2022-04-15 | 江西中弘晶能科技有限公司 | Novel MARK point manufacturing graphic design for improving MARK point subfissure |
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