CN109411449B - Wafer assembly and wafer alignment method - Google Patents

Wafer assembly and wafer alignment method Download PDF

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CN109411449B
CN109411449B CN201811392941.9A CN201811392941A CN109411449B CN 109411449 B CN109411449 B CN 109411449B CN 201811392941 A CN201811392941 A CN 201811392941A CN 109411449 B CN109411449 B CN 109411449B
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alignment mark
wafer
alignment
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pattern
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CN109411449A (en
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周云鹏
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Wuhan Xinxin Integrated Circuit Co.,Ltd.
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

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Abstract

The invention provides a wafer assembly and a wafer alignment method, wherein the wafer assembly comprises: the device comprises a process wafer, at least one first alignment mark is distributed on the process wafer; to be provided withAnd a carrier wafer, wherein at least one second alignment mark is distributed on the carrier wafer, the second alignment mark is used for matching the first alignment mark to realize the alignment of the process wafer and the carrier wafer, the perimeter of the outer contour of the second alignment mark is not less than 200 μm, and the area of the second alignment mark is not less than 800 μm2. By making the second alignment mark on the large-bearing wafer, the perimeter and the area of the outer contour of the corresponding second alignment mark are also increased, so that the second alignment mark is easier to identify, the identification efficiency of the alignment mark is improved, and the bonding efficiency of the two wafers can be improved. Meanwhile, the bearing wafer is used for supporting the process wafer, functional patterns can not be distributed on the bearing wafer, and therefore the utilization of the effective area of the bearing wafer is not influenced by the large second alignment mark.

Description

Wafer assembly and wafer alignment method
Technical Field
The invention belongs to the field of semiconductors, and particularly relates to a wafer assembly and a wafer alignment method.
Background
In a semiconductor process, a process wafer, on which various functional devices are formed, and a carrier wafer, which is mainly used for supporting the process wafer, are generally bonded. The process wafer and the bearing wafer are aligned through the alignment mark, and then the process wafer and the bearing wafer are bonded. Typically, the alignment marks are distributed on the scribe lines of the process wafer and the carrier wafer to avoid occupying the area of the device region. And, in order to effectively utilize the area of the wafer, the size of the scribe line is usually designed to be small, so that the size of the alignment mark distributed on the scribe line is also small, making the alignment mark difficult to be identified. In particular, the carrier wafer is mainly used for supporting, and a large part of the area except the alignment mark is not provided with a pattern, so that the reference pattern is not used for assisting identification during alignment, and the identification of the alignment mark on the carrier wafer is more difficult.
Disclosure of Invention
The invention aims to provide a wafer assembly and a wafer alignment method to improve the identification efficiency of a wafer alignment mark.
In order to achieve the above object, the present invention provides a wafer assembly comprising:
the device comprises a process wafer, at least one first alignment mark is distributed on the process wafer; and
a carrier wafer, at least one second alignment mark distributed on the carrier wafer for matching the first alignment mark to align the process wafer with the carrier wafer, wherein the second alignment mark is used for aligning the process wafer with the carrier waferThe perimeter of the outline of the two alignment marks is more than or equal to 200 μm, and the area of the second alignment mark is more than or equal to 800 μm2。
Further, the circumference of the outer contour of the second alignment mark is 201 μm to 2309 μm, and the area of the second alignment mark is 1340 μm2～64000μm2。
Further, the first alignment mark and the second alignment mark are axisymmetric structures symmetric with respect to two mutually perpendicular axes, and a center of the second alignment mark and a center of the first alignment mark coincide with each other when the process wafer and the carrier wafer are aligned.
Further, the first alignment mark includes a triangular pattern or a bar pattern.
Further, the first alignment mark includes at least two triangular patterns, or the first alignment mark includes a striped pattern crossing each other.
Further, the second alignment mark includes a triangular pattern and/or a bar pattern.
Further, the second alignment mark includes a striped pattern crossing each other; or, the second alignment mark comprises an inner mark and an outer mark surrounding the inner mark, the inner mark comprises a mutually crossed bar pattern or a triangular pattern distributed in an array, and the outer mark comprises a plurality of bar patterns arranged in a ring shape; alternatively, the second alignment marks comprise a triangular pattern distributed in an array.
Furthermore, two second alignment marks are distributed on the carrier wafer, and the two second alignment marks are symmetrically distributed about a diameter of the carrier wafer.
Further, the wafer assembly is a back-illuminated CMOS image sensor.
The invention also provides a wafer alignment method, which comprises the following steps:
providing a process wafer, wherein at least one first alignment mark is distributed on the process wafer;
providing a carrier wafer, wherein at least one carrier wafer is distributed on the carrier waferA second alignment mark for matching the first alignment mark to realize alignment between the process wafer and the carrier wafer, wherein the perimeter of the outer contour of the second alignment mark is not less than 200 μm, and the area of the second alignment mark is not less than 800 μm2And an
And identifying the first alignment mark and the second alignment mark, and matching the first alignment mark and the second alignment mark to realize the alignment of the process wafer and the bearing wafer.
Compared with the prior art, the invention provides a wafer assembly, the perimeter of the outer contour of a second alignment mark on a bearing wafer is more than or equal to 200 mu m, and the area of the second alignment mark is more than or equal to 800 mu m2By making the second alignment mark on the large-bearing wafer, the perimeter and the area of the outer contour of the corresponding second alignment mark are also increased, so that the second alignment mark is easier to identify, the identification efficiency of the alignment mark is improved, and the bonding efficiency of the two wafers can be improved. Meanwhile, the bearing wafer is used for supporting the process wafer, functional patterns can not be distributed on the bearing wafer, and therefore the utilization of the effective area of the bearing wafer is not influenced by the large second alignment mark.
Drawings
FIG. 1 is a schematic view of a first alignment mark on a process wafer according to an embodiment of the present invention;
FIG. 2 is a schematic view of a first second alignment mark on a carrier wafer according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a first alignment mark and a second alignment mark after alignment according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a second alignment mark on a carrier wafer according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating a first alignment mark and a second alignment mark after alignment according to an embodiment of the present invention;
FIG. 6 is a schematic view of a second type of first alignment mark on a process wafer according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating a second alignment mark and a first second alignment mark after alignment according to an embodiment of the present invention;
FIG. 8 is a diagram illustrating a second alignment mark after alignment of a second first alignment mark and a second alignment mark according to an embodiment of the present invention;
FIG. 9 is a schematic view of a third first alignment mark on a process wafer according to an embodiment of the present invention;
FIG. 10 is a diagram illustrating a third alignment mark on the carrier wafer according to the embodiment of the present invention;
FIG. 11 is a diagram illustrating a third alignment mark and a third second alignment mark after alignment according to an embodiment of the present invention;
FIG. 12 is a diagram illustrating a fourth alignment mark on a carrier wafer according to an embodiment of the present invention;
fig. 13 is a diagram illustrating a third alignment mark and a fourth alignment mark after alignment according to an embodiment of the invention.
Wherein the figures of the drawings are as follows:
11 — a first alignment mark; 111-triangular pattern;
21-a second alignment mark; 211-bar pattern; 212-a bar pattern; 213-a bar pattern; 214-a striped pattern; 215-bar pattern; 216-bar pattern;
22-a second alignment mark; 225-bar pattern; 226-bar pattern;
12-a first alignment mark; 121-triangular pattern;
13-first alignment mark; 131-a bar pattern; 132-a bar pattern;
23-a second alignment mark; 231-bar pattern; 232-bar pattern; 233-bar pattern; 234-bar pattern; 235-a triangular pattern;
24-a second alignment mark; 241-triangular pattern.
Detailed Description
The invention is described in further detail below with reference to the figures and specific examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted, however, that the drawings are designed in a simplified form and are not to scale, but rather are to be construed in an illustrative and descriptive sense only and not for purposes of limitation.
An embodiment of the present invention provides a wafer assembly, including:
the device comprises a process wafer, at least one first alignment mark is distributed on the process wafer; and
a carrier wafer, at least one second alignment mark distributed on the carrier wafer for matching the first alignment mark to realize alignment between the process wafer and the carrier wafer, wherein the perimeter of the outer contour of the second alignment mark is not less than 200 μm, and the area of the second alignment mark is not less than 800 μm2。
Preferably, the circumference of the outer contour of the second alignment mark is 201 μm to 2309 μm, and the area of the second alignment mark is 1340 μm2～64000μm2。
Preferably, the first alignment mark and the second alignment mark are axisymmetric structures symmetric with respect to two mutually perpendicular axes, and a center of the second alignment mark and a center of the first alignment mark coincide with each other when the process wafer and the handle wafer are aligned.
Preferably, the first alignment mark includes a triangular pattern or a stripe pattern.
Further, the first alignment mark includes at least two triangular patterns, or the first alignment mark includes a striped pattern crossing each other.
Preferably, the second alignment mark includes a triangular pattern and/or a stripe pattern.
Further, the second alignment mark includes a striped pattern crossing each other; or, the second alignment mark comprises an inner mark and an outer mark surrounding the inner mark, the inner mark comprises a mutually crossed bar pattern or a triangular pattern distributed in an array, and the outer mark comprises a plurality of bar patterns arranged in a ring shape; alternatively, the second alignment marks comprise a triangular pattern distributed in an array.
As shown in fig. 1, in the embodiment of the present invention, the first alignment mark 11 on the process wafer is an axisymmetric structure symmetric with respect to two orthogonal axes, and the first alignment mark includes four triangular patterns 111, the first alignment mark is symmetric with respect to the X axis, and the first alignment mark is also symmetric with respect to the Y axis.
As shown in fig. 1 and fig. 2, in the embodiment of the present invention, a second alignment mark 21 on a carrier wafer is matched with a first alignment mark 11 on a process wafer, the second alignment mark 21 is an axisymmetric structure symmetric with respect to two orthogonal axes, an X axis and a Y axis are set to be orthogonal to each other, the second alignment mark 21 is symmetric with respect to the X axis, and the second alignment mark 21 is also symmetric with respect to the Y axis, the second alignment mark 21 includes an inner mark and an outer mark surrounding the inner mark, the inner mark includes two mutually crossing bar patterns 215 and 216, and the outer mark includes four bar patterns 211, 212, 213, and 214 arranged in a ring shape in sequence. The pattern of the first alignment mark 11 and the first second alignment mark 21 after alignment is shown in fig. 3.
Two mutually crossed bar patterns 215 and 216 in the inner mark of the second alignment mark 21 are used for matching with the first alignment mark 11, the bar patterns 215 and 216 are located between the triangular patterns 111, and the first alignment mark 11 is an alignment mark on the process wafer, in order to effectively utilize the area of the process wafer, the size of the first alignment mark 11 needs to be smaller, the corresponding triangular patterns 111 are smaller, and the space between the triangular patterns 111 is also smaller, so the width W1 of the bar patterns 215 and 216 located between the triangular patterns 111 is also smaller, for example, W1 is 10 μm to 40 μm, and by making the size L1 of the bar patterns 215 and 216 in the length direction, for example, L1 is 40 μm to 800 μm, the perimeter and the area of the outer contour of the corresponding second alignment mark 21 are also increased; meanwhile, an outer mark is designed, and the outer mark comprises four bar patterns 211, 212, 213 and 214 which are sequentially arranged in a ring shape, so that the perimeter and the area of the outer contour of the second alignment mark 21 on the carrier wafer are further increased.
The outer contour perimeter of the second alignment mark 21 refers to a minimum length of a virtual connection line that can frame the outer boundary of the second alignment mark 21, and specifically, the outer contour of the second alignment mark 21 is defined by four peripheral edges of four bar patterns and a shortest connection line between every two adjacent peripheral edges.
The lengths of the outer boundaries of the four bar patterns (211-214) are all M1, the shortest connecting line between two adjacent outer edges is all N1, and the perimeter of the outer contour of the second alignment mark 21 is 4M1+4N 1. For easy recognition, the perimeter (4M1+4N1) of the outer contour of the second alignment mark 21 is set to be 200 μ M or more.
The area of the second alignment mark 21 is equal to the sum of the areas of all the patterns constituting the second alignment mark 21, and in particular, the area of the second alignment mark 21 is equal to the sum of the areas of the bar pattern 215, the bar pattern 216, the bar pattern 211, the bar pattern 212, the bar pattern 213, and the bar pattern 214. Preferably, the shape of the stripe pattern 215 is the same as that of the stripe pattern 216, the shape of the stripe pattern 211, the shape of the stripe pattern 212, the shape of the stripe pattern 213, and the shape of the stripe pattern 214 are the same, for example, 40 μm to 800 μm for L1, for example, 10 μm to 40 μm for W1, and the area of the stripe pattern 215 is, for example, 400 μm2～32000μm2The sum of the areas of the bar pattern 215 and the bar pattern 216 is greater than or equal to 800 μm2. Preferably, the width of the bar pattern 211 is 10 μm or more, the area of the second alignment mark 21 is equal to the sum of the areas of the bar pattern 215, the bar pattern 216 and the quadruple bar pattern 211, and it is apparent that the area of the second alignment mark 21 is greater than 800 μm2。
Fig. 3 is a schematic diagram illustrating the first alignment mark 11 and the second alignment mark 21 after alignment.
By making the second alignment mark 21 on the large-size carrier wafer, the circumference and the area of the outer contour of the corresponding second alignment mark 21 are also increased, so that the second alignment mark 21 is easier to identify, the identification efficiency of the alignment mark is improved, and the bonding efficiency of the two wafers can be improved. Meanwhile, the bearing wafer is used for supporting the process wafer, functional patterns can not be distributed on the bearing wafer, and therefore the utilization of the effective area of the bearing wafer is not influenced by the large second alignment mark.
As shown in fig. 4, the second alignment mark 22 has an axisymmetric structure symmetrical with respect to two mutually perpendicular axes, the second alignment mark 22 has two mutually perpendicular bar patterns 225 and 226, and the circumference and the area of the outer contour of the corresponding second alignment mark 22 are increased by making the dimension L2 in the length direction of the large bar patterns 225 and 226.
The outer contour perimeter of the second alignment mark 22 refers to a minimum length of a virtual connection line that can frame the outer boundary of the second alignment mark 22, and specifically, the outer contour of the second alignment mark 22 is defined by four peripheral sides of two bar patterns (225 and 226) and a shortest connection line between every two adjacent peripheral sides. Preferably, the bar pattern 225 and the bar pattern 226 have the same shape, four peripheral sides of the two bar patterns (225 and 226) have a length of M2, a shortest connecting line between two adjacent peripheral sides has a length of N2, and the outer contour circumference of the second alignment mark 22 is 4M2+4N 2. For easy recognition, the perimeter (4M2+4N2) of the outer contour of the second alignment mark 21 is set to be 200 μ M or more.
The area of the second alignment mark is equal to the sum of the areas of the bar patterns 225 and 226. The dimension L2 in the longitudinal direction of the stripe pattern 225 and the stripe pattern 226 is, for example, 67 μ M to 800 μ M, the width W2 is, for example, 10 μ M to 40 μ M, when L2 is 67 μ M and W2 is 10 μ M, the outer contour circumference (4M2+4N2) of the second alignment mark 22 is 201 μ M, and the area of the second alignment mark is 1340 μ M2(ii) a When L2 is 800 μ M and W2 is 40 μ M, the outer circumference (4M2+4N2) of the second alignment mark 22 is 2309 μ M and the area of the second alignment mark is 64000 μ M2(ii) a The area of the stripe pattern 225 was 670 μm2～32000μm2The area of the second alignment mark 22 is equal to twice the area of the bar pattern 225, and the area of the second alignment mark is, for example, 1340 μm2～64000μm2。
The outer circumference of the second alignment mark 22 is 201 μm to 2309 μm, and the area of the second alignment mark 22 is 1340 μm2～64000μm2。
As shown in fig. 5, the first alignment mark 11 and the second alignment mark 22 are aligned.
As shown in fig. 6, the first alignment marks 12 are two triangles 121 symmetrically distributed between the included angles of the mutually perpendicular X-axis and Y-axis, and the pattern of the second first alignment marks 12 aligned with the first second alignment marks 21 is shown in fig. 7. The aligned pattern of the second type first alignment mark 12 and the second type second alignment mark 22 is shown in fig. 8.
As shown in fig. 9, the first alignment mark 13 includes a bar pattern 131 and a bar pattern 132 crossing each other, and preferably, the bar pattern 131 and the bar pattern 132 are perpendicular to each other.
As shown in fig. 9 and 10, in the embodiment of the present invention, the second alignment mark 23 on the carrier wafer is matched with the first alignment mark 13 on the process wafer, the second alignment mark 23 is an axisymmetric structure symmetric with respect to two orthogonal axes, and the orthogonal X-axis and the orthogonal Y-axis are arranged, the second alignment mark 23 is symmetric with respect to the X-axis, and the second alignment mark 23 is also symmetric with respect to the Y-axis. The second alignment mark 23 includes an inner mark including four triangular patterns 235 arranged in an array, and an outer mark surrounding the inner mark including four bar patterns 231, 232, 233, and 234 arranged in a ring shape in sequence. The aligned patterns of the third first alignment mark 13 and the third second alignment mark 23 are shown in fig. 11.
Specifically, as shown in fig. 10, the outer contour perimeter of the second alignment mark 23 refers to the minimum length of a virtual connection line that can frame the outer boundary of the second alignment mark 23, and specifically, the outer contour of the second alignment mark 23 is defined by four peripheral edges of four bar patterns (231 to 234) and the shortest connection line between every two adjacent peripheral edges. The lengths of the outer boundaries of the four bar patterns (231-234) are all M3, the shortest connecting line between two adjacent outer peripheral edges is all N3, and the outer contour perimeter of the second alignment mark 23 is 4M3+4N 3. For easy recognition, the perimeter (4M3+4N3) of the outer contour of the second alignment mark 23 is set to be more than or equal to 200 μ M. Preferably, the width of the stripe pattern 231 is not less than 10 μm. Preferably, the triangular patterns 235 are isosceles right triangles having a right side length of, for example, 20 μm to 380 μm, and the sum of the areas of the four triangular patterns 235 is 800 μm2～288800μm2The second alignment mark 23 has an area of four triangle patterns 235 and four bar patternsThe sum of the areas (231-234).
The perimeter of the outline of the second alignment mark 23 is not less than 200 μm, and the area of the second alignment mark 23 is not less than 800 μm2。
By making the second alignment mark 23 on the large-size carrier wafer, the circumference and the area of the outer contour of the corresponding second alignment mark 23 are also increased, so that the second alignment mark is easier to identify, the identification efficiency of the alignment mark is improved, and the bonding efficiency of the two wafers can be improved. Meanwhile, the bearing wafer is used for supporting the process wafer, functional patterns can not be distributed on the bearing wafer, and therefore the utilization of the effective area of the bearing wafer is not influenced by the large second alignment mark.
As shown in fig. 12, the second alignment mark 24 is an axisymmetric structure symmetrical with respect to both of two axes perpendicular to each other, and the X axis and the Y axis perpendicular to each other are provided, and the second alignment mark 24 is symmetrical with respect to the X axis while the first alignment mark is also symmetrical with respect to the Y axis. The second alignment marks 24 are four triangular patterns 241 distributed in an array.
Specifically, the outer contour perimeter of the second alignment mark 24 refers to the minimum length of a virtual connection line that can frame the outer boundary of the second alignment mark 24, and specifically, the outer contour of the second alignment mark 24 is defined by the shortest connection line between four peripheral sides of four triangular patterns and every two adjacent peripheral sides. The lengths of the outer boundaries of the four triangular patterns 241 are all M4, the lengths of the shortest connecting lines between two adjacent peripheral edges are all N4, and the perimeter of the outer contour of the second alignment mark 24 is 4M4+4N 4. For easy recognition, the perimeter (4M4+4N4) of the outer contour of the second alignment mark 24 is set to be 200 μ M or more. The area of the second alignment mark 24 is equal to the sum of the areas of the four triangular patterns 241. Preferably, the triangular patterns 241 are isosceles right triangles having a right side length of, for example, 36 μm to 380 μm, and the sum of the areas of the four triangular patterns 241 is, for example, 2592 μm2～288800μm2。
The aligned patterns of the third first alignment mark 13 and the fourth alignment mark 24 are shown in fig. 13.
The perimeter (4M4+4N4) of the outline of the second alignment mark 24 is greater than or equal to 200 μ M, and the perimeter of the outline of the second alignment mark 24 is larger than or equal to 200 μ MThe area is more than or equal to 800 mu m2。
By making the second alignment mark 24 on the large-size carrier wafer, the circumference and the area of the outer contour of the corresponding second alignment mark 24 are also increased, so that the second alignment mark is easier to identify, the identification efficiency of the alignment mark is improved, and the bonding efficiency of the two wafers can be improved.
The first alignment mark and the second alignment mark are metal patterns or dielectric layer patterns. The metal material in the metal pattern is any one of aluminum, copper and tungsten. The dielectric layer material in the dielectric layer pattern is, for example, silicon oxide and/or silicon nitride.
Preferably, two second alignment marks are distributed on the carrier wafer, and the two second alignment marks are symmetrically distributed about a diameter of the carrier wafer.
Preferably, the wafer assembly is a back-illuminated CMOS image sensor, the process wafer is a pixel wafer, and the pixel wafer and the carrier wafer are bonded.
The embodiment of the invention also provides a wafer alignment method, which comprises the following steps:
providing a process wafer, wherein at least one first alignment mark is distributed on the process wafer;
providing a carrier wafer, wherein at least one second alignment mark is distributed on the carrier wafer, the second alignment mark is used for matching the first alignment mark to realize the alignment of the process wafer and the carrier wafer, the perimeter of the outer contour of the second alignment mark is more than or equal to 200 mu m, and the area of the second alignment mark is more than or equal to 800 mu m2(ii) a And
and identifying the first alignment mark and the second alignment mark, and matching the first alignment mark and the second alignment mark to realize the alignment of the process wafer and the bearing wafer.
Stacking the bearing wafer and the process wafer, for example, the bearing wafer is positioned below, the process wafer is positioned above, the wafer can be penetrated by infrared rays, the first alignment mark and the second alignment mark are respectively found under the lens of the infrared microscope, the positions of the bearing wafer and the process wafer are moved by the machine platform after the first alignment mark and the second alignment mark are aligned, and the bearing wafer and the process wafer are bonded after the first alignment mark and the second alignment mark are aligned.
In summary, in the embodiment of the invention, the perimeter of the outer contour of the second alignment mark on the carrier wafer is greater than or equal to 200 μm, and the area of the second alignment mark is greater than or equal to 800 μm2By making the second alignment mark on the large-bearing wafer, the perimeter and the area of the outer contour of the corresponding second alignment mark are also increased, so that the second alignment mark is easier to identify, the identification efficiency of the alignment mark is improved, and the bonding efficiency of the two wafers can be improved. Meanwhile, the bearing wafer is used for supporting the process wafer, functional patterns can not be distributed on the bearing wafer, and therefore the utilization of the effective area of the bearing wafer is not influenced by the large second alignment mark.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the device disclosed by the embodiment, the description is relatively simple because the device corresponds to the method disclosed by the embodiment, and the relevant part can be referred to the method part for description.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (10)

1. A wafer assembly, comprising:
the device comprises a process wafer, at least one first alignment mark is distributed on the process wafer; and
a carrier wafer, at least one second alignment mark distributed on the carrier wafer for matching the first alignment mark to realize alignment between the process wafer and the carrier wafer, wherein the perimeter of the outer contour of the second alignment mark is not less than 200 μm, and the area of the second alignment mark is not less than 800 μm2；
Wherein the outer contour perimeter of the second alignment mark indicates a minimum length of a virtual connection line that can frame an outer boundary of the second alignment mark; the area of the second alignment mark is equal to the sum of the areas of all the patterns constituting the second alignment mark.
2. The wafer assembly of claim 1, wherein the outer perimeter of the second alignment mark is 201 μm to 2309 μm, and the area of the second alignment mark is 1340 μm2～64000μm2。
3. The wafer assembly of claim 1, wherein the first alignment mark and the second alignment mark are axisymmetric structures that are symmetric about two axes perpendicular to each other, and a center of the second alignment mark and a center of the first alignment mark coincide with each other when the process wafer is aligned with the handle wafer.
4. The wafer assembly of claim 1, wherein the first alignment mark comprises a triangular pattern or a bar pattern.
5. The wafer assembly of claim 4, wherein the first alignment mark comprises at least two triangular patterns, or wherein the first alignment mark comprises a striped pattern that intersects with each other.
6. The wafer assembly of claim 1, wherein the second alignment mark comprises a triangular pattern and/or a bar pattern.
7. The wafer assembly of claim 6, wherein the second alignment mark comprises two bar patterns crossing each other; or, the second alignment mark comprises an inner mark and an outer mark surrounding the inner mark, the inner mark comprises a mutually crossed bar pattern or a triangular pattern distributed in an array, and the outer mark comprises a plurality of bar patterns arranged in a ring shape, or the second alignment mark comprises a triangular pattern distributed in an array.
8. The wafer assembly of claim 1, wherein two of the second alignment marks are distributed on the carrier wafer, and the two second alignment marks are symmetrically distributed about a diameter of the carrier wafer.
9. The wafer assembly of claim 1, wherein the wafer assembly is a backside illuminated CMOS image sensor.
10. A wafer alignment method, comprising:
providing a process wafer and a handle wafer according to any one of claims 1 to 9; and
and identifying the first alignment mark and the second alignment mark, and matching the first alignment mark and the second alignment mark to realize the alignment of the process wafer and the bearing wafer.
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CN110955120B (en) * 2019-12-16 2021-08-06 武汉新芯集成电路制造有限公司 Method and device for determining precompensation value
CN111933618B (en) * 2020-08-13 2022-01-28 武汉新芯集成电路制造有限公司 Wafer assembly with alignment mark, forming method thereof and wafer alignment method
CN112151444B (en) * 2020-09-28 2023-04-07 武汉新芯集成电路制造有限公司 Matching design method of wafer, wafer bonding structure and chip bonding structure
CN113421874A (en) * 2021-06-24 2021-09-21 武汉新芯集成电路制造有限公司 Wafer assembly
CN114779572B (en) * 2022-06-16 2022-11-04 合肥晶合集成电路股份有限公司 Manufacturing method of alignment mark and wafer bonding method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7190823B2 (en) * 2002-03-17 2007-03-13 United Microelectronics Corp. Overlay vernier pattern for measuring multi-layer overlay alignment accuracy and method for measuring the same
DE10345471B4 (en) * 2003-09-30 2006-03-30 Infineon Technologies Ag Adjustment mark for coarse adjustment and fine adjustment of a semiconductor wafer in an exposure device
US8299584B2 (en) * 2010-03-08 2012-10-30 International Business Machines Corporation Alignment of wafers for 3D integration
CN102692831B (en) * 2012-05-28 2014-03-26 京东方科技集团股份有限公司 Counterpoint mark and method for using same to manufacture workpieces in exposure process
CN104701301B (en) * 2015-03-10 2018-05-01 武汉新芯集成电路制造有限公司 A kind of wafer alignment mark

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