JP2659645B2 - Lead terminal flatness measurement method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for measuring the flatness of a lead terminal used in a semiconductor device.

[0002]

2. Description of the Related Art FIG. 5 is a side view showing a method for measuring the flatness (hereinafter, also referred to as coplanarity) of a lead terminal of a conventional semiconductor device using a reference plane of a measurement stage. In FIG. A semiconductor device to be measured (hereinafter, referred to as an IC to be measured), 1a is a molded part thereof, and 1b is a lead. Reference numeral 2 denotes a measurement stage for mounting the IC 1 to be measured thereon to perform measurement, 3 denotes a camera for capturing an image of the lead 1b of the IC 1 to be measured, 4a denotes the IC to be measured,
The light is emitted from a direction facing the camera 3. FIG. 6 is a diagram showing an image captured by the camera 3 when the irradiation light 4a is applied to the IC 1 to be measured. In FIG. 6, reference numeral 1c denotes a shadow of the lead 1b. Here, shadows of four leads are shown. . 2a is a shadow of the measurement stage 2 serving as a reference plane, and 5 is a measured coplanarity value (flatness).

Next, a measuring method will be described. The IC 1 to be measured is placed on the measurement stage 2, and irradiation light 4 a is emitted from the direction in which the lead terminal 1 b of the IC 1 to be measured faces the camera 3. Then, as shown in FIG. 6, a shadow 1c of the lead of the IC 1 to be measured and a shadow 2a of the reference plane of the measurement stage are formed. At the same time, the image is captured by the camera 3 and subjected to binary processing to calculate a coplanarity value 5 of the lead 1b.

[0004]

Since the conventional method for measuring the flatness of a lead terminal is constructed as described above, if the gap between the lead terminal and the measurement stage is small, that is, if the coplanarity value is small, the interference of the illuminating light will not occur. In addition, there is a problem that a portion where the coplanarity value is to be measured becomes dark due to a shortage of the amount of light transmitted to the camera, which causes an erroneous measurement.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a lead terminal flatness measurement method capable of improving measurement accuracy in coplanarity measurement.

[0006]

A lead terminal flatness measuring method according to the present invention includes a first step of obtaining an image of a reference plane of a measuring stage, and a method of mounting a semiconductor device to be measured on the measuring stage. A second step of obtaining an image of only the lead terminal of the semiconductor device, and combining the respective images obtained in the first and second steps, a reference plane of the measurement stage of the combined image and the lead terminal And a third step of measuring the flatness of the lead terminal from the gap between them.

[0007]

According to the present invention, an image of a measurement stage serving as a reference plane and an image of a lead terminal of a semiconductor device to be measured are separately captured, and the above-described measurement of an image obtained by combining these two images is performed. Because the gap between the reference plane of the stage and the lead terminal was measured to determine the flatness of the lead terminal, even if the gap between the reference plane of the measurement stage and the lead terminal was small, light interference and insufficient transmission caused the gap. There is no darkening between the reference plane and the lead terminals.

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing a method for measuring lead terminal flatness according to an embodiment of the present invention. In FIG.
The same reference numerals as those in FIG. 5 denote the same or corresponding parts, 6 denotes a measuring stage made of light-transmitting glass for mounting the IC 1 to be measured, and 7 denotes a measuring stage for capturing an image of a reference plane. A light source for irradiating light from above the stage 6. FIG. 2 is a diagram for explaining a method of capturing a shadow of a reference plane as a first measurement stage. In the drawing, reference numeral 7a denotes a light source 7 from a measurement stage 6 on which the IC 1 to be measured is mounted. This is irradiation light that is irradiated vertically. FIG. 3 shows an IC to be measured as a second measurement stage.
FIG. 4 is a diagram for explaining a method of capturing an image of a lead 1b.

FIG. 4 is a diagram for explaining signal processing for calculating the coplanarity by processing the image of the measured IC 1 obtained in the two-stage measurement. In the drawing, reference numeral 8 denotes an obtained image of the reference plane, 9 denotes an inverted image of the reference plane in which the black and white of the image 8 of the reference plane is inverted and the reference plane portion is blackened, and 10 denotes an obtained lead 1b of the IC 1 to be measured. Image 11 is an inverted image 9 of the reference plane and the IC to be measured
9 is a composite image for obtaining a coplanarity value of 5 by synthesizing the lead 1b of No. 1;

Next, a measuring method will be described. First, as shown in FIG. 2, before mounting the IC 1 to be measured on the measurement stage 6, the irradiation light 7a is irradiated from above the measurement stage 6 and an image of the measurement stage 6 is obtained from the side by the camera 3 (first measurement stage). ). Here, since the periphery is dark and the measurement stage 6 is made of glass, the image obtained here is bright at the measurement stage 6 like the image 8 of the reference plane in FIG. Get dark. Next, as shown in FIG. 3, the IC 1 to be measured is placed on the
The lead 1b of C1 is irradiated with irradiation light 4a from a direction facing the camera 3. Then, an image of the lead 1b of the measured IC 6 is taken from the side again by the camera 3 (second measurement stage). At this time, the portion where the lead 1b exists as shown in the image 10 of the lead 1b of the measured IC 6 in FIG.

Finally, the brightness of the image 8 of the reference plane obtained as described above is inverted to obtain an inverted image 9 of the reference plane, and the image 10 of the lead to be measured obtained in the second measurement stage. (See 11 in FIG. 4) and coplanarity
Find the value 5.

As described above, according to the present embodiment, as the first measurement step, before mounting the IC 1 to be measured, the irradiation light 7a is irradiated from above the measurement stage 6 and the image of the reference plane of the measurement stage 6 is obtained. The image is taken by the camera 3 and the image is inverted to obtain an inverted image 9 of the reference plane, and as a second measurement step,
The IC 1 to be measured is mounted on the measurement stage 6, and the irradiation light 4a is irradiated from the side to obtain an image 10 of the lead 1b. An image 11 obtained by synthesizing the image 10 and the inverted image 9 of the reference plane is obtained. The coplanarity value 5 is determined from the following equation. Therefore, even when the distance between the measurement stage 6 and the lead 1b is small, interference of light occurs, and the amount of transmitted light incident on the camera 3 is reduced, so that the portion where the coplanarity should be measured is reduced. Highly accurate measurement can be performed without darkening.

[0013]

As described above, according to the lead terminal flatness measuring method of the present invention, an image of a measurement stage serving as a reference plane and an image of a lead terminal of a semiconductor device to be measured are separately imaged. The air gap between the reference plane of the measurement stage and the lead terminal of the image obtained by synthesizing these two images was measured to determine the flatness of the lead terminal. There is no darkening between the reference plane and the lead terminal of the semiconductor device to be measured. As a result, erroneous measurement is prevented, and the lead terminal can be measured with high accuracy.

[Brief description of the drawings]

FIG. 1 is a diagram showing an arrangement of various equipment when measuring coplanarity using a lead terminal flatness measuring method according to an embodiment of the present invention.

FIG. 2 is a diagram showing a method for capturing a reference plane image by the above method.

FIG. 3 is a diagram showing a method for capturing an image of a lead of an IC to be measured by the above method.

FIG. 4 is a view for explaining a method of processing each image obtained by the above method to obtain coplanarity.

FIG. 5 is a diagram showing an arrangement of various devices when measuring coplanarity by a conventional lead terminal flatness measuring method.

FIG. 6 is a diagram showing an image of a lead of an IC to be measured taken by a camera by a conventional lead terminal flatness measuring method.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 IC to be measured 1a Mold part 1b Lead part 1c Lead shadow 3 Image capturing camera 4 Irradiation light source from the side of measurement stage 4a Light emitted from irradiation light source 4 5 Coplanarity value 6 Light transmission measurement stage 7 Above measurement stage Irradiation light source 7a Irradiation light from irradiation light source 8 8 Image of reference plane 9 Inversion image of image of reference plane 10 Image of lead 1b 11 Composite image of inverted image 9 of reference plane and image of lead 1b

Claims (1)

(57) [Claims] 1. A semiconductor device to be measured is mounted on a measurement stage, light is irradiated from a predetermined direction to image a shadow of a lead terminal of the semiconductor device to be measured, and a reference plane between the lead terminal and the surface of the measurement stage is taken. In the method of measuring the flatness of the lead terminal from the gap between the semiconductor device and the semiconductor device to be measured, light is radiated before mounting the semiconductor device to be measured. A second step of mounting the semiconductor device to be measured on the stage, irradiating light from a predetermined direction to obtain an image of only the lead terminals, and a second step of obtaining an image of only the lead terminals. The image of the reference plane of the measurement stage and the image of only the lead terminal obtained in the second step are combined, and the lead terminal is obtained from the gap between the lead terminal and the reference plane obtained from the image. Flatness And a third step of measuring the flatness of the lead terminal.