JP2659619B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device structure of a semiconductor device, and more particularly to a device structure using a TFT (Thin Film Transistor).

[0002]

2. Description of the Related Art FIG. 2 is a sectional view of a memory cell of a conventional CMOS type SRAM using a TFT. In the figure, 1 is a silicon substrate, 3 is a gate electrode formed via a gate oxide film 2 for an N-channel transistor, 4 is an N ⁺ diffusion region formed on the semiconductor substrate 1, 5 is an interlayer insulating film,
6 is a gate electrode for a P-channel transistor, 7 is a gate oxide film, 8 is a P ⁺ diffusion region, 9 is a P-channel region,
Reference numeral 0 denotes a contact region connecting the P ⁺ diffusion region 8 and the N ⁺ diffusion region 4, and the P ⁺ diffusion region 8 and the P channel region 9 form an operation layer.

Next, a manufacturing method will be described. Gate oxide film 2 for N-channel transistor on silicon substrate 1
And a gate electrode 3 are formed. The gate oxide film 2 is a thermal oxide film of silicon having a thickness of about 150 Å,
The gate electrode 3 is made of polycrystalline silicon of about 2000 Å and tungsten silicide of about 1500 Å.

Next, an N ⁺ diffusion region 4 is formed on the substrate surface in a self-aligned manner with respect to the gate electrode 3. N ⁺ diffusion region 4 is formed by double implantation of phosphorus and arsenic.

Then, after forming an interlayer insulating film 5 on the gate electrode 3 using a CVD oxide film of about 1500 Å, polycrystalline silicon of about 2000 Å is formed on the interlayer insulating film 5 to form a P-channel transistor. Is formed.

Next, after a gate oxide film 7 is formed using a thinned CVD oxide film, a P channel region 9 is formed from polycrystalline silicon and a P ⁺ diffusion region 8 is formed by boron implantation or the like. Also, by partially removing the interlayer insulating film 5,
A contact region connecting the P ⁺ diffusion region and the N ⁺ diffusion region is formed.

[0007]

The semiconductor equipment using INVENTION Problems to be Solved conventional TFT is configured as described above, the polycrystalline silicon layer is required three layers, also the vertical direction of the step is large circuit on the wiring There was a problem that it became complicated. In addition, there is a problem that when a transistor is formed in a plane to eliminate a step in the vertical direction, the memory size increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to reduce the number of polycrystalline silicon layers, simplify the wiring structure, and obtain a semiconductor device which does not increase the memory size. Aim.

[0009]

A semiconductor device according to the present invention is formed in a surface region of a substrate and includes a first transistor.
An operation layer of the data, and the gate electrode of the first transistor formed via an insulating film on said operating layer, the first
A gate electrode which is formed on a gate electrode of the first transistor via an insulating film and constitutes a second transistor ;
An operating layer that is formed on the side wall surface of the gate electrode of the second transistor via an insulating film, and that constitutes the second transistor, wherein the source / drain of the first transistor is provided .
The current flowing between the in-diffusion regions is supplied to the first transistor
And the second transistor
Current flowing between the source / drain diffusion regions of the
Configuration controlled by the gate electrode of two transistors
It was done.

[0010]

According to the present invention, a TF is further provided on a transistor formed on a substrate via an insulating film.
Since the operation layer is formed on the side wall surface of the gate electrode of T, the step due to the polycrystalline silicon layer is reduced , and the memory cell size is not increased.

[0011]

FIG. 1A is a sectional view of a memory cell of a CMOS SRAM using a TFT according to an embodiment of the present invention.
(b) is the bird's eye view. In the figure, the same reference numerals as those in FIG. 2 indicate the same or corresponding parts, and reference numeral 11 denotes a polycrystalline silicon layer on the side wall of the gate electrode of the TFT.

Next, the manufacturing method will be described. On a silicon substrate 1, a gate oxide film 2 and a gate electrode 3 for an N-channel transistor are formed in the same manner as in the prior art. The gate oxide film 2 is made of a thermal oxide film of silicon having a thickness of about 150 Å, and the gate electrode 3 is made of polycrystalline silicon having a thickness of about 2,000 Å and tungsten silicide having a thickness of about 1500 Å.

Next, an N ⁺ diffusion region 4 is formed on the surface of the substrate 1 by self-alignment with respect to the gate electrode 3. N ⁺ diffusion region 4 is formed by double implantation of phosphorus and arsenic.

Next, an interlayer insulating film 5 is formed on the gate electrode 3 using a CVD oxide film of about 1500 angstroms, and polycrystalline silicon of about 2000 angstroms is formed on the interlayer insulating film 5 to form a P-channel transistor. Is formed.

Next, the gate electrode 6 for the P-channel transistor is oxidized to form a gate oxide film 7 on both side walls of the gate electrode 6.

Next, after depositing the polycrystalline silicon, anisotropic etching is performed to form a polycrystalline silicon layer 11 on the side wall surface of the gate electrode 6. The P ⁺ diffusion region 8 of the polycrystalline silicon layer 11 is formed by implanting boron, and the region of the polycrystalline silicon layer 11 where boron is not implanted becomes the P channel region 9.

Next, the function and effect will be described. As described above, the operation layer including the P channel region 9 and the P ⁺ diffusion region 8 of the TFT is formed on the side wall surface of the gate electrode 6 with the gate oxide film 7 interposed therebetween. Compared with the structure in which the diffusion region 8 and the channel region 9 are formed via the oxide film 7, a step difference of one step of the polycrystalline silicon layer can be reduced, and the memory cell size is maintained at the same size as the conventional one. In addition, the wiring structure can be simplified. FIG. 1 (b) shows the contact area 1
0 is omitted.

[0018]

As described above, according to the semiconductor device of the present invention, the transistor is formed on the transistor formed on the substrate.
Further, since an operation layer composed of a source / drain diffusion region and a channel region is formed on the side wall surface of the gate electrode of the TFT arranged via the insulating film via the gate insulating film,
In the case where the thickness of the transistor in the vertical direction is reduced and a CMOS type SRAM or the like is formed by using the transistor, the step in the vertical direction can be reduced without increasing the memory size, and the wiring structure is simple. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a CM using a TFT according to an embodiment of the present invention.
FIG. 3 is a diagram for explaining a memory cell of an OS type SRAM.

FIG. 2 is a diagram for explaining a memory cell of a CMOS SRAM using a conventional TFT.

[Explanation of symbols]

Reference Signs List 1 silicon substrate 2 gate oxide film for N-channel transistor 3 gate electrode 4 N ⁺ diffusion region 5 interlayer insulating film 6 gate electrode for P-channel transistor 7 gate oxide film 8 P ⁺ diffusion region 9 P-channel region 10 contact region 11 TFT Polysilicon layer on the side wall of the gate electrode

Claims (1)

(57) [Claims] 1. A source formed in a surface region of a substrate.
/ Drain diffusion region and the channel region between them
That the active layer of the first transistor, and a gate electrode of the first of the first transistor formed via an insulating film on the active layer of the transistor, on the gate electrode of the first transistor A gate electrode of a second transistor formed via an insulating film; a source / drain diffusion region formed on a side wall surface of the gate electrode of the second transistor via an insulating film;
Comprising a channel region between, and a operation layer of the second transistor, the source / drain diffusion region of the first transistor
To the gate electrode of the first transistor.
And the source / drain of the second transistor
The current flowing between the rain diffusion regions is applied to the second transistor.
A semiconductor device configured to be controlled by a gate electrode of the semiconductor device.