JP2658609B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an electrode structure in a bipolar transistor having a comb-shaped electrode structure.

[0002]

Performance parameters of the Related Art Operation Frequency 1GHz or more high-frequency transistor - as data, gain bandwidth f _T is used. As this f _T is high, the gain of the transistor is high, those performance be better. As a method of increasing f _T , it is common practice to reduce the base-collector junction area Ac in order to reduce the collector junction capacitance Cc and shorten the charging time of the collector capacitance. The simplest way to reduce the base-collector junction area Ac is to reduce the emitter width. This not only reduces the effective emitter width but also increases the ratio L _E / Ac between the emitter circumference L _E and the base-collector junction area Ac.

In order to increase L _E / Ac, a comb-shaped electrode structure is often used as a transistor structure. The comb-shaped electrode structure is such that a plurality of elongated rectangular emitters and bases are alternately arranged to face each other,
An elongated rectangular emitter electrode and a base electrode are also formed thereon, and the emitter electrode and the base electrode are connected in parallel by the emitter lead electrode and the base lead electrode, respectively. Are comb-shaped because they are comb-shaped.

A conventional bipolar transistor having the above-mentioned comb-shaped electrode structure will be described with reference to FIGS. 11 to 13 by taking an NPN-type bipolar transistor as an example.
FIG. 11 is a plan view of the conventional bipolar transistor, FIG. 12 is a view for explaining a gold plating process of the bipolar transistor, and FIG. 13 is a cross-sectional view taken along a line DD in FIG. FIG.

A conventional NPN type bipolar transistor having a comb-shaped electrode structure
As shown in FIG. 13, an N-type silicon substrate 1 has a collector region, a P-type base region 2 is formed on one main plane of the N-type silicon substrate 1, and a P-type base region 2 as shown in FIG. A plurality of rectangular N ⁺ -type emitter regions 3 and P ⁺ -type base contact regions 4 are alternately formed therein.

As shown in FIG. 13, a rectangular emitter electrode 6 and a base electrode are formed on the emitter region 3 and the base contact region 4 via an insulating film 5 made of an oxide film or a nitride film, respectively. 7 are formed. Here, each of the emitter electrode 6 and the base electrode 7 has a width of 0.5 to 0.5.
About 1.0μm, thickness about 0.8μm, length 30μ
m, and the electrode interval is 0.5 to 1.0 μm.
m.

This gold electrode is formed by plating a resist mask as shown in FIG. That is, after forming the diffusion layer, a Ti-Pt layer 8 serving as a conductive path for electrolytic plating is deposited on the entire main surface by sputtering. Next, by employing a normal photoresist process, portions other than those where the electrodes are to be formed are covered with a resist film 9 and gold is plated by a plating method using the resist film 9 as a mask.
Next, the resist film 9 is removed, the Ti-Pt layer 8 is selectively removed by a dry etching process using the plated gold as a mask, and the emitter electrode 6 and the base electrode as shown in FIGS. -Electrode 7 is obtained.

Referring to FIGS. 12 and 13, the polysilicon layer 10 contains an impurity (for example, arsenic) for forming the emitter region 3. This polysilicon layer 1
The description of the process of forming 0 is omitted.

Further, the plurality of emitter electrodes 6 are arranged as shown in FIG.
As shown in the figure, the emitter connection electrodes 11 are connected in parallel, connected to the emitter bonding pad 12,
On the other hand, the plurality of base electrodes 7 are connected to the base extraction electrode 1.
3 are connected in parallel, and the base bonding pads 1
4 is connected. The collector electrode is formed on the bottom surface of the N-type silicon substrate 1, and an emitter stabilizing resistor for uniformly operating each emitter in RF is generally provided between the emitter electrode 6 and the emitter extraction electrode 11. However, description of these collector electrodes and emitter stabilizing resistors will be omitted here.

[0010] As documents showing the prior art, "Si Bipol
ar Transistors with 0.5μmwidthEmitter for 20GHz
Oscillator Applications ”(NEC Res & Develop 37 No.9
3 April 1989).

[0011]

As described above, the formation of the gold electrode is performed by plating the gold using the resist film 9 as a mask and then performing a dry etching process to form the underlying Ti-Pt layer serving as a conductive path for the gold plating. 8 is formed by etching. By the way, in the photoresist process,
In the case of forming a pattern for removing resist which is repeatedly arranged like an emitter and a base electrode of a transistor, the amount of the developing solution flowing around the pattern on both ends of the pattern is increased. Therefore, it generally becomes thicker.

For this reason, the plated gold is 0.7-1.
On the other hand, the distance between the plated gold becomes 0.
It becomes as narrow as 3 to 0.8 μm. Where the distance between the gold is small, the etching gas becomes difficult to enter in the dry etching step for removing the underlying Ti-Pt layer 8, so that the Ti-P
There is a problem that the t layer 8 remains and the emitter electrode 6 and the base electrode 7 are short-circuited. Since the oxide film and the nitride film are etched to some extent in the gas used for the dry etching, the insulating film 5 disappears when the overetching is performed, and the silicon substrate 1 is exposed. Therefore,
There is a drawback that the amount of burch is limited and gold electrodes cannot be processed with good yield.

The inventors of the present invention intend to provide a semiconductor device which solves the above-mentioned drawbacks, does not cause a short between the base and the emitter, and can process a gold electrode with a high yield. And said, "Alternately opposed
A plurality of rectangular emitter electrode and base - with the scan electrode
In a bipolar transistor, a plurality of emitter
Pole, a rectangular shape electrically floating outside the base electrode
Equipped with one or more metal patterns "
Which eliminates the above disadvantages,
Considering providing the above-described semiconductor device (see below)
Examples 1 and 2).

[0014] The above semiconductor device is provided outside the base electrode.
A metal pattern that is not electrically connected to any of the base, the emitter or the collector, ie, is electrically floating.
The base electrode and the emitter electrode are short-circuited even if the outermost metal pattern is widened and the above-mentioned remaining Ti-Pt layer is generated. In addition, the width and spacing of a plurality of base electrodes and emitter electrodes inside the metal pattern can be formed uniformly.

[0015] The semiconductor device, more Shoki the arrangement and it is intended to achieve the effect, the present inventors as a result of further extensive research, in the semiconductor device, a metal pattern - down metal pattern - In the cleaning process after the formation of the pattern, the pattern may be bent, floated, adhered, etc., resulting in a short-circuit of the emitter electrode and the base electrode, and a plurality of metal patterns. Of the outer metal patterns
Have the disadvantage that they are easily stressed and easily peeled off.

[0016] The metal pattern - will be described based on the status peeling down in FIGS. 9 and 10, FIG. 9, a rectangular metal pattern which is electrically floating - plan view of the semiconductor device comprising a down , FIG. 10 is a cross-sectional view taken along line CC of FIG.
In each case, the left metal pattern 15 is peeled off. In FIGS. 9 and 10, reference numerals 1 to 14 other than the metal pattern 15 are bipolar transistors having the above-described conventional comb-shaped electrode structure (FIGS. 11 to 1).
Since it is the same as 3), the description is omitted to avoid duplication.

Therefore, the present invention provides the above-mentioned disadvantages (easy peeling).
Disadvantage), and the above-described semiconductor device
To provide a semiconductor device further improved
You.

[0018]

A semiconductor device according to the present invention.
Are the plurality of metal patterns in the semiconductor device.
Is characterized by adopting a configuration in which
ing. That is, the present invention provides an
A plurality of rectangular emitter electrode and base - with the scan electrode
In a bipolar transistor, a plurality of emitter
Pole, a rectangular shape electrically floating outside the base electrode
Metal pattern - Ri Contact comprise two or more down to one side, they contact
Continued ".

According to the present invention , as described above, since a plurality of metal patterns are connected to each other, the metal patterns are not peeled off by the cleaning step after the formation of the electrodes and the metal patterns. Among the plurality of metal patterns, even when the outer metal pattern is subjected to stress, the metal pattern does not peel off. As a result, the metal pattern is brought into contact with the base electrode and the emitter electrode, so that the base and the emitter are not short-circuited.

[0020]

Next, an embodiment of a semiconductor device according to the present invention will be described.
And will be described with reference to the drawings (FIGS. 5 to 7).
Because, for the reference example (the semiconductor device described above),
This will be described with reference to the drawings (FIGS. 1 to 4).

( Reference Example 1 ) FIG. 1 is a plan view of a semiconductor device showing an example (Reference Example 1) of a reference example , and FIG. 2 is a view for explaining a gold plating step of the semiconductor device. FIG. 3 is a sectional view taken along line AA of FIG.

In the semiconductor device shown in FIGS. 1 to 3, an N-type silicon substrate 1 is used as a collector region, and a P-type base region 2 is formed on one main plane of the silicon substrate 1.
A plurality of rectangular N ⁺ -type emitter regions 3 and P ⁺ -type base contact regions 4 are alternately formed therein. A rectangular emitter electrode 6 and a base electrode 7 are formed on the emitter region 3 and the base contact region 4 via an insulating film 5 made of an oxide film or a nitride film, respectively. Here, each of the emitter electrode 6 and the base electrode 7 has a width of about 0.5 to 1.0 μm and a thickness of 0.8 to 1.0 μm.
μm, and the electrode interval is 0.5 to 1.0.
It is about μm.

On the outside of the base electrode 7, two
An electrically floating rectangular metal pattern 15 is formed. The formation of the gold electrodes of the rectangular emitter electrode 6 and the base electrode 7 and the formation of the metal pattern 15
As shown in FIG. 2, this is performed by a plating method of a resist mask. That is, a Ti-Pt layer 8 serving as a conductive path for electrolytic plating is deposited on the entire main surface by sputtering. Next, portions other than those where an electrode is to be formed by a normal photoresist process are covered with a resist film 9, gold is plated using the resist film 9 as a mask, the resist film 9 is removed, and then dry etching is performed using the gold as a mask. By the process, the Ti-Pt layer 8 is selectively removed. As shown in FIGS. 1 and 3, the emitter electrode 6, the base electrode 7, and the metal pattern are formed.
15 is obtained.

That is, a resist having a width of about 0.5 to 1.0 μm, an interval of about 0.5 to 1.0 μm, a thickness of about 1.0 μm, and a length of about 30 μm is repeatedly arranged in a rectangular shape. The emitter pattern 6, base electrode 7, and metal pattern 15 are formed by plating gold on the portion of the pattern to be removed.
Is formed. Here, the pattern of removing the resist on both sides of the repetitive pattern becomes thick due to the large amount of the developing solution flowing around in the PR process. Therefore, the width of the metal pattern 15 after dry etching is: 0.7-1.2 μm
The interval is as narrow as about 0.3 to 0.8 μm.

( Reference Example 2 ) FIG. 4 is a plan view of a semiconductor device showing another example (Reference Example 2) of the reference example . In FIG. 4, the metal patterns 15 are formed one by one on the outside of the base electrode 7, and the length thereof is characterized in that it is longer than the base electrode 7.

In FIG. 1 to FIG. 4, the other parts such as the emitter lead-out electrode 11 are the same as the conventional bipolar transistor having the above-mentioned comb-shaped electrode structure (FIGS. 11 to 13), and the duplication is avoided. Therefore, the description is omitted.
In addition, a Pt-Si layer 8 is formed at the interface between the Ti-Pt layer 8 and Si to make ohmic contact, but the description of this point is omitted.

Next (Example 1 of the present invention), an example of a semiconductor device according to the present invention (Example 1) will be described with reference to FIGS. 5 to 7. FIG. 5 shows the first embodiment .
Is a plan view of a semiconductor device according to FIG. 6 is a diagram for explaining a gold plating step of the semiconductor device, FIG. 7,
FIG. 6 is a sectional view taken along line BB of FIG. 5. Except for the electrodes, the above-described conventional bipolar transistor having a comb-shaped electrode structure (FIGS. 11 to 13) and the semiconductor device shown in Reference Examples 1 and 2 (FIGS. 1 to 4). Is the same as
Omitted.

The electrodes and the metal patterns are formed by plating a resist mask as shown in FIG. That is, T is a conductive path for electrolytic plating over the entire main surface.
An i-Pt layer 8 is deposited by a sputtering method. Next, the portions other than those where the electrodes and metal patterns are formed by a normal photoresist process are covered with a resist film 9, gold is plated using the resist film 9 as a mask, and after removing the resist film 9, the gold is masked. T by dry etching process
The i-Pt layer 9 is removed to obtain an emitter electrode 6, a base electrode 7, and a metal pattern 15, as shown in FIG. Here, the emitter electrode 6, the base electrode 7, the metal pattern 15
Has a width of 0.5 to 1.0 μm, an interval of 0.5 to 1.0 μm,
The length is about 30 μm and the thickness is about 0.8 μm. The metal patterns 15 are connected to each other at both ends as shown in FIG.

[0029] Another example of FIG. 8 (Example 2 of the present invention), the semiconductor device according to the present invention (Example 2)
It is a top view of the semiconductor device shown . In FIG. 8, metal patterns 15 are connected to each other at the center.

In each of the embodiments described above, the collector electrode is formed on the bottom surface of the silicon substrate 1. However, the description of the collector electrode is omitted because it does not explain the characteristic portion of the present invention .

[0031]

In the semiconductor device according to the reference example described above,
As described above, since a metal pattern that is not electrically connected to any of the base, the emitter, and the collector, that is, an electrically floating metal pattern, is provided outside the base electrode. There is an effect that the width and interval of the plurality of base electrodes and emitter electrodes inside the base electrode can be formed uniformly. As a result, the distance between the base electrode and the emitter electrode, which has conventionally occurred, is reduced, and the base-emitter short due to the remaining underlying Ti-Pt layer is eliminated, thereby forming a transistor with a high yield. Can be .

On the other hand, in the semiconductor device according to the present invention,
As described above, the base is provided outside the base electrode.
Since a plurality of metal patterns that are not electrically connected to any one of the source, the emitter, and the collector are formed on one side, and the metal patterns are connected to each other, the electrodes and the metal patterns are formed. There is an effect that the metal pattern is not peeled off by the cleaning process after the formation, and that the metal pattern is not peeled off even if stress is applied to the outer metal pattern among the plurality of metal patterns. As a result, the metal pattern is brought into contact with the base electrode and the emitter electrode, so that the base and the emitter are not short-circuited.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device showing an example of a reference example (Reference Example 1) .

FIG. 2 is a view for explaining a gold plating step of the semiconductor device of FIG. 1;

FIG. 3 is a sectional view taken along line AA of FIG. 1;

FIG. 4 is a plan view of a semiconductor device showing another example (Reference Example 2) of the reference example .

FIG. 5 shows an example (Example 1) of a semiconductor device according to the present invention .
1 is a plan view of a semiconductor device.

FIG. 6 is a view for explaining a gold plating step of the semiconductor device of FIG. 5;

FIG. 7 is a sectional view taken along the line BB of FIG. 5;

FIG. 8 is another example (actual example) of a semiconductor device according to the present invention;
FIG. 11 is a plan view of a semiconductor device according to a second embodiment.

FIG. 9 is a plan view of a semiconductor device having an electrically floating rectangular metal pattern, showing a state where the left metal pattern is peeled off.

FIG. 10 is a sectional view taken along line CC of FIG. 9;
It is a figure showing the situation where the metal pattern on the left is also peeled off.

FIG. 11 is a plan view of a conventional bipolar transistor.

FIG. 12 is a view for explaining a gold plating step of the bipolar transistor.

FIG. 13 is a sectional view taken along line DD of FIG. 11;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Base region 3 Emitter region 4 Base contact region 5 Insulating film 6 Emitter electrode 7 Base electrode 8 Ti-Pt layer 9 Resist film 10 Polysilicon layer 11 Emitter extraction electrode 12 Emitter bonding pad 13 Base extraction electrode 14 Base bonding pad 15 Metal pattern

Claims (3)

(57) [Claims] 1. A bipolar transistor having a plurality of rectangular emitter electrodes and a plurality of base electrodes alternately arranged opposite to each other. A semiconductor device comprising two or more rectangular metal patterns floating on one side and connected to each other. 2. The semiconductor device according to claim 1 , comprising three metal patterns, which are connected to each other at both ends. 3. The semiconductor device according to claim 1 , comprising three metal patterns, which are connected to each other at the center.