JP2656504B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a memory circuit and an analog circuit mounted on a single chip.

[Conventional technology]

Conventionally, the analog circuit of a memory circuit mounted on the same chip is described in the 1987 VLSI Circuit Symposium.
mposium on VLSI Circuits Digest of Technical Paper
s, pp 107-108.). In this paper, an EDL with a storage capacity of 16 words x 8 bits (128 bits)
(E mitter C oupled L ogic) form a static random access memory (S tatic R andom A ccess M emory-
Hereinafter SRAM abbreviated) two and, 8-bit resolution digital-to-analog converter (D egital to A nalog C onve
rter- hereinafter DAC abbreviated) comprises one of a semiconductor device is disclosed which has a function of outputting converted to an external analog signal to a digital signal in the SRAM 256 gradations (2 ^8). This device was developed for color modulation signal display of color bitmap display such as a graphic display terminal of a computer. By using three of these devices corresponding to the primary colors red, green and blue in the display, color An image can be displayed. EDL-type SRAM is Nikkei Electronics, No. 5 May 20, 1985, is used as a color appendix which details etc. pp 257 pp ～281 stated (abbreviated as C olor L ook-up T able- less CLT) , All displayable 2 ²⁴ (2
^{8 / chip × 3 chips)} color of any 2 ¹² (2
^{(4 / chip × 3 chips} ) A color image of a combination of colors can be displayed. The combination color is specified by data stored in the SRAM in each chip.

The above ECL type SRAM is a bipolar transistor (hereinafter referred to as Bip
Tr) (abbreviated as Tr).
By multiplexing two SRAMs alternately, the speed is further doubled. Also, DAC is suitable for high-speed B
High-speed, low-noise design is performed using ip Tr. This enables high-speed,
A low noise color modulation signal can be generated.

[Problems to be solved by the invention]

The above prior arts have insufficient consideration for reducing the occupied area and the power consumption, and have a problem in achieving higher integration. In the bitmap display method, it is necessary to prepare a large-capacity image memory for storing color modulation image data for each picture element to be displayed, a so-called frame memory. For example,
In order to the 500 × 500 picture elements of the display is 2 ¹² colors previously mentioned, it is necessary to prepare a 12 × 500 × 500 = 3 × 10 6 -bit frame memory. It is desirable that this frame memory and the above-mentioned DAC be formed on the same chip. However, since the ECL type SRAM composed of Bip Tr used in the above-mentioned conventional technology has a large occupied area and power consumption, it is impossible to increase the capacity as described above. Was the limit. Therefore, the frame memory needs to be provided as a separate chip, which causes problems such as an increase in the volume of the entire display device, an increase in the number of wirings between the semiconductor devices, and a decrease in reliability. In addition, an increase in the number of input / output pins and noise of the integrated circuit causes another problem that it is difficult to increase the speed. That is, it is difficult to transmit a high-speed signal because the connection wiring between the semiconductor devices has a large parasitic capacitance. For this reason, many low-speed signals are transmitted in parallel,
This is multiplexed in the integrated circuit by the parallel / serial conversion technique to form one high-speed signal. However, the number of input / output pins for transmitting the low-speed signal increases, and the number of these input / output pins increases. When the potential or current of the low-speed signal changes at the same time, problems such as generation of large noise occur.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art and provide a semiconductor device suitable for mounting a large-capacity memory and an analog circuit on the same chip.

[Means for solving the problem]

The above object can be achieved by using a memory constituted by MOS transistors (hereinafter abbreviated as MOST) suitable for high integration as a memory and integrating it with an analog circuit in one chip.

[Action]

Because MOST memory has a small area and low power consumption, large-capacity memory and analog circuits can be mounted on the same chip. As a result, the above-described problems of the related art can be solved, and a high-speed, low-noise semiconductor device including a large-capacity memory and an analog circuit can be realized.

〔Example〕

 Hereinafter, details of the present invention will be described with reference to examples.

FIG. 1 is an embodiment showing the basic concept of the present invention. In the figure, 100 is a semiconductor chip, 10 is a memory composed of MOST, 2
0 DAC, analog-to-digital converter (A nalog to
D igital C onverter- to hereinafter abbreviated as ADC), the operational amplifier is an analog circuit and the like. Here, the configuration of the memory may be a so-called random access memory (Randam Access Memory) capable of reading and writing data at an arbitrary address at all at random according to the purpose, or serially such as a shift register. Even if it is a format that reads and writes data, it also has these two functions, and it is an IEE Journal of Solid-State Circuit, SC-1
Vol. 9, No. 6, December 1984, pp. 999-1007 (IEEE Journ
al of Solid−Stete Circuits Vol.SC−19, No.6, Dec.19
84, pp. 999-1007.) May be used.

According to this embodiment, the memory has a small occupation area and power consumption, and is constituted by MOST memory cells suitable for high integration. Therefore, a large-capacity memory and an analog circuit can be easily mounted on the same chip. In this embodiment, the memory and the analog circuit are connected by wiring on the same chip. Therefore, the wiring length becomes short, and the parasitic capacitance of the wiring becomes extremely small, so that a signal can be transmitted at high speed. Further, since the speed is high, the number of wirings can be reduced, and noise at the time of simultaneous change in potential or current can be reduced. Even if the method of transmitting a large number of signals in parallel and adopting the technique of parallel-to-serial conversion to increase the speed in the same way as in the conventional technology is adopted, even if the signal potential or current changes because the wiring length is extremely short. Noise is negligibly small, and a high-speed, low-noise large-capacity memory and a semiconductor device in which analog circuits are mixed can be realized.

FIG. 2 shows another embodiment that further utilizes the advantage of integrating a marriage MOS memory and an analog circuit into one chip. In this embodiment, a fuse 10f for repairing a defect in a memory and a fuse 20 for trimming (fine adjustment) various analog characteristics of an analog circuit.
The feature is that f is the same method. In a large-capacity memory, a spare memory cell is prepared in advance in order to increase the manufacturing yield, and if a defective memory cell is found as a result of the test, the defective memory cell is replaced with the spare memory cell to be a good product. Defect relief technology is adopted. The defect relieving fuse functions as a switch for replacing the defective memory cell with the spare memory cell. In the analog circuit, the amplification factor of the multiplication amplifier, ADC,
In some cases, it may be necessary to perform trimming (fine adjustment) on the values of the reference voltage and current source used in the SAC based on the performance test result to achieve high accuracy. A fuse is used as a switch for this trimming. This fuse is generally formed of Al wiring resistance, polysilicon wiring resistance, or the like, and is blown by irradiating a laser beam or flowing a large current. By sharing the material, forming method, cutting method, etc. of this fuse for memory and analog circuits, the manufacturing process, test process, cutting process and the equipment used for them can be made the same, and the efficiency of each process can be improved. Becomes possible. In this embodiment, the fuse is used as the resistor itself in the circuit for trimming the analog circuit portion, and this is changed by cutting off a part of the fuse with a laser beam, or using a polysilicon fuse. By heating this with laser light, the resistance value can be adjusted by changing the distribution of impurity concentration.

FIG. 3 shows another embodiment in which a logic circuit 30 is added to the embodiment of FIG. According to the present embodiment, the logic circuit 30
Various logical operations can be performed, and 10, 20 can be controlled based on the results, so that a more multifunctional semiconductor device can be realized. Here, 30 is equipped not only with a simple logic circuit but also with a microcomputer or the like, so that the processing capacity can be further increased.

FIG. 4 shows another embodiment of the present invention applied for color graphic display. Reference numeral 11 denotes an image memory for storing image data corresponding to each picture element to be displayed, and is constituted by a MOS memory. It is input from image data 101 for each picture element. Since the input and output of the memory can be performed simultaneously in parallel, it is preferable that the memory is a dual port type memory in which the stored data can be rewritten while the display data is output. 21 converts the output of 11 into an analog signal and outputs it to 102 as a color modulation signal of each picture element.
AC. Reference numeral 31 denotes a control logic circuit for controlling the operations of 11 and 21, and a control signal is input from 103.

According to this embodiment, an image memory for high-speed, low-noise color graphic display and an ADC non-image memory in which the ADC is integrated into one chip can be realized.

FIG. 5 shows an embodiment in which an input logic circuit 32 is added to the embodiment of FIG.
This is an embodiment in which logical operation processing of input data is enabled.
According to the present embodiment, various arithmetic processing such as generation of an arbitrary figure such as a circle or a square can be performed using the input logic circuit. Further, by providing each of the logic circuits 31 and 32 with the same function as a microcomputer or the like, higher-level processing can be performed and higher performance can be achieved.

FIG. 6 shows an embodiment in which the above-mentioned coloring table CLT41 is added. According to the present embodiment, as described above, the content of 11 can be arbitrarily colored according to the content of the CLT to expand the range of colors that can be displayed.

FIG. 7 shows the relationship between the memory 11 and the CLT 41, and between the CLT 41 and the DAC 21.
Between 51 and 52 parallel-to-serial conversion circuits are inserted between them to increase the output speed. According to this embodiment, the parallel-serial circuit allows the output signal to be multiplexed by the amount of multiplexing the parallel signal. This is suitable for increasing the number of picture elements to be displayed and increasing the number of display times (the number of scans) per unit time to create a wobble on the screen. As described later, the memory configuration shown in FIGS. 6 and 7 is highly integrated using a one-transistor type memory cell as shown in FIG. 11, and reference numeral 41 is shown in FIG. It is conceivable to increase the speed by using such an SRAM or an ECL type SRAM using the above-mentioned Bip Tr.

FIG. 8 shows an embodiment in which an analog / digital conversion circuit ADC is added to the input section of the embodiment of FIG. Input terminal 1
The analog signal input from 04 is converted into a digital signal by the ADC 22 and supplied to the input logic circuit 32.

According to the present embodiment, in addition to the digital display signal input from 101, an analog signal such as a television video signal input from 104 can be simultaneously stored in the memory 11, and on the same display screen, It is possible to simultaneously display the output of a computer or the like and a television image. Also, 32 allows arithmetic processing between the signals 101 and 104 to be performed, and it is also possible to superimpose and display both. Further, according to this embodiment, it is also possible to convert a TV video signal or the like of 104 once into a digital signal, store it in 11, and output that signal at a sweep frequency different from the input, and a video device of a different specification. It can also be used as a specification conversion device between them.

In the present embodiment, the reference voltage or current serving as a reference for the operation of the ADC 22 and the DAC 21 is a reference voltage / current generation circuit 23.
Output is shared. As a result, the chip input / output characteristics of analog signals can be made exactly the same, for example, the zero-scale level, full-scale level or DC level of 22 and 21 can be adjusted to the same level. Also, in order to reduce the power consumption or protect a device which has been reduced in size and has a low breakdown voltage, Japanese Patent Application Nos. 56-57143 and 56-16869.
8 has a means for lowering the power supply voltage inside the chip, such as that disclosed in Section 8, etc., and employs a so-called on-chip voltage limiter system that operates some or all circuits in the chip with this lowered voltage. In this case, the reference voltage for the operation is shared with the voltage generated by the circuit 22,
Alternatively, it can be generated and used based on this. As a result, the operating voltage of the entire chip is standardized, and an operation with high overall matching is enabled.

In the present embodiment, the signal input from 104 may be a signal separated in advance into three origins of color display or a signal not separated. If they are not separated, a circuit for separating the signals according to the format of the data stored in the memory 11 may be provided inside the chip. In this embodiment, an example in which an ADC is added to the embodiment of FIG. 5 has been described.
It is possible to add C.

FIG. 9 is a more specific example of the DAC 21 of the embodiment shown in FIG. As shown in the figure, reference numeral 21 designates R, G, and B DACs for each of the three primary colors red, green, and blue for color display, and externally outputs modulation signals 102R, 102G, and 102B for the three primary colors. These are synthesized on the display screen, and according to the so-called additive color mixing principle,
Various colors are displayed. Therefore, according to the present embodiment, a color image can be displayed with one chip. In the above description, the three primary colors of the color display are described as red, green, and blue. However, the three primary colors differ depending on the color generation method of the display device, and are not limited thereto. For example, in a color printer device or the like, yellow, cyan, and magenta are three primary colors.
In some cases, a coloring method based on subtractive color mixing is used. When the present embodiment is applied to such an apparatus, DACs may be used corresponding to the respective primary colors.

As described above, according to the present invention, a semiconductor device with a large-capacity memory and a DAC can be realized. However, in some cases, a larger-capacity memory may be required. In such a case, various modifications can be considered. For example, in FIG. 9, only one color is prepared for the DAC, all memories are used for storing one color data, and these are used in parallel with three chips to generate three primary colors. According to this, the memory capacity per color can be tripled. Also, DAC
Is provided for three colors in the same manner as in FIG. 9, and is used as it is when the memory capacity is small. When a large memory capacity is required, the DACs for two colors are stopped and only one color is used. Switching means for operating and using the memory 11 as a memory for one color is provided in a chip in advance, and a method of using three chips as described above is also conceivable. According to this method, it is possible to cope with both cases where the required memory capacity is small and large. In FIG. 9, the memory 11
It is also conceivable to provide an additional terminal in advance and connect an additional memory to this terminal from the outside. The various methods described above can be similarly applied to the case where a DAC is provided as shown in FIG.

As described above, by using MOS memory,
A semiconductor device in which a large-capacity memory and an analog circuit are integrated into one chip can be realized. Various types of memory cells as shown in FIGS. 10 to 12 can be used as the memory cells constituting the MOS memory. FIG. 10 is a flip-flop type static memory cell comprising four MOS transistors and two resistors, FIGS. 11 and 12 are dynamic type memory cells, and FIG. FIG. 12 shows a one-transistor memory cell formed of one capacitor, and FIG. 12 shows a three-transistor memory cell formed of three MOS transistors. The cell of FIG. 10 is capable of low-noise operation, and is suitable when low noise is particularly required.
Further, since a resistor is used as the load of the flip-flop circuit, it has a feature that its occupied area can be reduced as compared with a type using a p-channel MOS transistor instead of a resistor. The cell shown in FIG. 11 has a small number of elements, is excellent in high integration, and has low power consumption. Therefore, the cell shown in FIG. 11 is suitable particularly when a large capacity memory is required. Cells of FIG. 13 is, Q _A
The information charge stored in the gate capacitance of the current of Q _A is controlled, since a large signal to the read data line D _R is output, it is suitable for high S / N operation, especially at high S / N operation Suitable when required.

FIG. 13 shows a specific example of the circuit configuration of the embodiment shown in FIG. The memory cell array 12 of the memory 10 is configured using a one-transistor memory cell MCI suitable for high integration. In addition, a so-called folded data line in which a data pair line D, is arranged in parallel and a memory cell is arranged at one of intersections with a word line W so that S / N operation can be performed with low noise. The configuration is adopted. Peripheral circuits composed of such as a sense amplifier SA for amplifying the small signals from the memory cell 13 is constituted by BiCMOS circuit that combines Bip Tr and CMOS (C omplementary M OS). In other words, when high integration and low power consumption are required, such as SA, or when driving a small capacity load, low power consumption, a CMOS circuit with a small occupied area is used to drive a large capacity load, When it is necessary to amplify a small signal at a different speed and with high sensitivity, a Bip Tr circuit or a circuit combining CMOS and Bip Tr is used. In addition to the above, as a dynamic memory using BiCMOS,
The circuits disclosed in JP-A-61-142594 and JP-A-61-170992, etc., to which the techniques disclosed in JP-A-61-170992 can be applied as they are, are also constituted by BiCMOS. In 20, for example, ADCs and DACs that need to process minute high-speed signals are constituted by Bip Tr circuits, and analog switch circuits and the like are constituted by CMOS circuits having a small offset. As a result, a high-speed, high-accuracy ADC or DAC can be realized. The reference voltage / current generation circuit shown in FIG. 8 can be a highly stable reference voltage / current generation circuit using a well-known Bip Tr band gap generation circuit.
A current is obtained. Furthermore, if the CLT 41 and the parallel-to-serial conversion circuits 51 and 52 shown in FIG. 7 are configured using Bip Trs, high-speed operation becomes possible. In the 30 logic circuits as well,
A high-speed, low-power-consumption, highly-integrated logic circuit can be realized by using CMOS, Bip Tr, or a combination of both circuits.

As described above, a semiconductor device in which a high-speed, low-power-consumption large-capacity memory and a high-speed, high-precision analog circuit are integrated can be realized. Here, an example is shown in which a BiCMOS circuit is used except for the memory cell. However, particularly when low power consumption or low manufacturing cost is required, the circuit may be configured only with a CMOS circuit.

As described above, according to the present invention, by integrating the large-capacity memory and the analog circuit into one chip, the number of wirings between them can be reduced and the wiring length can be shortened. it can. However, when the memory is formed of one-transistor memory cells, a transient current may flow through the power supply line during a data line charge / discharge operation or the like, which may affect the analog circuit unit as noise. Hereinafter, an embodiment capable of reducing the noise via the power supply line will be described.

FIG. 14 shows an embodiment thereof. In this figure, reference numeral 300 denotes a package, and reference numerals 311 and 312 denote pins of the package, which are used here as power supply pins. 301 is a semiconductor chip housing frame, 321 and 322 bonding wires, 331 to 333 are package pins and bonding pads 111 and 112 on the semiconductor chip.
And is usually formed of Al or the like.

111 and 112 are bonding pads for power supply including ground of the memory 11 and the analog circuit 123, respectively, and 121 and 123 are power supply wires on the chip.

According to this embodiment, the power supplies for the memory and the analog circuit are:
Since power is supplied through separate pins, bonding lines, bonding pads, and power supply wiring, noise interference does not occur between circuits. Also, depending on the case, as shown by a broken line 333 in the figure, there is also a method in which the package pin and the bonding wiring are common and both are separated from the bonding line.Since the package pin and the bonding wiring have relatively small inductance, resistance, etc., This method can also reduce noise.

FIG. 15 shows another embodiment of the low-noise feeding method. In this embodiment, power supply to both circuits is separated by power supply wiring on the semiconductor chip. Although low noise can be expected by this, furthermore, in this embodiment, the power supply wiring of the analog circuit includes a resistor R _W ,
Dekappungu circuit is provided comprising a capacitance C _W.

According to the present embodiment, noise generated in the power supply due to the operation of the memory is removed by the decoupling circuit.
Noise does not affect analog circuits. The concept of the decoupling circuit used here can be applied to the embodiment shown in FIG. The resistance of the Al wiring can be used as the resistance of the decoupling circuit, and in some cases, a more effective decoupling circuit can be obtained by using the self-inductance. As the capacitance, a wiring capacitance can be used, but in order to further enhance the effect, an inversion layer capacitance of a MOS transistor having a small area and a large capacitance value may be added. Furthermore, it is conceivable that a semiconductor chip is partially formed with a circuit only on the main surface, a capacitance is formed on the back surface of the chip, and this is used as _CW .

In the above-described embodiment, the power supply method for the memory and the analog circuit has been described. However, even when there are a large number of circuits as shown in FIGS. 7 and 8, the same low-noise power supply method as described above can be used according to the purpose. . For example, it is conceivable that the above-described various low-noise supply voltages are used alone in a reference voltage / current generating circuit or the like that requires particularly low noise.

As mentioned above, the method of noise reduction by the power supply method has been described.
There is also a method of taking advantage of the fact that the memory and the analog circuit are integrated, and reducing the noise in consideration of the operation timing of both circuits. For example, as shown in Figure 16, the switch provided in the R _W series, during timing noise is generated by the operation of the memory 10 by turning off the switch, it is conceivable to disconnect the power line. According to this method, even when noise occurs, the power supply is completely separated, so that the influence of the noise can be completely eliminated. Incidentally, the resistor R _W as FIG. 17
Taking a method which also serves as an on-resistance of the MOS transistor Q _R,
The switch and the resistor can be realized by one MOS transistor. That is, the pulse phi _R, typically Q _R is turned on, the on-resistance so as to act as a R _W,
The noise occurring, may be set to turn off the Q _R. In addition,
Equivalent noise reduction can also be achieved by simultaneously performing the timing at which noise is generated at 10 and the timing at which there is no problem even if some noise enters from a power source or the like at 20. For example, when applying to color graphic display, 10 is the timing of the charge / discharge operation of the data line where noise is most likely to occur, and 20 DAC is the blanking at the time of horizontal or vertical sweep of the display that causes little problem even if noise occurs. By matching the operation timing, noise can be reduced.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited to these embodiments. For example, as an application range of the present invention, color graphic display of a computer terminal or the like has mainly been described. However, the present invention is not limited to this, and an image memory with a DAC such as a color printer, a laser beam printer, a high-definition digital TV, a VTR, or a measurement device The present invention can be applied to all cases where a large-capacity memory and an analog circuit are required, such as converting an arbitrary amount of an analog substance into a digital signal in a device or a control device and storing the digital signal in a memory.

〔The invention's effect〕

According to the present invention, a large-capacity memory and an analog circuit can be mounted on the same chip, thereby realizing a high-capacity, low-noise large-capacity memory and a semiconductor device in which analog circuits are mixed.

[Brief description of the drawings]

1 to 3 are diagrams showing a basic embodiment of the present invention, FIGS. 4 to 9 are diagrams showing an embodiment in which the present invention is applied to a graphic display, and FIGS. FIG. 14, FIG. 14, FIG. 15 to FIG.
FIG. 1 is a diagram showing an embodiment relating to the low-noise feeding method of the present invention. 100: Semiconductor chip 10: Memory 20: Analog circuit, 30: Logic circuit 300: Package

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-59-61040 (JP, A) JP-A-61-77357 (JP, A) JP-A-57-20995 (JP, A) JP-A-62 212713 (JP, A) JP-A-63-244486 (JP, A) JP-A-64-13561 (JP, A) JP-A-60-136364 (JP, A) JP-A-59-105378 (JP, A) JP-A-59-86253 (JP, A) JP-A-62-122262 (JP, A) JP-A-57-160215 (JP, U) JP-B-55-51389 (JP, B2)

Claims (9)

(57) [Claims] 1. A semiconductor device comprising a memory circuit and an analog circuit provided between a first potential and a second potential on the same semiconductor chip, wherein the memory circuit comprises a MOS transistor. A bonding pad connected to the first potential and provided in common with the memory circuit and the analog circuit, the bonding pad being a dynamic random access memory comprising the MOS transistor; And a resistor connected between the power supply input of the analog circuit and a capacitor connected between the power input of the analog circuit and the second potential on the same semiconductor chip. A semiconductor device, comprising: 2. The method according to claim 1, wherein the resistance element is realized by an on-resistance of a switch MOS transistor, and the switch MOS transistor is turned off when noise occurs in the memory circuit which is a dynamic random access memory including the MOS transistor. The semiconductor device according to claim 1, wherein 3. The memory circuit according to claim 2, wherein the memory circuit is a dynamic random access memory including the MOS transistor, the memory circuit is a memory for displaying an image, and the memory is a dynamic random access memory including the MOS transistor in which the switch MOS transistor is turned off. The timing of charging / discharging operation of the data line of the memory circuit and the timing of blanking operation at the time of horizontal or vertical sweep of the screen display are substantially simultaneous at the time of occurrence of circuit noise. 3. The semiconductor device according to item 1 or 2. 4. An apparatus according to claim 1, wherein said analog circuit includes at least one of an analog-to-digital converter, a digital-to-analog converter, and an operational amplifier. 3. The semiconductor device according to claim 1. 5. The fuse according to claim 1, wherein a defect relief fuse of said memory circuit, which is a dynamic random access memory comprising said MOS transistor, and a characteristic trimming fuse of said analog circuit are of the same type. Item 5. The semiconductor device according to any one of Items 4 to 4. 6. A semiconductor device comprising a memory circuit and an analog circuit provided between a first potential and a second potential on an identical semiconductor chip, wherein the memory circuit comprises a MOS transistor. Wherein said analog circuit includes at least one of an analog-to-digital converter, a digital-to-analog converter, and an operational amplifier, and wherein said memory circuit is a dynamic random-access memory comprising said MOS transistor. And a logic operation circuit for controlling the analog circuit including at least one of an analog-to-digital converter, a digital-to-analog converter, and an operational amplifier on the same semiconductor chip. Semiconductor device. 7. The memory circuit, which is a dynamic random access memory including the MOS transistor, is a memory for displaying an image, and the analog circuit converts pixel data output from the memory for displaying an image into an analog signal. 7. The semiconductor device according to claim 6, wherein the semiconductor device is a digital / analog converter for performing conversion. 8. The semiconductor device according to claim 6, wherein said logical operation circuit is a microcomputer. 9. The fuse according to claim 6, wherein a defect relief fuse of said memory circuit which is a dynamic random access memory comprising said MOS transistor and a characteristic trimming fuse of said analog circuit are of the same type. Item 9. The semiconductor device according to any one of items 8 to 8.