DE3832456A1 - Semiconductor device with a memory circuit and an analog circuit - Google Patents

Abstract

The present invention relates to a one-chip semiconductor device for processing image signals. Since a conventional semiconductor circuit, which comprises an ECL memory, requires a large number of chips, such a system configuration suffers from a variety of disadvantages. The present invention provides a one-chip semiconductor device for processing image signals, a high-volume MOS memory, in particular a dynamic memory with direct access, an analog/digital converter circuit or a digital/analog converter circuit, and a control circuit for controlling the digital circuit being arranged on a single chip. The present invention discloses the healing of a fault, an energy supply method and also a novel mode of operation. <IMAGE>

Description

The present invention relates to a semiconductor element with a memory circuit and an analog circuit, which both are arranged on the same chip.

A semiconductor device with a memory circuit and an analog circuit, both arranged on the same chyp is already in "1987 Symposium on VLSI Circuits Digest of Technical Papers, "pp. 107-108. This document discloses a semiconductor element which with two static ECL (emitter coupled logic) memories with direct access (hereinafter referred to as "SRAMs") with a memory capacity of 16 words at 8 bits (= 128 Bit) and with a digital / analog converter (hereinafter referred to as "DAT"), which has an 8-bit accuracy owns and which has the function, a digital one Signal in the SRAM into an analog signal of 256 levels (2⁸) to convert and emit this analog signal to the outside. This component has been developed to be a colored Display signal of a color bit measurement display e.g. B. to generate a graphic display of a computer, by using these components as a result of three basic colors, d. H. Red, green and blue displayed a color image can be. The ECL SRAM is used as a color reference table (color look-up table) (hereinafter referred to as "CLT"), as in "Nikkei Electronics," May 20, 1985, pages 257-281 described, used and can display a color image, which from a combination of any 2¹² (2⁴ / chip × 3 Chips) among all 2²⁴ (2⁸ / chip × 3 chips). The too combining colors are determined by the storage data of the SRAM determined in each chip. In addition to the fact that the  ECL SRAM described above is a high speed memory with a bipolar transistor (hereinafter referred to as "Bip Tr") can also be a double-speed mode of operation can be achieved when two SRAMs as in operation a pipeline operation operated alternately will. The design for high speed and one low noise is used for the DAC one suitable for high speed operation Bip Trs realized. Accordingly, color display signals at high speed and low noise what is required for a color bit display.

However, the known technique described above has not been found in sufficiently reducing the occupancy area as well of energy consumption is considered and is not yet free from the problem of achieving a higher integration density. In the bit map display system for each pixel or so-called "frame memory" (frame memory) for storing the image data for a color display a large capacity image memory can be manufactured. Around with the 2¹² colors described above 500 × 500 pixels display, for example, 12 × 500 × 500 = 3 × 10⁶ Bit frame memories are generated. The frame memory and DAC described above are preferably on the same chip integrated. However, that's because of the one described above and existing Bip Tr used in the known art ECL SRAM a large occupancy area and high energy consumption has, it is not possible to have such a large capacity to obtain, with CLTs of at most a few 100 bits can be integrated on the same chip. Consequently the image memory must be arranged as a separate chip, whereby the volume of the display device as a whole or the number of wirings between the Semiconductor components increase and thus operational reliability is reduced. Since the number of input and Output contact pins and thus the noise increases  difficult to operate at a higher speed. With in other words, it is difficult to get a signal at high speed to transfer because the wiring between the semiconductor components have a high parasitic capacitance have. For this reason, a procedure has been used which has a large number of signals at low Transmits speed and parallel to each other, this using a parallel series implementation technique within an integrated circuit can be multiplied, whereby a single high speed signal is obtained. However this method is also not without problems in that the number of input and output pins for the transmission of signals at low speed increases and there is a high level of noise when that Potential or the current of a large number of signals low speed changes at the same time.

According to the present invention, a memory with MOS Field effect transistors, especially for a higher one Integration of suitable transistors (hereinafter referred to as "MOST" referred to) used as memory, this memory is applied as an analog circuit on the same chip.

The MOST comprehensive storage has a small occupancy area and low energy consumption. Consequently can have a high capacity memory and an analog circuit be placed on the same chip. this makes possible it, the prior art inherent described above Solve problems and a semiconductor device to create in which a high-capacity memory High speed operation with low noise level has and an analog circuit as an additional circuit is present.

The present invention is in a semiconductor device for integrated circuits, which is a digital circuit  and includes an analog circuit, a switching circuit in front, which makes it possible from the outside directly on the memory circuit and the analog circuit in accordance with a test signal in the semiconductor component to access. The present invention generates image data for a high tint (contrast) through temporal processing of the Image data from the memory or in chronological order of a spatial section of the memory circuit using the storage circuit for storage the digital image data and a D / A converter circuit to deliver an analog video signal after receiving the image data, which are entered in the semiconductor component and optionally enables a high contrast display Use of this image data.

According to the switch arrangement described above, the direct access to digital and analog circuitry under the Control of a switch take place so that the test time (test time) shortened and operational safety improved can be. Because of the temporal or spatial processing (time or spatial processing) the number of data bits can enlarge from the image memory as a digital circuit selective high-contrast display possible.

A first object of the present invention is to provide a To create semiconductor device, which described the above Solves problems of the prior art and which to accommodate a high capacity storage and an analog circuit on the same chip is.

Another object of the present invention is to provide a Semiconductor component for an integrated circuit create which has a large memory and one on the same Chip arranged analog circuit and which runs a test.  

Another object of the present invention is a semiconductor device for an integrated circuit to create which by using an image memory and a D / A converter circuit, both on the same Are designed a new mode of operation of a chip Display guaranteed.

These and other tasks as well as many of the added benefits this invention will be readily understood if the invention itself by referring to the following, detailed coating as well as taking into account of the accompanying drawings is easier to understand.

Figs. 1 to 3 show basic embodiments of the present invention;

FIGS. 4 to 9 show a graphical display suitable embodiments of the present invention;

Figs. 10 to 13 show specific embodiments of the memory, and the like of the present invention;

Figs. 14 to 17 show embodiments of the present invention, which relates to a method for supplying power with low noise;

Fig. 18, 19 (A) and 19 (B) show embodiments of the present invention that facilitate testing; such as

Fig. 20 (A) to 23 show embodiments of the present invention which relates to a novel operation by use of the present invention.

Preferred embodiments of the present invention are described below with reference to the drawings. Although the characterizing part of each embodiment will be described in the following description in a strongly emphasized manner, the present invention is not limited to this in detail, but naturally also includes the mutual combination of the embodiments. For example, the melting element shown in FIG. 2 can be used in all configurations of the invention. The combination of the configurations shown in FIGS. 13 to 23 with other configurations also falls under the subject matter of the present invention.

Fig. 1 a shows the basic principle of the present invention representing embodiment. In the drawing, reference numeral 100 represents a carrier body, in particular a semiconductor chip, reference numeral 10 a data storage device, in particular a memory, which consists of field effect transistors, in particular MOST, and reference numeral 20 a data converter unit, in particular an analog circuit composed of a DAC or an analog / Digital converter (hereinafter referred to as "ADC"), an operational amplifier and the like. The memory can be a so-called random access memory, which is able to read from any address completely arbitrarily or to write data to it, such as a shift register or a dual-channel memory with the two functions as described in IEEE Journal of Solid-State Circuits, Volume SC-19, No. 6, Dec. 1984, pages 999-1007, depending on the intended application.

According to the present embodiment, the memory exists from memory cells from MOST with a small space, low energy consumption and suitability for one high integration. As a result, a memory with large Capacity and an analog circuit in a simple manner be attached to the same chip. With this configuration  are the memory and the analog circuit using a Conductor, especially wiring, on the same chip electrically coupled together. For this reason, the Wiring length can be reduced, reducing the parasitic Capacity of the wiring becomes extremely small, so that the Signals can be transmitted at high speed. Since the speed is high, the number of wirings can be as well as the noise that arises when the Potentials or currents change simultaneously, are reduced. In a process that uses a large number of parallel signals and transmits these signals undergoes a parallel-series conversion to speed in the same way as in the prior art Technology to further increase known technology continues the noise at the time the signal potential changes negligible (since the wiring length is extreme is short) and created a semiconductor device can be in the one at high speed working, low noise memory with large Capacity next to an analog circuit.

FIG. 2 shows another embodiment of the invention, which furthermore makes optimal use of the advantages which result from the configuration in which the MOS memory and the analog circuit are mounted thereon. This embodiment is characterized in that the memory has a remedying means and the analog circuit has a device for controlling the characteristics of the analog circuit, in particular a redundancy fuse or fuse element 10f of the memory and a fuse element 20f for trimming the various analog The characteristics of the analog circuit have the same design. In order to improve the output when manufacturing a large capacity memory, excess memory cells are manufactured in advance and used as a replacement for memory cells if the latter are found to be defective after a test. This is the so-called "redundancy technique". The redundancy melting element has the role of a switch if the faulty memory cell is replaced by a redundant, ie excess, memory cell. In the analog circuit, it is sometimes necessary to trim the gain of the operational amplifier, the reference voltage and the value of the current strength used in the ADC and DAC, etc. in accordance with a test result in order to obtain higher accuracy. A melting element is used as a switch for this trimming. The melting element consists largely of an Al wire or a polysilicon wire (polysilicon) and is melted when a laser beam is directed onto it or a high current passes through it. If the design of this fusing element such as the material, the manufacturing method, the separation method and the like for the memory and the analog circuit is standardized, the manufacturing method, the testing method, the separation method and the various devices and apparatus used for these steps can be standardized and each Procedures are made extremely efficient.

Incidentally, it is when trimming the analog circuit part concerns this configuration, possible that Melting element as a resistor in the circuit itself too use and the resistance value by separating a To change part of the melting element arrangement or the Resistance value by heating a polysilicon melting element by means of a laser beam, creating the contamination profile the impurity concentration changes will adjust.

FIG. 3 shows a detailed configuration of the present invention, which is formed by adding a control unit, in particular a logic circuit 30 to the configuration shown in FIG. 1. According to this configuration, various types of logical calculations can be carried out by the logic circuit 30 , so that a control of 10 and 20 can also be carried out. Accordingly, a semiconductor device with additional multiple functions can be created. At this point, in order to further increase the operating capacity, it is possible to mount not only a mere logic circuit but a microcomputer or the like as part 30 .

Fig. 4 shows a detailed embodiment of the present invention which is used for a color graphic display. Reference numeral 11 relates to an image memory for storing the image data corresponding to each picture element (pixel) of the display. The image memory consists of a MOS memory. The image data which is fed into the terminal 101 for each pixel is supplied to the memory 11 . In order to carry out the input and output simultaneously in parallel with one another, the image memory is preferably a dual port memory, which enables the memory data to be rewritten during the output of the display data. Reference numeral 21 represents a DAC which converts the output of 11 into an analog signal and outputs this analog signal as a color display signal of each pixel via the terminal 102 . Numeral 31 denotes a control logic circuit for controlling the operation of FIGS. 11 and 21 , and a control signal is input through the terminal 103 .

According to this embodiment of the present invention an image memory equipped with a DAC was created in which a working at high speed however, low noise image memory for a color graphic display and a DAC are arranged on a single chip.

FIG. 5 shows a further detailed configuration of the present invention, which is formed by adding a data conversion device, in particular an input logic circuit 32 to the configuration shown in FIG. 4, so that the input data can be subjected to processing in the form of a logical calculation. According to this embodiment, due to the use of the input logic circuit, various types of calculation treatments such as e.g. B. a circle or a square. Higher level machining can also be achieved by equipping each logic circuit 31, 32 with a microcomputer equivalent function, whereby higher performance can be achieved.

FIG. 6 shows a detailed configuration of the present invention, in which the color reference board CLT 41 already described is added. According to this configuration, the content of FIG. 11 can be colored in any color according to the content of the CLT, and the color range that can be displayed can be expanded as already described.

FIG. 7 shows a detailed embodiment of the present invention, in which parallel-series converter circuits 51 and 52 are respectively inserted between the memory 11 and the CLT 41 and between the CLT 41 and the DAC 21 in order to achieve a higher output speed. According to this embodiment, the speed of the output signal can be increased in the form of a bundling of parallel signals with the aid of the parallel-series converter circuits. This configuration is used in a suitable manner when the number of pixels to be displayed increases or when the number of display times (the number of sampling times) per unit time increases, so that a fluctuation in the image surface would be generated. Incidentally, as for the memory structures described in Figs. 6 and 7 above, it is possible to achieve a memory structure with high integration by using a single transistor memory as the memory 11 as shown in Fig. 11 and a memory structure with high To generate speed by using an SRAM shown in FIG. 10 or an ECL SRAM used in the aforementioned Bip Tr as CLT 41 .

FIG. 8 shows a detailed embodiment of the present invention, in which an analog / digital converter circuit ADC 22 is added to the input section of the embodiment shown in FIG. 5. The analog signal fed via the input connection 104 is converted into a digital signal by the ADC 22 and fed to the input logic circuit 32 .

According to this configuration, it is possible to simultaneously store analog signals, such as a television video signal, which are input from 104 into the memory 11 , in addition to the digital display signals which are input via 101 , and to output the output signal of the computer or the like. and simultaneously display the television video signal on the same display surface. The signals between 101 and 104 can be calculated by the input logic circuit 32 , the signals being able to be represented in a mutual superimposition. Furthermore, according to this embodiment of the present invention, the television signal or the like is converted from 104 into a digital signal and stored in the memory 11 . This signal can be output at a deflection frequency which is different from the input frequency, which represents a so-called "image raster converter" (scan converter). This makes it possible to use this configuration as a specification converter between video devices which have mutually different specifications.

In this embodiment, the output signal of a reference voltage / current generator circuit 23 is used together as a reference voltage or reference current as the basis for the operation of the ADC 22 and DAC 21 . As a result, the chip input / output characteristics of the analog signals can be exactly matched, such as in the form of an adjustment to a 0 value of a scale division, a maximum value of a scale division or the adjustment of the DC level of 22 and 21 to an equal value. The voltage may be used as a basis for operation in conjunction with the voltage generated by the circuit 22 described above, or may be generated based on this voltage if a so-called "on-chip voltage limiting system" is used, which, as described in US Patent No. 4 4 82 985, has a converter for reducing the voltage of a current source within the chip and operates part or all of the circuit with this reduced voltage in order to reduce energy consumption or to protect those parts which are miniaturized and have a low breakdown voltage system. Accordingly, as a result of the operating voltage of the chip, when the analog input signal is converted into a digital signal by DAC, then again converted into an analog signal and then output, the signal level of the input / output signals can always be kept at a constant level, thereby a Operation with high alignment can be achieved.

In this embodiment, the signal fed in via 104 can consist of signals which have been separated into the three primary colors in advance for a color display, or of undivided signals. If the signal is not yet separated, a circuit for separating the signal in accordance with the format of the memory data of the memory 11 can be arranged within the chip. Although this embodiment describes the case where an ADC is added to the embodiment shown in FIG. 5, it is also possible to add an ADC to other embodiments of the invention as well.

FIG. 9 shows a circuit which concretizes the DAC 21 of the embodiment shown in FIG. 5. As shown in FIG. 9, three DACs for the three primary colors red, green and blue, that is to say the DACs R, G and B for a color display, are assigned as DAC 21 and provide modulation signals 102 R, 102 G and 102 B of the three primary colors Down on the outside. These output signals are synthesized on the screen and different colors are displayed on the basis of the principle of the so-called "additive mixture color stimuli". Although the three primary colors for the color display in the description set forth above are red, green and blue, they change with the color generation method of the display device and therefore are not particularly limited. For example, a color generation method based on the principle of so-called "subtractive mixed color stimuli", which uses the colors yellow, cyan (cyan) and magenta (magenta) as the three primary colors, is sometimes used in a color printer. If this embodiment of the present invention is applied to such a printer, the DACs can be designed to correspond to these three primary colors.

As described above, according to the present invention, it is possible to provide a semiconductor device which is equipped with a large capacity memory and a DAC, but a memory with an even larger memory capacity may be necessary for various applications. In such a case, various modifications of the invention can be made. In FIG. 9, for example, the DAC can only be prepared for a single color, all memory locations being used for storing the data of this single color, so that three of these chips are then used in parallel with one another to generate the three primary colors. According to this arrangement, the storage capacity per color can be increased three times. Furthermore, it is possible to arrange a switching element within the chip, the chip having DACs for the three colors in the same way as in FIG. 9 and using them as such when the storage capacity can be small, and the switching element operating the DACs for two colors, however, then ended and the DAC continues to operate for only a single color, as a result of which a greater storage capacity can be achieved by using the memory 11 as a memory for only a single color and when using the switching element for the three chips as described above. According to this method, it is possible to cope with a situation in which the necessary storage capacity has to be small and large. In FIG. 9, it is also possible to attach a connection in advance for expanding the storage capacity of the memory 11 and to connect an expansion memory to this connection from the outside. The various methods described above can also be applied to a case where the DAC is configured as shown in FIG. 8.

As already described above, a semiconductor device with a large storage capacity and an analog circuit mounted on the same chip can be created by using a MOS memory. Various types of memory cells, such as those shown in Figs. 10 to 12, can be used as memory cells for building this MOS memory. FIG. 10 shows a static memory cell of the flip / flop type with four MOS transistors and two resistors, with FIGS . 11 and 12 each showing a dynamic memory cell. FIG. 11 shows a 1-transistor memory cell with a MOS transistor and with a capacitive resistor (capacitor), and FIG. 12 shows a 3-transistor memory cell with three MOS transistors. The cell shown in FIG. 10 can be operated with low noise and is particularly suitable when low noise is required. Since the resistors are used as load resistors of the flip / flop circuit and since these can be formed from multiple poly-Si layers or the like laminated onto the MOS transistors, this memory cell is distinguished in that its occupancy area is smaller than that Memory cells that use p-channel MOS transistors instead of the resistors. Since the number of components is small, the cell shown in Fig. 11 has a high integration density and a low energy consumption. As a result, this cell is particularly suitable when high-capacity memory is required. In the cell shown in Fig. 12, the current of Q _A is controlled by the information charge stored in the capacitive resistance of the gate of Q _A , and a large signal is output to the data read line D _R. As a result, this cell is suitable for operation with a high S / N ratio, particularly when operation with a higher S / N ratio is required.

FIG. 13 shows a circuit which concretizes the circuit arrangement of the embodiment shown in FIG. 3. The memory cell arrangement 12 of the memory 10 consists of individual transistor memory cells MCI which are suitable for achieving a high integration circuit. In order to achieve an operation with a high S / N ratio with low noise, the data line pairs D, are arranged parallel to one another and the memory cells are arranged at each intersection with the word lines W. In other words, this circuit uses a so-called "folded bit line structure". A peripheral circuit 13 with a sense amplifier SA for amplifying a small signal originating from the memory cell comprises a BiCMOS circuit, which in turn contains a combination of Bip Tr and CMOS (complementary MOS). The CMOS circuit, which has a low power consumption and a small circuit area, is used when a high integration density and a low power consumption are necessary, such as in the case of the SA or when a small load capacity is being driven. The Bip Tr circuit or the Bip Tr circuit combined with CMOS is used when driving a high load capacity or when it is necessary to amplify a weak small signal at high speed and at high sensitivity level. In addition to the circuit described above, the technique published in Japanese Patent Laid-Open Nos. 142594/1986 and 170992/1986 can be applied as such.

The circuits 20 and 30 are constructed in the same way with BiCMOS. For example, in the circuit 20 of the ADC and DAC, which have to process a high-speed small signal, are formed by the Bip Tr circuit, while the analog switch circuit or the like is formed by the CMOS circuit with less offset (with less off-set). In this way, the ADC and DAC have a high-speed operation, and high accuracy can be achieved. If the known Bip Tr bandgap generator is used for the reference voltage / current generating circuit shown in Fig. 8, a highly stable reference voltage / current can be obtained. In addition, if CLT 41 and parallel-series converter circuits 51, 52 , as shown in FIG. 7, are built using Bip Trs, they can operate at high speed. In the logic circuit 30 , too, a high consumer and high integration density can be achieved through the optional use of the CMOS and Bip Tr circuits or their combination in the same manner as described above.

As described above, it is possible to use a semiconductor device to create which in one piece a highly capacitive Storage with a high operating speed and low energy consumption and an analog circuit with a high operating speed and high accuracy includes. Although in the description given above BiCMOS circuit is used differently than the memory cells it is possible to use only the CMOS circuit, especially when low energy consumption or low manufacturing costs are required. Corresponding of the present invention described above can be one high-capacity memory and an analog circuit on the same be attached with chip so that the number of Wiring between the two and the wiring length can be lowered. As a result, this can occur in the Wiring noise can be minimized. If Memory cells of the single transistor type are used, However, the case may occur that a transient current (transient current) through the power supply circuit to Time of loading / unloading of the data lines flows and this current turns to the analog circuit position as smoking. The following are some Examples of a decrease in energy supply management described noise.

Fig. 14 shows one of these examples. In the drawing, reference numeral 300 represents a sheath and 311 and 312 pins on the sheath, which are used for the power supply as the contact pins that will appear later. Reference numeral 301 represents a cavity for the semiconductor chip; 321 and 322 are component lines, 331 to 333 are connecting wires for connecting the bond pads 111 and 112 on the semiconductor chip and the component lines, which are essentially made of Al or the like; 111 and 112 are bond pads for the power supply including the grounding of the memory 11 and the analog circuit 123; 121 and 123 are power supply lines on the chip.

In accordance with this configuration, energy is supplied to the memory and the analog circuit via separate pins, connecting wires, separate bond pads and energy supply lines. As a result, there is no noise superposition between the circuits. Sometimes, however, it is possible to use the connecting lines from the component contact pins to the bonding pads, as shown by the dashed line 33 in the drawing, together and to separate them from the connecting wire. Since the component contact pin and the connecting line have a relatively low inductance and resistance, the noise can also be reduced using this method.

Fig. 15 shows another embodiment of a low-noise power supply method. In this embodiment, the power supply of both circuits is not (?) Separated by means of power supply wiring on the semiconductor chip. Low noise can be expected with this circuit, but this embodiment further includes a decoupling circuit with a resistor R _w and a capacitive resistor C _w to remove the memory noise of the power supply in the power supply wiring of the analog circuit.

Because of this configuration, the noise which arises due to the operation of the memory in the power supply is removed by means of the decoupling circuit. As a result, the noise does not affect the analog circuit. The principle of the decoupling circuit used here can also be applied to the embodiment shown in FIG. 14. The resistance of the Al wiring can be used as the resistance of the decoupling circuit, and sometimes a more effective decoupling circuit can be obtained by using its self-inductance. The capacitance of the wiring can be used as a capacitive resistor, however, to improve the effect, a capacitive resistor in the form of an inversion layer of a MOS transistor, which ensures a high capacitance value in a small area, should be added. Furthermore, it is possible to form the capacitive resistor on the back of the chip and to use it as C _w , since the circuit is only arranged on part of the main surface of the semiconductor chip.

The configuration described above deals with the energy supply method of the memory and the analog circuit. If there is a large number of circuits as shown in Figs. 7 and 8, the low-noise power supply method described above can be used depending on the purpose. For example, different low noise power supply methods can be used independently of one another for a reference voltage / power generator circuit for which low noise is particularly necessary.

The above explanations explain the method for reducing the noise by the energy supply method. However, it is also possible to lower the noise taking into account the operation timing of the memory and the analog circuit by taking advantage of the fact that both are integrated with each other. For example, as shown in Fig. 16, a switch is arranged in series with R _w , which can be turned off, thereby interrupting the power supply lines at a time and period at which noise occurs due to the operation of the memory. According to this method, the power supply is cut off completely when noise occurs, so that the influences of the noise can be completely removed. Incidentally, the switch and the resistor can be provided by means of a MOS transistor when the ON resistance of the MOS transistor Q _{R is used} as the resistor R as shown in FIG. 17. In other words, Q is normally held in the ON position by a pulse ø _R, which performs the configuration / configuration of Q _R in accordance with the operation of the memory DAC or ADC, so that its ON resistance functions as R _w and transistor Q _{R is} turned off when noise occurs. Furthermore, the noise can be reduced in an equivalent manner by synchronizing the timing of the occurrence of the noise in FIG. 10 with the timing in which no problems appear, even if some noise enters through the power supply or the like. For example, the noise can be combined with the time period of the blanking operation horizontally or vertically by synchronizing the time period of loading / unloading operation of the data lines, in which the greatest noise in FIG. 10 occurs with the device in a color graphic display, with no critical problems do not occur when there is noise in the DAC of 20 . The configurations of FIGS. 14, 15, 16 and 17 can be combined accordingly with the configurations of FIGS. 2 to 9 and FIGS. 13, 18, 19, 21, 22 and 23.

Various configurations of the present invention have thus been described. Because in these embodiments the memory circuit, the digital circuit, the Analog circuit and the like. In the form of a mixture on the same Semiconductor chips are arranged, are different types Tests during the manufacture of semiconductor chips, the assessment of the approved and defective products after its completion and the guarantee of Quality become extremely complicated, so that sometimes Adequate tests are not performed can.  

Fig. 18 shows an embodiment which is suitable for solving these problems. This configuration is based on the configuration shown by way of example in FIG. 4. The symbols SW ₀₁- SW ₁₂ represent analog switches for switching both the digital and the analog input / output signals, reference numeral 225 representing a control signal. Although a plurality of control signals are generated according to the control of each switch, only a single signal is shown in the drawing for the sake of simplicity.

If the switches SW ₀₁ and SW ₁₁ are turned on while the switches SW ₀₂ and SW ₁₂ are off in this embodiment, a signal can be fed directly from the outside via the input terminal 101 , the switch SW ₀₁ and the wiring 221 into the memory , wherein the operating state of the memory 11 can be detected via the wiring 23 , the switch SW ₁₁ and the output 102 , so that the memory can be checked. On the other hand, if the switches SW ₀₁ and SW ₁₁ are off while the switches SW ₀₂ and SW ₁₂ are on, the operation of 21 can be checked directly from the outside through the input / output terminals 101, 102 . In this way, each circuit section can be easily checked. Incidentally, the circuits can normally be operated in exactly the same way as in the embodiment shown in Fig. 4 by turning on the switches SW ₀₁, SW ₁₁ and turning off the switches SW ₀₂, SW ₁₂. When performing the test, either a digital signal or an analog signal can be applied to each switch according to the goal of the test.

In this embodiment, although the signal 201 for connecting FIGS. 11 and 21 is the same as the embodiment shown in FIG. 4, it is of course possible to use a circuit structure in which this signal by means of an arrangement of a group of switches directly via an external contact pin fed in or delivered to an external contact pin. Although the above description deals with an example in which the switches are only used for test purposes or during the test time, it is of course also possible during a current operating state to use the switch and by using the same signal line as a function of the digital and analog signals of the intended application. Although this configuration takes the configuration shown in FIG. 4 as an example, the technical content of this configuration can of course also be applied as such to other structures.

The Fig. 19 (A) and 19 (B) show a specific example of an analog switch as described above. Fig. 19 (A) shows its circuit and (B) and its equivalent circuit. In the drawings, the symbols Q _N , Q _P and INV accordingly represent an N-channel MOST, a P-channel MOS and an inverter. Since the signal ø has a high potential, so that there is a high potential at the gate of Q _N and a low potential at the gate of Q _P , both Q _N and Q _{P are} switched on. The digital or analog signal can thus be transmitted at high speed from A to B or vice versa without loss of voltage. If the signal ø has a low potential, both Q _N and Q _P and thus the switch are switched off. Although the above is a circuit example using P- and N-channel MOSTs, it is possible to create the circuit by using P- or N-channel MOSTS alone. The configurations of FIGS. 18 and 19 can be combined accordingly with the configurations of FIGS. 1, 2, 3, 5, 6, 7, 8, 9, 13, 14, 15, 16, 17, 21, 22 and 23.

Although different configurations of the present Invention have been described, the semiconductor circuit with the large capacity memory, the digital circuit and the analog circuit, all arranged on the same chip are, achieve new functions through the components of the prior art can not be achieved.

The Fig. 20 (A) to (D) show an embodiment of the present invention for such an application. If the present invention is applied to a graphic display, such as. B. applied a computer terminal or the like., The embodiment of the invention makes it possible to change the number of bits as display data for both the number of pixels to be displayed and the contrast and thus a display with a high number of pixels (A), a display with high To achieve contrast (or color tint) (B) or a combination of (C), (D). In the drawing, reference numeral 500 represents a screen using a CRT, a liquid crystal or plasma. The black circle L represents a display pixel with a relatively low tint (or relatively low tint). For example, a display of 4 bits per pixel, ie 2⁴ tint / pixel is made. The white circle H represents a display pixel with a relatively high tint (contrast), this being generated, for example, with a display of 8 bits per pixel, ie 2⁸ tint / pixel.

Fig. 20 (A) shows an example of display with a high number of pixels are displayed in black over the entire image area with a relatively small circles L tint, but but the number of pixels is increased on the screen. Fig. 20 (B) shows an example of a high contrast display in which the number of pixels corresponds to half that in Fig. 20 (A), but each pixel by the white circles H with a relatively high tint, ie by 8 bits instead of 2 pixels is shown in Fig. 20 (A). Fig. 20 (C) shows an example of a combination of Fig. 20 (A) and FIG. 20 (B), in which the number of pixels in the area 501 is half as large as the number of pixels in the other face, however, a wedge display with high contrast is achieved. FIG. 20 (D) shows an example in which a high contrast display is achieved in area 502 in the same way as in FIG. 20 (C), but with the number of pixels in this area being the number (or Density) of the pixels in the other area.

According to each of the configurations described above, it is possible to achieve a wide variety of representations depending on the intended application. For example, it is possible to carry out a display with a high contrast of image data from a television or VTR and a display with a high number of pixels from a computer output on the same screen under the best display conditions for each of the two representations. Although L and H have been described as 4 bits / pixel and correspondingly 8 bits / pixel in the description above, a high-quality color display can of course also be achieved if one assumes, for example, 12 bits / pixel for L and 24 bits / pixel for H.

Fig. 21 shows a specific embodiment of the present invention for performing the display of Figs. 20 (A) to (C). The configuration is based on the configuration shown in FIG. 4. However, the present embodiment differs from the embodiment shown in FIG. 4 in that a logic AND circuit and a delay circuit 600 are added, a DAC with a number of bits required for high-contrast display being used as 21 . In the case of a display with a high number of pixels, the display data are only output over 231 and in the case of a display with high contrast both over 231 and 232 .

Fig. 21 (B) is a diagram which helps explain the operation of this embodiment. In this embodiment too, the display point L has 4 bits / pixel and the display point H 8 bits / pixel in the same way as in the embodiment described above. For purposes of illustration, the signals from 231 and 232 are represented by the binary numbers "0" and "1" and the signals from 233 to 235 in pulse form.

The 4-bit data for the display are output by the memory 11 in the time sequence t ₀- t ₇ via the line 201 . The time t ₀- t ₇ corresponds to each pixel in the transverse direction of the display with a high number of pixels in FIG. 20 on a 1: 1 basis, but the description given here relates to the case in which a display with a high number of pixels and a display with high contrast corresponding to the second line from the top in Fig. 20 (C).

As a result, t ₀, t ₁, t ₆ and t ₇ represent a display with a high number of pixels and t ₃ and t ₅ represent a display with high contrast (tinting). The signal from 201 is delayed during each time L by the delay circuit 600 , which is controlled by the signal 235 , and output to the line 230 (not shown in Fig. 21 (B)). In other words, the signal from 201 at time t ₀ is delivered to line 230 at time t ₁. The signals from 231 and 230 are subjected to a logical AND operation with the signals from 233 and 234 and are fed to the DAC 21 via 231 and 232 . As a result, the signal from 201 is at 231 as such when there is a pulse at 233 , which applies to the times t ₀, t ₁, t ₃, t ₅, t ₆ and t ₇. The signals from 201 at times t ₂ and t ₄ are at 232 when there is a pulse on line 234 , which is the case at times t ₃ and t ₅. As a result, only the 4-bit signal component of 231 , which represents the data display of L , is fed to the DAC 21 at times t darstellt, t ₁, t ₆, t ₇. On the other hand, the data at t ₃ and t ₅ and the data from 201 at t ₂, t ₃ and t ₄, t ₅ are combined accordingly and fed to the DAC as high-contrast display data H. At time t ₂ and t ₄, no display data is output and the number (or density) of the display pixels is, according to the area 501 in FIG. 20 (C), half of the pixels in other areas.

As described above, a high pixel display and a high contrast display can be easily controlled by the signals in 233 and 234 . In this way, according to the present invention, it is possible to realize the various displays from (A) to (C) shown in Fig. 20 by adding circuits.

FIG. 22 shows a specific embodiment of the present invention, which makes it possible to achieve a high-contrast display without reducing the number of pixels according to FIG. 20 (D). In this embodiment, a memory 11 H for storing the data for a high-contrast display is arranged separately from the memory 11 , the output of this memory 11 H via an AND gate in addition to the output of the memory 11 at a point in time of a display with high contrast DAC 21 is fed. According to this configuration, a display with high contrast can be carried out without reducing the number of pixels. The storage capacity of the memory 11 H can be suitably used in accordance with the bit number of the display for a "high" contrast, and in accordance with the size of the area should be performed for a high contrast display can be selected.

FIG. 23 shows a further embodiment of the present invention, which can increase the possible combinations of the displayable colors by using a color reference panel CLT 41 of the type shown in FIG. 6 if the display is not implemented as a high-contrast display. Here, the combination of those colors that can be selected using the CLT is equated to the contrast (or color tint) at the time of the high-contrast display. In this way, the DAC 21 , which was originally designed to use a CLT, can also be used as such for a high-contrast display without any special changes. In other words, when a CLT is used, the DAC 21 still has the capacity for a high contrast display.

In this embodiment of the present invention, the outputs of 11 and 11 H as such are fed to the DAC 21 via a logic circuit at the time of the high-contrast display at 231 and correspondingly 232 . On the other hand, at different times at the above time, the CLT 41 is referred to via the output of the memory 11 , the outputs 240, 241 of the CLT 41 being supplied to the DAC at 231 and 232 via a logic circuit. As a result, the possibility of combining the displayable colors by means of CLT can be expanded at times other than the times of high-contrast display. As such, the method of using this CLT can also be applied to the configuration shown in FIG .

Although the configurations of the various display functions are shown in FIGS. 20 to 23, these configurations can of course also be applied to the other configurations of the present invention which have already been described.

Although the present invention is by reference to some preferred embodiments has been described, it is especially not limited to this. For example, the present invention, although the scope described so far of the present invention mainly one Color graphic display of a computer terminal or the like. in particular not limited to this, but can be applied to all cases where a memory with large capacity and an analog circuit for a digital Amount of data and their storage in a memory or in an image memory equipped with DAC, e.g. B. in one Color printer, a laser beam printer, a high-precision digital TV, VTR etc., or a measuring instrument, one Control device or the like. Is essential.

According to the present invention, it is possible to have a memory with large capacity and an analog circuit on the same Arrange chip, whereby a semiconductor device, which has a low-noise memory with high capacity as well high speed and an additional analog circuit includes, as well as a new functional component can be generated, which is such a semiconductor device used.

It is understood by those skilled in the art that the foregoing Description is only a preferred embodiment of the present invention and various Changes and modifications can be made without the principle and scope of the invention leave.

Claims (45)

1. Semiconductor component, characterized by

• - a semiconductor chip;
• a memory circuit for storing data, which is provided on the semiconductor chip;
• - An analog circuit for processing the data of the memory circuit, which is also provided on the semiconductor chip; and
• - Provided on the semiconductor chip conductor for the electrical connection of the memory circuit and analog circuit;
• - The memory circuit includes a plurality of memory cells, and each of these memory cells comprises at least one field effect transistor.

2. The semiconductor component according to claim 1, characterized in that the analog circuit is a digital / analog converter circuit having.   3. Semiconductor component according to claim 2, characterized in that the memory circuit a first device for a Replace a defective memory cell with one includes redundant memory cell. 4. Semiconductor component according to claim 3, characterized in that the analog circuit another device for change the characteristics of the analog circuit. 5. The semiconductor device according to claim 4, characterized in that these first and second devices from a fusible element consist. 6. The semiconductor device according to claim 2, still characterized by a switch arrangement to enable a in accordance with an external test signal Access to the memory circuit and the analog circuit. 7. The semiconductor component according to claim 2, still characterized by a device for generating image data for a high contrast due to the temporal processing of the  Memory circuit or a spatial part of this Storage circuit output image data. 8. The semiconductor device according to claim 1, characterized in that the analog circuit is an analog / digital converter circuit and comprises a digital / analog converter circuit. 9. The semiconductor device according to claim 2, characterized in that the memory circuit is a first facility for healing (remedying) the memory circuit, and the analog circuit another device for controlling the characteristic of the analog circuit, the first and second device are constructed in the same way. 10. The semiconductor component according to claim 2, marked by a logic circuit provided on the semiconductor chip to control the memory and analog circuit. 11. The semiconductor component according to claim 10, characterized in that the logic circuit has a microcomputer.   12. The semiconductor element according to claim 2, still characterized by an input logic circuit arranged on the semiconductor chip to control the fed into the memory circuit Input data. 13. The semiconductor component according to claim 2, characterized in that the memory circuit of a CMOS circuit and a includes bipolar circuit. 14. The semiconductor component according to claim 2, characterized in that the analog circuit is a CMOS circuit and a includes bipolar circuit. 15. The semiconductor component according to claim 2, characterized in that the logic circuit is a CMOS circuit and a bipolar Circuit includes. 16. The semiconductor device according to claim 2, further characterized by

• - A first power supply connection for the memory circuit; such as
• - A second power supply connection for the analog circuit; the first and second power supply connections being separate from one another.

17. The semiconductor device according to claim 2, further characterized by

• - A first power supply connection for the memory circuit; and
• - A second power supply connection for the analog circuit;
• - A decoupling circuit for removing noise from the first power supply connection from the second power supply connection.

18. The semiconductor component as claimed in claim 17, characterized in that the decoupling circuit has one resistor and one Contains capacitor. 19. The semiconductor component as claimed in claim 17, characterized in that the decoupling circuit is a switch, a Has resistance and a capacitor. 20. The semiconductor component according to claim 17, characterized in that the decoupling circuit a switching transistor and comprises a capacitor.   21. The semiconductor component according to claim 2, wherein the memory circuit is characterized by

• a plurality of memory cells, each memory cell having a flip / flop circuit consisting of driver MOS transistors, load resistors and transfer MOS transistors;
• - wherein a source or drain electrode of one of the driver MOS transistors is electrically connected to one of the load resistors, to the source or drain electrode of one of the transfer MOS transistors and to a gate electrode of another driver MOS transistor;
• - wherein a source or drain electrode of the other driver MOS transistor is electrically connected to another of the resistors, to the source or drain electrode of another of the transfer MOS transistors and to the gate electrode of the one driver transistor;
• - a first voltage supply electrode;
• - wherein a drain or source electrode of the two driver MOS transistors are electrically connected to this first voltage supply electrode;
• a plurality of word lines means for selecting a memory cell, each word line being electrically connected to the gate electrode of each transmission MOS transistor;
• a plurality of data line pairs for selecting a memory cell, each data line pair being electrically connected to a source or drain electrode of the transfer MOS transistors and one of the data line pairs having "HIGH" level data and the other of the data line pairs having "LOW" level data;
• - A plurality of voltage supply electrodes for supplying energy to the memory cells, each voltage supply electrode being electrically connected to the load resistors.

22. The semiconductor machine according to claim 2, wherein the memory circuit is characterized by

• a plurality of memory cells, each memory cell having a MOS transistor and a capacitor,
• - wherein a source or drain electrode of the MOS transistor is electrically connected to one of the electrodes of the capacitor;
• a plurality of word lines for selecting the memory cells, each word line being electrically connected to the gate electrode of the MOS transistor;
• a plurality of data line pairs for the selection of the memory cells, each of these data powers being electrically connected to the drain or source electrode of the MOS transistor and one of the data line pairs having "HIGH" level data and the other of the data line pairs having "low" level data during normal operation .

23. Semiconductor component, characterized by

• - a semiconductor chip;
• - A memory circuit, which consists of
  • a plurality of memory cells, each memory cell having a field effect transistor and a capacitor;
  • - wherein a source or drain electrode of the field effect transistor is electrically connected to the one electrode of the capacitor;
  • a plurality of word lines for selecting the memory cells, each word line being electrically connected to the gate electrode of the field effect transistor;
  • a plurality of data line pairs for selecting the memory cells, each data line pair being connected to a drain or source electrode of the field effect transistor and having one data line pair "HIGH" level data and the other data line pair "LOW" level data in normal operation;
• an analog circuit for processing the data of the memory circuit;
• - The memory circuit and analog circuit are arranged on the same semiconductor chip; and
• - The analog circuit comprises a digital / analog converter.

24. The semiconductor component as claimed in claim 23, characterized in that the memory circuit is a first facility for healing (remedying) the memory circuit and the analog circuit a second device for controlling the characteristic of the analog circuit, the first and second device are constructed in the same way. 25. The semiconductor component according to claim 23, marked by a logic circuit for controlling the memory circuit and the analog circuit, the logic circuit on the same semiconductor chip is arranged. 26. The semiconductor component as claimed in claim 25, characterized in that the logic circuit comprises a microcomputer. 27. The semiconductor component as claimed in claim 23, marked by an input logic circuit for controlling the input data, which are fed into the memory circuit, the input logic circuit on the semiconductor chip is arranged.   28. The semiconductor component as claimed in claim 23, characterized in that the memory circuit is a CMOS circuit and a includes bipolar circuit. 29. The semiconductor component as claimed in claim 23, characterized in that the analog circuit is a CMOS circuit and a includes bipolar circuit. 30. The semiconductor component according to claim 23, characterized in that the logic circuit is a CMOS circuit and a bipolar Circuit includes. 31. A semiconductor device according to claim 23, characterized by

• - A first power supply connection for the memory circuit; and
• - A second power supply connection for the analog circuit;
• - The first and second power supply connection are separate from each other.

32. Semiconductor component according to claim 23, characterized by

• - A first power supply connection for the memory circuit; and
• - A second power supply connection for the analog circuit;
• - A decoupling circuit for removing the noise of the first power supply connection from the second power supply connection.

33. Semiconductor component according to claim 23, characterized in that the decoupling circuit has one resistor and one Has capacitor. 34. Semiconductor component according to claim 23, characterized in that the decoupling circuit is a switch, a Has resistance and a capacitor. 35. Semiconductor component according to claim 32, characterized in that the decoupling circuit a switching transistor and has a capacitor.   36. Semiconductor component characterized by

• - a semiconductor chip;
• a first circuit, a second circuit and a circuit arrangement for enabling direct access in accordance with a test signal from the outside of the semiconductor chip to the first and the second circuit, the first circuit, the second circuit and the switch arrangement being arranged on the same semiconductor chip .

37. Semiconductor component according to claim 36, characterized in that the first circuit is a memory circuit, which has a field effect transistor. 38. The semiconductor component as claimed in claim 37, characterized in that the switch assembly is a CMOS switch circuit includes. 39. Semiconductor component according to claim 37, characterized in that the memory cell of the memory circuit is dynamic Memory cell is.   40. Semiconductor component according to claim 39, characterized in that the dynamic memory cell is a single transistor memory cell is which consists of a MOS transistor and a capacitor. 41. The semiconductor component as claimed in claim 37, still characterized by a device for generating image data for a high contrast due to temporal processing of the image data, that in a time sequence from the memory circuit or a spatial part of this memory circuit be issued. 42. Semiconductor component characterized by a memory circuit for storing digital Image data, a converter unit for the output of an analog Video signal after receiving the digital image data and a device for generating image data for a high contrast due to the temporal processing of the Image data in a time sequence from the memory circuit or a spatial part of this memory circuit will be spent.   43. The semiconductor component as claimed in claim 42, characterized in that the device for generating the image data for one high contrast a delay circuit for a readout of in time sequences from the memory circuit read image data and to delay this image data by one clock, as well as a logic gate circuit for the transmission of the image data and the output signal the delay circuit to the input of the converter unit in accordance with a control signal. 44. The semiconductor component according to claim 42, characterized in that the memory circuit for a first image memory Storage of image data of a high number of pixels and a second image memory for storing Has image data for high contrast, the High contrast image data resulting from the can be read out to the input of the second image memory Converter unit via the logic gate circuit under the Control can be transmitted by control signal. 45. The semiconductor component according to claim 43 marked by a switch arrangement to enable a depending of a test signal direct access to the  Transducer unit from the outside of the semiconductor component.