JPH025300A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To surely perform the function tests of both a digital circuit and an analog circuit in a short period of time by using a changeover switch which can realize the direct accesses to both circuits. CONSTITUTION:The signal can be directly inputted to a picture memory GRAM from outside via an input terminal 101, a switch SW01 and a wiring 221 after switches SW01 and SW11 are turned on with the switches SW02 and SW12 turned off respectively. Thus the direct access is possible to the memory GRAM and this memory can be tested in the same way as that of a single unit memory device. While the working of a D/A converting circuit DAC serving as an analog circuit can be directly tested from outside by means of the terminal 101 and an output terminal 101 after the switches SW01 and SW11 are turned off with the switches SW02 and SW12 turned on respectively.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and is applicable to, for example, a semiconductor integrated circuit device equipped with an image memory circuit and a D/A conversion circuit that receives a read signal from the image memory circuit. It is about effective techniques.

[Conventional technology]

Conventionally, regarding devices in which a memory circuit and an analog circuit are mounted on the same semiconductor chip, the 107th to 108th technical papers of the 1987 VLS 1-Circuit Symposium (1987 Symposium VLS
I C1rcuits Digest of Tech
nical Paperspp 107-108) This paper uses an ECL (emitter
It is equipped with two static RAMs (random access memories) of the coupled logic type and one D/A (digital/analog) conversion circuit with an 8-bit resolution. A semiconductor integrated circuit device has been disclosed which has a function of converting a digital signal in ) into an analog signal of 256 gray scales and outputting it to the outside.

This device is disclosed for use in generating color modulation signals for color bitmap display in computer graphics display terminals, etc. By using three of this device corresponding to the primary colors red, green, and blue in the display, It becomes possible to display a color image. The ECL type SRAM is used as a color lookup table (CLT), which is described in detail in Nikkei Electronics, May 20, 1985 issue, pages 257 to 281, and can be displayed.
Any 21 of the 214 (21/eNIP X ffcMIP) colors! (24/eNIF +1 IC
MIP) can display color images with combinations of colors. The colors of the combination are dictated by data stored in SRAM within each chip (CHIP).

In addition to being a high-speed memory using bipolar transistors, the above-mentioned ECL type SRAM is designed to double the speed by alternately operating two SRAMs in multiplex mode. Further, the D/A conversion circuit is also designed to have high speed and low noise using bipolar transistors suitable for high speed. This makes it possible to generate high-speed, low-noise color modulation signals necessary for color bitmap display.

[Problem to be solved by the invention]

The above-mentioned conventional technology has insufficient consideration for reducing the occupied area and lowering power consumption, and has had problems in promoting higher integration. In the bitmap display method, a large-capacity pixel memory that stores color modulation image data for each pixel to be displayed;
It is necessary to prepare a so-called frame memory 0 For example, the 2′ mentioned above! In order to display 500 x 500 pixels in color, it is necessary to prepare a frame memory of 12 x 500 x 500 = 3 x 10" bits. It is desirable that this frame memory and the above-mentioned D/A conversion circuit be on the same chip. However, , ECL-type SRAMs made of bipolar transistors used in the above-mentioned conventional technology occupy a large area and consume a large amount of power, so it is impossible to increase the storage capacity to such a large extent. Therefore, the frame memory must be provided as a separate chip, which increases the number of parts and increases the scale of the entire display device. Problems such as an increase in the number of wiring lines and a decrease in signal chain quality also occur.Additionally, the increase in the number of input/output bins and noise in semiconductor integrated circuit devices also causes problems in that it becomes difficult to increase the speed. It is difficult to transmit high-speed signals because the wiring for connecting circuit devices has large parasitic capacitance.For this reason, a large number of low-speed signals are transmitted in parallel, and these are connected in parallel and serially within a semiconductor integrated circuit. A method of multiplexing into one high-speed signal using conversion technology is used, but the number of input/output pins for transmitting low-speed signals increases, and the potentials or currents of these multiple low-speed signals are When changing, there are problems such as generating a large amount of noise.

An object of the present invention is to provide a semiconductor integrated circuit device in which a large-capacity memory and an analog circuit are mounted on the same chip, and in which testing thereof is carried out in a single device.

Another object of the present invention is to provide a semiconductor integrated circuit device that realizes a new display function by using an image memory and a D/A conversion circuit formed on the same chip.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a semiconductor integrated circuit device including a digital circuit and an analog circuit is provided with a changeover switch circuit that enables direct access to the memory circuit and the analog circuit from the outside in response to a test mode signal. Further, by using a memory circuit built in the semiconductor integrated circuit device for storing digital image data and a D/A conversion circuit for receiving the image data and outputting an analog video signal, the data is output from the memory in a time-series manner. Image data for high gradation is generated by temporal processing of image data or spatial division of the memory circuit, and high gradation display is selectively performed using this image data.

[For production]

According to the above-mentioned means, the digital circuit and the analog circuit can be directly accessed by controlling the changeover switch, so that test time can be shortened and high reliability can be obtained. Furthermore, the number of bits of data from the image memory as a digital circuit can be expanded by the above-mentioned temporal or spatial processing, so that selective high-gradation display becomes possible.

〔Example〕

FIG. 8 shows a block diagram of an embodiment of the basic concept to facilitate understanding of a semiconductor integrated circuit device to which the present invention is applied.

The semiconductor integrated circuit device LSI includes a memory circuit RAM and an analog circuit AC. The above memory circuit RAM
is composed of a MOSFET (insulated gate field effect transistor). The analog circuit AC is composed of analog circuits such as a D/A conversion circuit and an operational amplifier circuit. Here, the structure of the memory RAM is a so-called random access memory (Ra
Access Memory) or a format that serially reads and writes data like a shift register, or even an IEE journal that combines these two functions. Of Solid-State Circuits Volume 5C-19, No. 6, December 1984 issue,
999 pages/1007 pages (IEEE Journal
of 5olid-3tete C1rcuits V
ol, 5C-19, Na6. Dec, 1984. p
p. 999-1007),
So-called dual boat memory (Dual Port memory)
tMemory).

According to this embodiment, since the memory is constructed of memory cells using MOSFETs that occupy a small area and consume less power and are suitable for high integration, a large-capacity memory RAM and an analog circuit AC can be integrated on the same chip. Easy to install. Also,
In this embodiment, the memory circuit RAM and the analog circuit AC are connected by a wiring 201 on the same chip. Therefore, the wiring length of this wiring 201 is short (and the parasitic capacitance in the wiring 201 is extremely small, so signals can be transmitted at high speed. Also, since the signal transmission is high-speed, the number of wirings can be reduced, and the potential or current The noise caused by simultaneous changes in the signals can be reduced.Even if a method of transmitting many signals in parallel and increasing the speed by parallel-to-serial conversion is adopted to further increase the speed, the wiring length would be extremely long. Because of its short length, the noise when signal potential or current changes is negligibly small (high-speed, low-noise, large-capacity memory circuit RA
It is possible to realize a semiconductor integrated circuit device LSI in which M and analog circuits AC are mixed.

FIG. 9 shows a schematic diagram of an embodiment of a semiconductor integrated circuit device that takes advantage of integrating a memory circuit consisting of a MOS FET and an analog circuit into one chip.

In this embodiment, the memory circuit RAM includes a fuse F1 for relieving defects, and the analog circuit AC includes a fuse F2 for trimming (fine adjustment) of various analog characteristics. In this embodiment, both fuses F
The feature is that 1 and F2 are of the same system. In order to increase the manufacturing yield of the large capacity memory circuit RAM, spare memory cells are prepared in advance, and if a defective memory cell is found as a result of a test, it is replaced with a spare memory cell and a good product is made. A so-called defect relief technique is adopted. The defect relief fuse F1 functions as a switch for replacing the defective memory cell with the spare memory cell.

In the figure, one fuse F1 is exemplarily shown as a representative. In addition, in the analog circuit AC, the amplification factor of the operational amplifier, the A/D (analog/digital) conversion circuit,
It may be necessary to trim (adjust) the reference voltage, current values, etc. used in the D/A conversion circuit based on the results of a performance test to improve accuracy. Fuse F2 is used as a switch for this trimming.

In the figure, one fuse F2 is exemplarily shown as a representative.

Generally, fuses formed in semiconductor integrated circuits are formed of aluminum wiring, polysilicon wiring, or the like, and are blown by irradiation with laser light or by flowing a large current. By standardizing the materials, forming method, cutting method, etc. of this fuse for the fuse F1 of the memory circuit RAM and the fuse F2 of the analog circuit AC, manufacturing processes, testing processes, cutting processes, and the equipment used therein can be simplified. Since they can be made the same, each process can be made more efficient. In this example, for trimming the analog circuit AC, the fuse is used as a resistor itself in the circuit, and the resistance value is changed by scraping off a part of it with a laser beam, or a polysilicon fuse is used. It is also possible to adjust the resistance value by heating this with laser light and changing the impurity concentration distribution.

FIG. 10 shows a block diagram of a modification of the embodiment of FIG. 8. In FIG.

In this embodiment, the logic circuit LOG is newly added 0
According to this embodiment, the logic circuit LOG enables various logical operation processes, and the results are used in the memory circuit RAM.
It is also possible to control the analog circuit AC. Here, the logic circuit LOG is assumed to include not only a simple logic circuit but also a microcomputer, etc., so that the processing capacity can be further increased.

FIG. 11 shows a block diagram of an embodiment of a semiconductor integrated circuit device for color graph ink display.

The image memory GRAM stores image data corresponding to each picture element (pixel) for display, and is configured with a MOS memory. Image data for each picture element is input from the input terminal 1. The configuration of the image memory GRAM allows input and output to be performed simultaneously in parallel, so stored data can be rewritten while outputting display data. The D/A conversion circuit (DAC) as an analog circuit, which is preferably the above-mentioned Dürbor boat type memory, converts the digital output signal 201 from the image memory GRAM into an analog signal and outputs it as a color modulation signal for each picture element. Output to the output terminal 102.

The control circuit C0NT controls the image memory ORAM and D/
This is a control logic circuit that controls the operation of the A conversion circuit DAC, and a control signal is input from the input terminal 103.

According to this embodiment, an image memory GRAM for high-speed, low-noise color graph ink display and a D/A conversion circuit DAC are provided.
It is possible to create an image memory with a DAC that integrates the image into a single chip.

FIG. 12 shows a block diagram of a modification of the embodiment of FIG. 11.

In this embodiment, an input logic circuit AU is added to the input section of the image memory GRAM. This input logic circuit AU is
Performs logical operation processing on input data.

According to this embodiment, the input logic circuit AU can be used to perform various calculation processes such as generating arbitrary figures such as circles and squares. Further, by providing the input logic circuit AU and the control circuit C0NT with functions similar to those of a microcomputer, more advanced processing can be realized, and even higher performance can be achieved.

FIG. 13 shows a block diagram of a modification of the embodiment of FIG. 12.

In this embodiment, the coloring table CLT mentioned above is added. This coloring table CLT is provided between the output of the image memory GRAM and the D/A conversion circuit DAC. According to this embodiment, the contents of the coloring table CLT are added to the contents of the image memory GRAM as described above. You can expand the range of colors that can be displayed by adding colors according to your preference.

FIG. 14 shows a block diagram of a modification of the embodiment of FIG. 13.

In this embodiment, for high-speed operation, the image memory GR
Parallel-serial conversion circuits PSCI and P are connected between AM and color table CLT, and between color table CLT and D/A conversion circuit DAC, respectively.
According to this embodiment, the parallel-serial change circuits PSC1 and PSC2 can speed up the output signal by multiplexing the parallel signals, increasing the number of display pixels or increasing the display speed per unit time. This is suitable for increasing the number of scans (number of scans) to create flicker-free images. Regarding the memory configuration of the embodiments shown in FIGS. 13 and 14, the large storage capacity image memory GRAM uses a known 1MO8 type dynamic memory cell consisting of an address selection MO3FET and a storage capacitor. Colored table C that uses high integration and high-speed operation
The LT includes a latch-type drive (memory') MOSFET whose gate and drain are cross-connected, a polysilicon high resistance provided at its drain, and the drive MOS described above.
A MOS static type memory cell consisting of a transmission gate (transmission gate) MOSFET provided between the drain of an FET and a pair of complementary data lines.A structure for increasing speed using an ECL type static memory cell using a bipolar type transistor is used. Conceivable.

FIG. 15 shows a block diagram of a modification of the embodiment of FIG. 12.

In this embodiment, A/
A D conversion circuit ADC is added. That is, input terminal 1
The analog signal input from 04 is sent to the A/D conversion circuit A.
It is converted into a digital signal 213 by DC and input to the input logic circuit AU.

According to this embodiment, in addition to a digital display signal input from the input terminal 101, an analog display signal such as a television video signal input from the input terminal 104 is simultaneously stored in the image memory GRAM. This makes it possible to simultaneously display the output of a computer and a television video signal on the same display screen. In addition, the input logic circuit AU also controls the input terminals 101 and 1.
It is possible to carry out arithmetic processing between the 04 signals and display them in a superimposed manner. Furthermore, according to this embodiment, a so-called scan converter converts a portion of the television video signal or the like at the input terminal 104 into a digital signal, stores this in the image memory GRAM, and outputs the signal at a sweep frequency different from that of the input. It can also be used as a specification conversion device between video devices with different specifications.

In this embodiment, the reference voltage or reference current that serves as the reference for the operation of the A/D conversion circuit ADC1D/A conversion circuit DAC is the output signal 21 of the reference voltage/current generation circuit REF.
4 are shared. As a result, it is possible to make the chip input/output characteristics of analog signals exactly the same, such as adjusting the zero scale level, full scale level, or DC level of the A/D conversion circuit ADC and the D/A conversion circuit DAC to the same level. become. In addition, for the purpose of reducing power consumption or protecting elements that have been miniaturized and have low withstand voltage,
Patent Application No. 56-57143, Patent Application No. 168698-1982
The device employs a so-called on-chip voltage limiter method, which has a means to lower the power supply voltage inside the chip and operates some or all of the circuits within the chip using this lowered voltage, as disclosed in In this case, it is also possible to use a common voltage as the reference voltage for operation with the voltage generated by the above-mentioned reference voltage/current generating circuit REF, or to generate it based on this voltage. This standardizes the operating voltage of the entire chip, allowing highly consistent operation of the entire chip.

In this embodiment, the signal input from the input terminal 104 may be a signal that has been separated in advance into three primary colors for color display, or may be a signal that is not separated. If the signal is not separated, a circuit for separating this signal according to the format of the data stored in the image memory GRAM may be provided inside the chip LSI. In this embodiment, an A/D conversion circuit ADC is added to the embodiment shown in FIG. Although an example in which an A/D conversion circuit is added has been described, it is possible to add an A/D conversion circuit in the same way in other embodiments.

FIG. 16 shows a block diagram embodying the D/A conversion circuit DAC in the embodiment of FIG. 12.

In this embodiment, the D/A conversion circuit DAC includes R, G%B D/A conversion circuits for each of red, green, and blue, which are the three primary colors of color display, and externally receives the modulation signal 102 of the three primary colors.
On the 0 display screen that outputs R, 102G, and 102B, these are combined and various colors are displayed according to the principle of so-called additive color mixing. Therefore, according to this embodiment, 1
The chip semiconductor integrated circuit device LSI enables the display of color images. Note that the three primary colors of color display are explained above as red, green, and blue, but this varies depending on the coloring method of the display device and is not limited to this.For example, in a color printer device, etc. Yo, yellow.
A subtractive color mixing method using cyan and magellan as the three primary colors is sometimes used, but when applying this embodiment to such a device, the D/A conversion circuit DAC must be configured to correspond to each primary color. Just use it.

As described above, according to the present invention, a large-capacity image memo IJGR
A semiconductor integrated circuit device LSI with an AM and D/A conversion circuit DAC can be realized, but depending on the case, a larger capacity memory may be required. In such a case, various modifications can be made. For example, in FIG. 16, the D/A conversion circuit DAC is prepared for only one color, and the image memory GRAM is all used for storing data for one color. It is also possible to generate three primary colors by using three chips in parallel. According to this, the memory capacity per color can be tripled. Further, the D/A conversion circuit DAC is the 16th D/A conversion circuit DAC.
As shown in the figure, it is provided for three colors, and if the memory capacity is small, it can be used as is, but when a large memory capacity is required, the D/A conversion circuit for two colors can be stopped, and the D/A conversion circuit for one color can be stored. Only the D/A conversion circuit is operated, and the image memory GR
A switching means that allows AM to be used as a memory for one color is provided in advance in the chip, and this is switched to 3 as described above.
Another option is to use chifubu. According to this method,
It can handle both cases where the required memory capacity is small or large. In FIG. 16, the image memory GRAM
Another possible method is to provide an expansion terminal in advance and connect an expansion memory to this terminal from the outside. The various methods described above can be similarly applied to the case where a D/A conversion circuit is provided as shown in FIG.

As mentioned above, by using MOS memory,
A semiconductor integrated circuit device tLsI in which a large capacity memory and an analog circuit are integrated into one chip can be realized.

The memory cells constituting this MOS memory include static type and dynamic type.

An example of a static memory cell is a pair of latch-type drive (memory) MOSFETs whose drains and gates are cross-connected as described above, a polysilicon high resistance element provided on each drain, and the drive MOS
Some devices are composed of a transmission gate MOSFET for address selection provided between the drain of an FET and a pair of complementary data lines (bit lines or digit lines).

Each MO3FET described above is composed of an N-channel MO8FET. This static type memory cell is capable of low noise operation and is suitable when low noise is particularly required. Further, when the polysilicon high resistance element is used, the occupied area can be made smaller than when a P-channel MO3FET is used.

On the other hand, examples of dynamic memory cells include a 1MO3 type consisting of an address selection MO3FET and an information storage capacitor, a storage MO3FET whose gate capacitance is used as a storage capacitor, and a readout MOSFET provided at its drain. and the above memory MOS FET
There is a 3MO3 type consisting of a writing MO3FET provided at the gate of the 3MO3 type. Since the number of IMO3 type memosa memory cells is small, it is excellent in high integration, and has low power consumption, so it is particularly suitable when a large capacity memory is required. The above-mentioned 3MO3 type memory cell is suitable for high S/N operation, and is particularly suitable when high S/N operation is required, since the information storage charge is amplified by the storage MO3FET and output. .

FIG. 17 shows a block diagram of an embodiment that embodies the circuit configuration of the embodiment shown in FIG. 10.

The memory cell array of the memory circuit RAM is constructed using highly integrated IMOSMOS memory cells, as shown by the dotted line in the figure. In addition, the data line pairs are designed to enable low noise and high S/N operation.

A so-called folded data line (bit line or digit y>m configuration) is adopted in which data lines D are arranged in parallel and a memory cell MC is arranged at one of the intersections with a word line W.

The peripheral circuitry including the sense amplifier SA that amplifies the minute signal from the memory cell MC is composed of a BICMO3 circuit that is a combination of a bipolar transistor and a CMOS (complementary MO3) circuit. In other words, circuits that require high integration and low power consumption, such as the sense amplifier SA,
Circuits that drive small-capacitance additions are 0M05 circuits with low power consumption and small footprint, and bipolar transistors are used for circuits that drive large-capacitance loads and circuits that require high-speed, high-sensitivity amplification of minute signals. circuit or commercial
The circuit is a combination of an OS circuit and a bipolar transistor. In addition to the above-mentioned dynamic memory using B i CMOS, there are analog circuits AC and logic circuits to which the techniques disclosed in JP-A-61-142594 and JP-A-61-170992 can be directly applied. Similarly in LOG, BiCMO3''?lI
Configure.

For example, in an analog circuit AC, the A/D conversion circuit and D/A conversion circuit that need to process minute high-speed signals are constructed with bipolar transistor circuits, and analog switch circuits are constructed using 0M03 circuits with low offset. Configure. As a result, a high-speed, high-precision A/D conversion circuit and D/A conversion circuit can be realized. Further, the reference voltage/current generating circuit REF shown in FIG. 15 can provide a highly stable reference voltage/current by using a well-known bipolar transistor bandgap generating circuit. Furthermore, the colored table CLT and parallel-to-serial conversion circuit P shown in FIG.
If the SCI and PSC2 are configured using bipolar transistors, high-speed operation is possible. In the logic circuit LOG as well, a high speed, low power consumption, and highly integrated logic circuit can be realized by selectively using the 0M03 circuit, the bipolar transistor circuit, or a combination of both as described above.

As a result, high speed, low power consumption, large capacity memory and high speed,
A semiconductor integrated circuit device that integrates a high-precision analog circuit can be realized. Note that here, everything other than the memory cell is B i
Although we have shown an example of using the 0M03 circuit, in cases where particularly low power consumption or low manufacturing costs are required, the 0M03 circuit may be used.
It can also be configured with only the M03 circuit.

According to the embodiments described above, by integrating the large-capacity memory and the analog circuit into one chip, the number of wires between them can be reduced and the length of the wires can be shortened, thereby minimizing the noise generated in these. can.

However, when the memory circuit is an IMO3 type memosa memory cell, a transient current may flow through the power supply line during charging/discharging operations of the data line, and this may affect the analog circuit AC side as noise.

Hereinafter, an embodiment that can reduce noise through this power supply line will be described.

FIG. 18 shows a schematic structural plan view of an embodiment of a semiconductor integrated circuit device.

Package PKG has multiple pins as external terminals. Two representative pins P1 and P2 among the plurality of pins are used as power supply pins. A semiconductor chip LSI is accommodated in the accommodation frame FLM. Bonding wiring L is attached to the above pins P1 and P2, respectively.
1 and L2 are provided. Bonding wiring BWI~B
W3 is the bonding wiring Ll of the package PKG,
L2 and the bonding pad BP on the semiconductor chip LSI
1. This is a bonding line for connecting BP2, and is usually made of aluminum. The bonding pads BPI and BF2 are for power supply including ground potential of the memory circuit RAM and analog circuit AC, respectively.
Wirings 121 and 122 are xi wiring formed on the semiconductor chip LSI.

According to this embodiment, the memory circuit RAM and the analog circuit A
The power supply of C is connected to separate pins Pl and P2, bonding wires BWI and BW2, and bonding pads BPI and BF2.
Since power is supplied through the wire, there is no noise interference between the circuits.In some cases, the bonding wire 1 is shared with the puff cage pin P1, as shown by the dotted line, bonding wire BW3. There is also a method of separating both from lines BWI and BW3. Since the package pin P1 and the bonding wiring 1 have relatively small inductance and resistance, this method can also reduce noise interference.

FIG. 19 shows a schematic plan view for explaining another embodiment of a low noise power supply circuit in a semiconductor integrated circuit device.

In this embodiment, the power supply wiring 12 on the semiconductor chip LSI
1 and 122 separate the power supplies to both circuits. This can also be expected to reduce noise, but in this embodiment, a decoupling circuit consisting of a resistor R and a capacitor C is also installed in the power supply wiring 122 of the analog circuit AC in order to remove the power supply noise from the memory circuit RAM. is provided.

According to this embodiment, the noise generated on the power line 121 due to the operation of the memory circuit RAM is removed by the decoupling circuit, so that the power line 121 is connected to the analog circuit AC.
It is possible to prevent noise from being transmitted through 2. The idea of the decoupling circuit used here can also be applied to the embodiment shown in FIG. As the resistor of the decoupling circuit, a resistor of aluminum wiring can be used, and in some cases, its self-inductance can be used to make the decoupling circuit even more effective. As a capacitor, a wiring capacitor can be used, but to further increase the effect, an inversion layer capacitor such as a MOSFET that can obtain a large capacitance value in a small area may be added. It is also conceivable to form a capacitor on the back surface of the chip and use it as the capacitor C by taking advantage of the fact that the circuit is formed only on the main surface.

In the above embodiment, the memory circuit RAM and the analog circuit AC
Although we have described the power supply method for It is also conceivable to use the various low-noise supply voltages described above independently in the reference voltage/current generating circuit REF and the like.

The method for reducing noise using the power supply method has been described above, but there is also a method for reducing noise by taking advantage of the fact that the memory circuit RAM and analog circuit AC are integrated and considering the operation timing of both circuits. For example, as shown in FIG. 20, a switch SW may be provided in series with the resistor R, and the switch SW may be turned off to disconnect the power line 122 at the timing when noise is generated due to the operation of the memory circuit RAM. Conceivable. According to this method, when noise occurs, the power supply is completely isolated, so the influence of the noise can be completely eliminated. Note that if a method is adopted in which the resistor R is also used as the on-resistance of a MOSFET, the switch SW and the resistor R can be realized by one MOSFET. That is, M
A pulse generated when the memory circuit RAM operates is supplied to the gate of the OS FET, and when the memory circuit RAM generates noise and does not operate, the MO3FET is turned on and its on-resistance is changed to the resistor R. It functions as a decoupling circuit together with the capacitor C. When the memory circuit RAM operates with noise generation, the MOSFET is turned off to function as a switch SW. In addition, the memory circuit RAM
Equivalent noise reduction can be achieved by simultaneously adjusting the timing at which noise occurs in the analog circuit and the timing at which there is no problem even if there is some noise from the power supply or other source in the analog circuit AC.For example, when applying to color graphic display. In addition, the timing of charging and discharging operations of the data line, which is likely to cause the largest noise in the memory circuit RAM, and the blanking during horizontal or vertical sweep of the display, where there is little problem even if noise occurs in the D/A conversion circuit in the analog circuit AC. By matching the timing of the operation, it is possible to reduce noise.

Various embodiments have been described above, but if memory circuits, digital circuits, analog circuits, etc. are mixed on the same half-quad chip as in these embodiments, wafer probing and Not only do various functional tests for determining whether a product is good or defective after completion or for quality assurance become extremely complicated, but in some cases, it may not be possible to carry out sufficient tests.

FIG. 1 shows a block diagram of an embodiment of a semiconductor integrated circuit device that solves the above problem.

In this embodiment, a function is provided that allows each of the memory circuit, digital circuit, and analog circuit to be directly tested from the outside.

In this embodiment, the configuration of the semiconductor integrated circuit device shown in the embodiment of FIG. 11 is taken as an example. Switch SWO1~5
W12 is an analog switch for switching the output signals of both the digital circuit and the analog circuit, and the signal 2
25 is its control signal. Actually, each switch SW
Depending on the control of O1-5WI2, each switch SW01-
Although a plurality of control signals are required in response to the switch operation of the 5WI2, they are simplified here and shown as one signal to prevent the drawing from becoming complicated.

In this embodiment, if the switches SWO1 and 5W11 are turned on and the switches 5WO2 and 5W12 are turned off, signals can be directly input from the outside to the image memory GRAM via the input terminal 101, the switch 5WOI, and the wiring 221. Also, the operating state of the image memory ORAM is determined by the wiring 22.
3. The signal can be output directly to the outside via the switch 5WII and the output terminal 102. In this way, direct access to the image memory GRAM becomes possible.
Even though the image memory GRAM is built into the above-mentioned complex semiconductor integrated circuit device LSI, it can be tested in the same manner as a single memory device.

On the other hand, if the switches SWO1 and 5WII are turned off and the switches SWO2 and 5W12 are turned on, the operation of the D/A conversion circuit DAC as an analog circuit can be directly tested from the outside using the input terminal 101 and the output terminal 102. 8 or more, it becomes possible to easily test each circuit part. In addition, during normal operation, switch 5WO
I and 5W12 are turned on, switches 5WO2 and 5W1
1 is turned off, it is possible to perform exactly the same operation as the embodiment shown in FIG. 11.

Further, in each test, either a digital signal or an analog signal may be applied to each switch depending on the purpose of the test.

In this embodiment, the signal line 201 connecting the image memory GRAM and the D/A conversion circuit DAC is the same as in the embodiment shown in FIG. output the signal directly to the external terminal, or directly output the signal from the external terminal to the D/D/
The signal may be configured to be input to the A conversion circuit DAC.

Further, in order to test the control circuit C0NT, a switch may be provided to output various control signals 202 and 203 output from the control circuit C0NT to the outside.
In order to reduce the number of external terminals, when testing the control circuit C0NT, we focused on the fact that the image memory GRAM does not test the D/A conversion circuit DAC at the same time. 101, D/
The output terminal 102 of the A conversion circuit DAC is connected to the control circuit C
It is desirable to use it as a terminal to output the 0NT signals 202 and 203 to the outside, or the above signal 20
2 and 203 may be input to a test shift register and serially output. In this case, one terminal outputs a plurality of control signals output from the control circuit C0NT. be able to.

In addition, although we have described an example in which the switch is used only in the test operation mode, depending on the purpose, it is also possible to use the same signal to switch and transmit both digital and analog signals during normal actual operation. In this embodiment, a case where the switch is applied to the embodiment shown in FIG. Needless to say, it can be used to conduct accurate tests.

FIG. 2 shows a circuit of a specific example of an analog switch used for the above-mentioned tests and the like. This switch circuit includes switches 5WOI to SW shown in FIG.
Used as I2. This switch circuit is a CMO
It is an S switch circuit, and includes an N-channel MO3FETQN and a P-channel MO3FETQP that are arranged in parallel.
In response to the switch control signal φ supplied to the gate of the N-channel MO3FETQN, the P-channel MO3FE
It is composed of an inverter circuit INV that transmits information to the gate of TQP. For example, when the control signal φ is at high level, the N-channel MO3FETQN and the P-channel MO3FET
Both QPs are turned on, and a digital signal or an analog signal can be bidirectionally transmitted from the terminal A side to the terminal B side or from the terminal B side to the terminal A side at high speed without voltage loss. When the control signal φ is at a low level, both the N-channel MO5FETQN and the P-channel MO8FETQP are turned off, and the connection between terminals A and B is cut off.
Although we have shown an example of a circuit using O3FETQN, in some cases P-channel MO3FET or N-channel MO3 may be used.
It is also possible to configure only one of the FETs to be a MOSFET.

Various embodiments have been described above, but this is a great example!
s! When memory, digital circuits, and analog circuits are mounted on the same chip, it becomes possible to use these circuits to realize new functions that have never existed before.

FIGS. 3A to 3D are conceptual diagrams for explaining the functions of the present invention, and when applied to a graphic display of a computer terminal device, etc., the number of pixels and gradation of the display The number of bits as data is mutually variable, and as shown in Figure 3A, high pixel display,
High gradation (or color tone) display as shown in Figure 3B, 3C
A combination of both is displayed as shown in the figure and FIG. 3D. That is, in FIGS. 3A to 3D,
The display screen DSP consists of a CRT (cathode ray tube), liquid crystal display panel, plasma display panel, etc.
The black circles shown there are display pixels (picture elements) with relatively low (few) gradations (or colors), for example, displaying 4 bits per pixel, that is, 24 gradations/pixel.
The white circles H shown on the display screen DSP are display pixels with relatively high gradations, and display, for example, 8 bits per pixel, that is, 21 gradations/pixel.

FIG. 3A is an example of a high-pixel display in which the entire surface of the display screen DSP is displayed with black circles L (4 bits/pixel) of relatively low gradation, and the number of display pixels is increased instead.

In Figure 3B, the entire surface of the display screen DSP is displayed with relatively high gradation white circles H (8 focus/pixel), and instead, the number of display pixels is reduced to 1/2 of that in Figure 3A, resulting in a high gradation display. This is an example.

FIG. 3C is a partial combination of FIG. 3A and FIG. 3B. For example, the high pixel display (FIG. 3A) is used as a background, and therein there is a high gradation display area D as shown by the dotted line.
SP' is provided. This high gradation display area DSP' is
The number of display pixels is reduced to 1/2 as shown in FIG. 3B.

Figure 3D shows the high gradation display area D in Figure 3C above.
SP' is displayed with a high number of pixels like other areas.

Each of the display examples described above allows various displays to be performed depending on the purpose.
It is now possible to display image information such as R (video tape recorder) in high gradation, and text and graphic information such as computer output in high pixel display, and display each display on the same display screen under the best conditions. Become. In the above example, the high pixel display of black circles was explained as 4 bits/pixel, and the high gradation display of white circles H was explained as 8 bits/pixel. Of course, it is also possible to perform even higher quality color display using 24 bits/pixel.

FIG. 4 shows a block diagram of an embodiment of a semiconductor integrated circuit device that performs the display operations shown in FIGS. 3A to 3D.

This embodiment is based on the semiconductor integrated circuit device shown in FIG. 11, and a circuit for realizing the display operation described above is added.

The output signal 201 of the image memory GRAM is on the one hand supplied to one input 231 of the D/A conversion circuit DAC through an AND gate circuit G1. Above signal 2
01 is supplied to the other input 232 of the D/A conversion circuit DAC through the delay circuit DL and the AND gate circuit G2. The above AND gate circuits G1 and G
2, controlled by control signals 233 and 234, respectively, generated by control circuit C0NT. The delay circuit DL receives a control signal 23 formed by the control circuit C0NT.
5. D/A conversion circuit DA of this embodiment
C is made to have input bits (232) necessary for high gradation display. Although the delay circuit DL is not particularly limited,
Consists of a 1-bit shift register, control circuit C0N
Image memory GRA according to clock signal 235 from T
Image data 201 from M is output after being delayed by one clock period of the read operation.

FIG. 5 shows a conceptual diagram for explaining an example of the display operation.

This figure shows a case where high pixel display (black circles) and high gradation display (white circles H) coexist, as in the second and third lines in FIG. 3C. Here, the black circle indicates 4 bits/pixel, and the white circle H indicates 8 bits/pixel.

Also, to facilitate understanding of the operation, the signal 201.2
31 and 232 are shown in binary numbers of logic "0" and "1", and signals 233 to 235 are shown in the form of pulses (waveforms).

In the figure, a signal 201 consisting of 4 bits for display read out from the image memory GRAM is output in time series from time TO to T7 in synchronization with the sweep timing of the display device. This time TO-T7 corresponds one-to-one to each pixel in the horizontal direction (row direction) in FIG. 3C.

Therefore, when displaying the second and third lines as described above, times TO, TI, T6, and T7 are high pixel display (black circles), and times T3 and T5 are high pixel display (black circles).
The output signal 230 of the delay circuit DL is indicated by a white circle H)
is the clock pulse 2 supplied from the control circuit C0NT.
35, the signal 201 is delayed by one clock (the unit time of the read timing). That is, the signal 201 output at time TO is output at time T1.
is output as a signal 230. The signals 201 and 230 are the AND of the control signals 233 and 234 formed by the control circuit C0NT. In other words, the signal 233 controls the opening and closing of the gates of the AND gate circuits G1 and G2.
and 234, the D of the above signals 201 and 230
/A selective input to the A conversion circuit DAC.

Therefore, at the input 231 of the D/A conversion circuit DAC,
When the control signal 233 arrives, that is, at the display times TO, Tl, T3, T5, T6, and T7, the control signal 233 is generated and the AND gate circuit G1 opens its gate, so it is synchronized with each timing. The display data 201 read out from the image memory ORAM is input as the signal 201 as it is. In addition, the D/A conversion circuit DA
When a control signal 234 arrives at the input 232 of C,
That is, at the display times T3 and T5, the control signal 23
4 is generated and the AND gate circuit G2 opens its gate, so that the output signal 230 of the delay circuit DL is input. The output signal 230 of the delay circuit DL is output at the times T3 and T.
Image memory GR at times T2 and T4 one time before 5.
This is display data 201 read from AM.

As a result, at times TO and T1 and T6 and T7,
Only the 4-bit display data read from the image memory GRAM at each timing, that is, only the display data is input to the input 231 of the D/A conversion circuit DAC. On the other hand, at times T3 and T5, input 2
31, the 4-bit display data read at times T3 and T5 as described above, and the display data read at the previous time T2 and T4, respectively, are input to the input 232. . Therefore, in the D/A conversion circuit DAC,
Since a total of 8 bits of display data is input, high gradation display H can be performed.

It should be noted that at times T2 and T4, the gate circuits G1 and G2 are not opened and the M signal is not formed. Therefore, the display data corresponding to the above-mentioned times T2 and T4 is not output, and the display data is not displayed in the high gradation display area DSP'. The number of pixels is set to 172.

As mentioned above, the control of high pixel display and high gradation display is
It utilizes the fact that image data is output in time series from the image memory GRAM, and expands the bits for high gradation display through temporal signal processing, and this can be easily done using control signals 233 and 234. be able to. In this manner, in this embodiment, display operations as shown in FIGS. 3A to 3C can be selectively performed by adding only a few circuits such as gate circuits and delay circuits.

FIG. 6 shows a block diagram of an embodiment of a semiconductor integrated circuit device that realizes the display operation shown in FIG. 3D.

In this embodiment, as shown in FIG. 3D, in order to enable high gradation display without reducing the number of pixels, the image memory G
A high gradation image memory GRAMH is added to the RAM. The output signal 201 of the image memory GRAM is directly transferred to D.
/A conversion circuit DAC, high gradation image memory G
The output signal 237 of the RAMH is transmitted to the aforementioned expansion input 232 of the D/A conversion circuit DAC via the AND gate circuit G3. The AND gate circuit G3 opens and closes its gate according to the control signal 236 generated by the control circuit C0NT, in other words, the high gradation signal 2
The input to the D/A conversion circuit DAC No. 37 is controlled.

This generates a control signal 236 corresponding to the display area where high gradation display is to be performed, opens the gate of the AND gate circuit G3, and inputs the display data from the high gradation image memo IJGRAMH to the D/A conversion circuit DAC. do. D/A
The conversion circuit DAC combines the display data from the image memory GRAM and the display data from the high gradation image memory GRAMH to form a high gradation display signal as display data for one pixel.

The memory capacity of the high gradation signal memory GRAMH is appropriately selected depending on the number of bits for high gradation display and the size of the area for high gradation display.

FIG. 7 shows a block diagram of still another embodiment of the invention.

In this embodiment, in the display other than the high gradation display signal, the 13th
As in the embodiment shown in the figure, the color combinations that can be displayed using the coloring table CLT can be expanded. Here, the color combinations that can be selected using the coloring table CLT are set to be the same as the level I (or color tone) during high gradation display. If you do this, each colored table CL
When using T, the D/A conversion circuit DAC prepared for use can be used as is without special modification for high gradation display. That is, each D/A conversion circuit DAC in the case of using the colored table CLT has the ability to display high gradations.

In this embodiment, during high gradation display, the image memo IJGR
AM and high gradation image memory GRAMH outputs 201 and 2
37 is an AND gate 02 when the control signal 239 is set to a logic "1" level by the control circuit C0NT.
Of the logic circuits as switching gate circuits, respectively constituted of circuits G3 and G4, an OR gate circuit G6 receiving their outputs, and an AND gate circuit G7 and G8, and an OR gate circuit G9 receiving their outputs, the above The signals are directly input to the D/A converter circuit DAC as inputs 231 and 232 through the gate circuits G5 and G6 and G8 and G9. On the other hand, when the control signal 238 instead of the control signal 239 becomes logic "1", the colored table CLT is referred to and its outputs 240 and 241 are inputted through the gate circuits G4 and G6 and G7 and G9 forming the logic circuit. 23
1 and 232 are input to the D/A conversion circuit DAC.

This makes it possible to expand the combinations of colors that can be displayed using the coloring table CLT even in cases other than high gradation display. This method of using the colored table CLT can be applied as is to the embodiment shown in FIG. 4.

Above, embodiments for realizing various display functions have been shown using FIGS. 4, 6, and 7, but these embodiments can also be applied to the various embodiment circuits described previously. Needless to say, it is a thing.

The effects obtained from the above examples are as follows. That is, (1) a semiconductor integrated circuit device including a digital circuit and an analog circuit is provided with a changeover switch that enables direct access to the digital circuit and the analog circuit from the outside in response to a test mode signal; As a result, it is possible to perform a functional test of each circuit reliably and in a short time.

(2) In a semiconductor integrated circuit device for graphic display that is equipped with an image memory as a digital circuit and a D/A conversion circuit as an analog circuit as described above, image data output from the memory in time series is By generating image data for high gradation through temporal signal processing or spatial division of the memory, an effect can be obtained in that a high gradation display area can be selectively formed on one display screen.

(3) Through (2) above, a high-quality display screen is created by combining video signals for television programs and VTRs that require high gradation with characters and graphics generated by computers, etc. that require high pixels. You can get the effect that you can.

(4) By providing a high-gradation image memory that stores high-gradation image data, it is possible to selectively display high gradations while maintaining a high number of pixels.

(5) A coloring table is provided in the output section of the image memory for high gradation that stores image data for high gradation and the image memory for high pixel to expand the bits, and when the above-mentioned high gradation display is not performed, By using the expansion bits formed by the coloring table described above, it is possible to achieve the effect of performing high gradation display and expanding the number of displayable color combinations.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it goes without saying that various changes can be made without departing from the gist thereof. For example, the present invention has been mainly described in the case where it is applied to a color graph ink display of a computer terminal, etc., but the present invention is not limited to this, and the present invention can be applied to a color printer, a laser beam printer, a high-speed printer, etc. High-capacity devices such as high-definition digital television receivers, image memories with D/A conversion circuits such as VTRs, or converting arbitrary analog physical quantities into digital signals using measuring instruments, IUI devices, etc. and storing them in memory. It can be widely applied to various semiconductor integrated circuit devices that require memory and analog circuits.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, by providing a semiconductor integrated circuit device including a digital circuit and an analog circuit with a changeover switch that enables direct access to the digital circuit and analog circuit from the outside in response to a test mode signal, Functional tests of each circuit can be performed reliably and in a short time. Furthermore, in the semiconductor integrated circuit device for graph ink display, which is equipped with an image memory as a digital circuit and a D/A conversion circuit as an analog circuit, as described above, image data output from the memory in time series is By generating image data for high gradation through temporal signal processing or spatial division of the memory, a high gradation display area can be selectively formed on one display screen.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a specific circuit diagram showing an embodiment of the switch used in the embodiment of Fig. 1, and Figs. 3A to 3D. 4 is a conceptual diagram for explaining the display operation of another embodiment of the present invention, FIG. 4 is a block diagram showing an embodiment for realizing the display operation shown in FIG. 3C, and FIG. The diagram is
An operational conceptual diagram for explaining an example of the operation; FIG. 6 is a block diagram showing one embodiment for realizing the display operation shown in FIG. 3D; FIG. 7 is a block diagram showing another embodiment. The block diagram shown in FIG. 8 is as follows.
FIG. 9 is a block diagram showing an embodiment of the basic concept of the semiconductor integrated circuit device to which the present invention is applied; FIG. 9 is a block diagram showing another embodiment of the semiconductor integrated circuit device; FIG. FIG. 11 is a block diagram showing another embodiment of the semiconductor integrated circuit device; FIG. 12 is a block diagram showing another embodiment of the semiconductor integrated circuit device; FIG. 12 is a block diagram showing another embodiment of the semiconductor integrated circuit device; 13 is a block diagram showing another embodiment of the semiconductor integrated circuit device; FIG. 14 is a block diagram showing another embodiment of the semiconductor integrated circuit device; FIG. FIG. 15 is a block diagram showing another embodiment of the semiconductor integrated circuit device, FIG. 16 is a block diagram showing another embodiment of the semiconductor integrated circuit device, and FIG. 17 is a block diagram showing another embodiment of the semiconductor integrated circuit device. A block diagram showing another embodiment of the device; FIG. 18 is a schematic plan view showing one embodiment of the semiconductor integrated circuit device; FIG. 19 is a block diagram showing another embodiment of the semiconductor integrated circuit device. Schematic Plan View FIG. 20 is a schematic plan view showing still another embodiment of the semiconductor integrated circuit device. LSI: Semiconductor chip, GRAM: Image memory, D
AC...D/A conversion circuit, sw, sw. 1~5W12...Switch, C0NT...Control circuit, Q
N...N channel MOSFET5QP...P channel MO3FET, INV...inverter circuit, L...high pixel display, H...high gradation display, DSP...display screen, D
SP'...High gradation display area, G1-G9...Gate circuit, DL...Delay circuit, GRAMH...Image memory for high gradation, CLT...Coloring table, RAM...Memory circuit, A
C...Analog circuit, Fl, F2...Fuse means, L
OG...logic circuit, AU...input logic circuit, pscl,
PSC2...Parallel-serial conversion circuit, ADC...A/D conversion circuit, REF...Reference voltage/current generation circuit, MC3...Memory cell array, SA...Sense amplifier, MC...Memory cell, PI, F2... External bin, Ll, L2... bonding wiring, BWI~BW3... bonding wire,
BPI, BF2...Bonding band, PKG...Package, FLM...Accommodation frame

Claims (1)

[Claims] 1. A changeover switch circuit that includes a digital circuit and an analog circuit and enables direct access to the memory circuit and the analog circuit from the outside in response to a test mode signal. Features of semiconductor integrated circuit devices. 2. The semiconductor integrated circuit device according to claim 1, wherein the digital circuit is a memory circuit comprising a MOSFET. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the changeover switch circuit is constituted by a CMOS switch circuit. 4. A memory circuit that stores digital image data, and a D/D that receives the image data and outputs an analog video signal.
A conversion circuit, and has a function of generating image data for high gradation by temporally processing the image data outputted from the memory in a time-series manner or by spatially dividing the memory circuit. Semiconductor integrated circuit device. 5. The circuit that generates the image data for high gradation includes a delay circuit that delays the image data read out in time series from the memory circuit by one clock, and a delay circuit that delays the image data read out in time series from the memory circuit by one clock, and outputs the image data and the output signal of the delay circuit according to a control signal. 5. The semiconductor integrated circuit device according to claim 4, further comprising a logic gate circuit for transmitting data to an input of a D/A conversion circuit. 6. The memory circuit includes a first image memory that stores image data for high pixels and a second image memory that stores image data for high gradation, and the memory circuit includes a first image memory that stores image data for high pixels, and a second image memory that stores image data for high gradation. The semiconductor integrated circuit according to claim 4, wherein the image data for high gradation is transmitted to the input for high gradation of a D/A conversion circuit through a logic gate circuit controlled by a control signal. Device.