JP2655466B2 - Packet switching equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet switching device, and more particularly, to a packet switching device using a multiprocessor system.

[0002]

2. Description of the Related Art Conventionally, a so-called small-scale packet switching device using a microprocessor has been known as a packet switching device. Since this small-scale packet switching device generally uses one microprocessor, it is difficult to increase the number of packet switching processes per unit time (hereinafter referred to as throughput).

[0003] In order to improve the throughput, a packet switching device using a multiprocessor system is known.
Such a packet switching device is, for example, an IEEE N
et al., published in the January 1991 issue of Etower Magazine, a paper by Cheetahbert, entitled "High Speed
d Transport ".

[0004] In a packet switching apparatus, switching processing is performed as follows.

(1) Extract a header portion from a received packet.

(2) Analyzing the contents of the extracted header, rewriting the extracted header with new information based on the analysis result,
An output port to be used as a rewrite header and for transmitting a packet is determined.

(3) A rewrite header is added to a packet and transferred to an output port.

In the above-mentioned paper, the above-mentioned exchange processing is divided and executed by a plurality of microprocessors.

As described above, by performing a series of exchange processing by a plurality of microprocessors, a part of the exchange processing can be performed by another microprocessor, that is, the exchange processing can be performed simultaneously and in parallel. Therefore, generally, it is possible to improve the throughput.

[0010]

However, in the above-described packet switching device, it is necessary to transfer information between the microprocessors. As the number of microprocessors increases, the amount of information transferred between the microprocessors increases. As a result, the time required for information transfer between microprocessors becomes longer than the throughput improvement by parallel processing. In other words, when the number of microprocessors increases, the information transfer time between the microprocessors cannot be ignored, and as the number of microprocessors increases, the degree of improvement in throughput decreases.

An object of the present invention is to provide a packet switching device using a multiprocessor system in which the degree of improvement in throughput is remarkable.

[0012]

According to the present invention, there is provided a packet switching apparatus for receiving a transmission packet as a reception packet, exchanging the reception packet, and outputting as an output packet, a plurality of processor units, a common memory, A first interface unit that writes the transmission packet to the common memory as the reception packet; and a second interface unit that sends the output packet, wherein the processor units each monitor the common memory. Determining means for determining whether or not the received packet is an unprocessed packet; and, if the received packet is determined to be an unprocessed packet, performing predetermined processing on a header of the unprocessed packet to exchange the processed packet. And processing means for writing to the common memory. Interface unit sends the replacement processed packet on said common memory as the output packet, the processor unit packet switching device is obtained, characterized in that to perform the replacement process independently of each other.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments.

Referring to FIG. 1, the illustrated packet switching apparatus includes first to third processor units 11 to 13. Then, the first processor unit 11 has C
PU 11a, program memory (P-MEM) 11b,
And a data memory (D-MEM) 11c.
These CPU 11a, P-MEM 11b, and D-ME
M11c are connected to each other by a local bus 11d. Although not shown, the second and third processor units 12 and 13 are also connected to the first processor unit 1.
1 are provided with the same components.

The packet switching apparatus further includes LAN interface units 14 and 15 and a common memory 16, and includes first to third processor units 11 to 13, LAN interface units 14 and 15,
And the common memory 16 are connected to each other by a data bus 17.

The packets continuously transmitted on the line from the transmission source are received by the LAN interface unit 14 as incoming packets, and are sequentially written to the common memory 16 via the data bus 17. The first to third processor units 11 to 13 constantly monitor the common memory 16 via the data bus 17.

Referring also to FIG. 2, the first to third processor units 11 to 13 operate independently. Here, paying attention to the first processor unit 11, the CPU
11a operates based on a program stored in the P-MEM 11b. The CPU 11a accesses the common memory 16 via the data bus 17 to store unprocessed incoming packets (hereinafter, simply referred to as unprocessed packets).
It is determined whether or not it exists within (step s1). If it is determined that there is an unprocessed packet in the common memory 16, C
The PU 11a extracts a header from the unprocessed packet (step s2). If there are a plurality of unprocessed packets, the header is extracted for one of the plurality of unprocessed packets.

In the D-MEM 11c, a table storing information indicating whether or not to output corresponding to each destination address is set, and the CPU 11a refers to the table by the destination address in the extraction header and refers to the table. It is determined whether to output a header, that is, a packet (step s3). If the packet is to be output, the CPU 1
In step 1a, an updated header is generated by rewriting the source address in the header to the own station address. (Step s
4). Then, the CPU 11a replaces the update header with the corresponding packet to obtain an update packet (step s5).

The updated packet (updated packet) is output from the common memory 16 by the LAN interface unit 15 via the data bus 17 to the line as an output packet.

Referring to FIGS. 1 and 3, the second and third processor units 12 and 13 also perform the same exchange processing as the first processor unit 11. For example, as shown in FIG. Assuming that the first to third arriving packets are sequentially written to the common memory 16, first, at the stage where the first arriving packet is written to the common memory 16, for example, the first processor unit 11 executes a program. , Generate a first update packet. If a second incoming packet is written to the common memory 16 during execution of a program by the first processor unit 11,
The second processor unit 12 executes a program and generates a second update packet. The generation of the first update packet is completed during the execution of the program by the second processor unit 12, and the first update packet is output as the first output packet. Further, if a third incoming packet is written to the common memory 16 during the execution of the program by the second processor unit 11, the third processor unit 13 executes the program,
Generate a third update packet. The generation of the second update packet is completed during the execution of the program by the third processor unit 13, and the second update packet is output as the second output packet. And finally the third
Is output as a third output packet.

In the above-described embodiment, a packet switching apparatus having three processor units has been described. However, it is sufficient if a plurality of processor units are provided, and if these processor units are operated independently, the same applies. An exchange process can be performed.

[0022]

As described above, in the present invention, since a plurality of processor units are operated independently, it is not necessary to transfer information between the processors and parallel processing can be performed. As a result, the number of processors is reduced. There is an advantage that the throughput is improved in proportion.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a packet switching device according to the present invention.

FIG. 2 is a flowchart for explaining processing of each processor unit in the packet switching device shown in FIG.

FIG. 3 is a diagram for explaining a packet switching procedure in the packet switching device shown in FIG. 1;

[Explanation of symbols]

 11, 12, 13 Processor unit 14, 15 LAN interface unit 16 Common memory 17 Data bus

Continuation of the front page (56) References JP-A-62-95049 (JP, A) JP-A-58-97944 (JP, A) IEICE General Conference, 1983 (issued March 5, 1983) 1680 Kunio Uemura, Minoru Nakamura, Shigeru Oyama "Processor Arrangement of Load Balancing Packet Switch" IEICE General Conference 1983 (March 5, 1983) 1687 Minoru Nakamura, Katsuharu Noguchi, Akira Hamaguchi " Study of Function Distribution Method in Packet Switching "Research and Application Report VOL. 35 NO.5 (May 22, 1986) P481-492 Zenichi Yatsushiro, Mineo Nishiwaki, Makoto Aoki, Takashi Honda "Large-capacity packet switching equipment"

Claims (1)

(57) [Claims] 1. A packet switching apparatus for receiving a transmission packet as a reception packet, exchanging the reception packet, and outputting as an output packet, a plurality of processor units, a common memory, and the transmission packet as the reception packet. A first interface unit for writing to a memory and a second interface unit for sending the output packet
Interface unit, wherein each of the processor units monitors the common memory to determine whether the received packet is an unprocessed packet, and the received packet is an unprocessed packet. Processing means for performing predetermined processing on a header of the unprocessed packet and writing the exchanged packet and the common memory, and wherein the second interface unit performs the exchange processing on the common memory. A packet switching device for transmitting the completed packet as the output packet, and the processor units performing the switching process independently of each other.