JPH1188404A - Gateway device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain high speed for a gateway device by reducing access to a memory when a reception frame is processed and transferred by the device. SOLUTION: A network interface part 1 converts a frame from a real network so as to output it onto a bus, a protocol processing part 3 executes the header processing of the frame which is outputted from the interface part 1, a delay part 5 outputs the frame after waiting for the portion of the processing time of the processing part 3 when the frame of the interface part 1 is received, a switch part 6 replaces a header part in the frame of the delay part with processing data of the processing part 3 after the frame of the delay part is inputted so as to store it in a memory 2 as a transmission frame and a data transfer part 4 reads the transmission frame of the memory 2 so as to transfer it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a gateway device for connecting networks.

[0002]

2. Description of the Related Art In recent years, with the speeding up of information communication, there is a demand for speeding up, that is, improving the processing speed of this type of gateway device for connecting a plurality of networks. The gateway device performs various checks on the arrived frame to confirm its normality, and performs a search process or the like to determine the destination of the frame (frame transfer destination). In this case, prior to these processes, the gateway device temporarily stores the frames to be processed in a memory and then starts the processes.

FIG. 5 is a block diagram showing the configuration of such a conventional device. This gateway device is composed of a network interface unit 1, a memory 2, a protocol processing unit 3, and a data transfer unit 4. . Here, upon receiving the frame data from the real network, the network interface unit 1 transmits the MAC (Media).
Access Control) frame data and outputs it on the bus BUS. The frame data received and output by the network interface unit 1 is temporarily stored in the memory 2, then the header X is taken out by the protocol processing unit 3, processed, and stored again in the memory 2 as the header Y. Thereafter, the data transfer unit 4 takes out the processing data in the memory 2 and transfers it to another network as a transmission frame.

[0004]

As described above, in the conventional gateway device, the received frames are temporarily stored in the memory 2 before the processing is started. Also, the protocol processing unit 3 that processes the header of the received frame has a CP
A processor such as U is used, and the CPU reads necessary data from the memory 2 and performs processing. In this case, there arises a problem that the following four accesses occur for input / output of data in the memory 2.

[0005] First, a first access for writing received frame data as shown by the reference numeral in FIG. 5, a second access to read data to be processed by the CPU as shown by the reference numeral in FIG. There is a third access to write the data resulting from the processing by the CPU as shown by the arrow, and a fourth access to read the frame data by the data transfer unit 4 as shown by the symbol in FIG.

For this reason, even if the peripheral blocks such as the protocol processing unit 3 are operated at a high speed, there is a problem that the input / output access of the memory becomes a bottleneck and the speed of the gateway device cannot be increased. Accordingly, it is an object of the present invention to reduce the number of accesses to a memory and to increase the speed of a gateway device.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides an interface unit which converts frame data from a network into predetermined frame data when the frame data is input, and an interface unit which receives the frame data from the interface unit. A protocol processing unit for executing a plurality of processes such as a search process for searching for a transmission destination of the frame data and a process for checking whether the frame data is correct, and a memory for storing the frame data processed by the protocol processing unit It is. In addition, a first switch is provided on the input side of the protocol processing unit for inputting frame data output from the interface unit by a pipeline operation and supplying the frame data to the protocol processing unit, and the protocol processing unit is provided with a first switch. A plurality of processing units are provided to execute the above-described plurality of processes in parallel when frame data is input. A delay unit that delays frame data output from the interface unit; and a second switch that inputs the frame data from the delay unit and the frame data processed by the protocol processing unit. The delay unit transmits the processed frame data to the second switch after waiting the processing time of the protocol processing unit for the processing time of the protocol processing unit. The second switch replaces the header of the frame data input from the delay unit with the header input from the protocol processing unit and accumulates it in the memory. A plurality of interface units, a delay unit, a second switch, and a memory are provided. When a plurality of network units input frame data from a plurality of networks, the plurality of interface units convert the frame data into predetermined frame data. The first switch extracts the header data from the frame data and distributes the header data to a plurality of processing units of the protocol processing unit, and sends the extracted data to a plurality of second processing units. When the frame data is input from the corresponding delay unit, the switch replaces the header data with the processing data from the protocol processing unit and stores it in the corresponding memory.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the gateway device according to the present invention. In this figure, the present apparatus converts frame data input from a real network into a MAC (Media Access Controller).
ol: medium access control) a network interface unit 1 that converts the data into frame data and outputs it as a received frame, a protocol processing unit 3 that processes a header portion of the received frame, a delay unit 5 that delays the received frame, It comprises a switch 6 for replacing frame data with data from the protocol processing unit 3, a memory 2 for storing transmission frame data output from the switch 6, and a data transfer unit 4 for reading and transferring the transmission frame data from the memory 2. .

In the device shown in FIG. 1, when the network interface unit 1 receives frame data from a real network, it converts the frame data and outputs it on the bus BUS as a received frame. Upon input of the header X of the received frame, the protocol processing unit 3 performs various processes described later and outputs it to the switch 6 as a header Y. on the other hand,
Upon receiving the received frame on the bus BUS, the delay unit 5 waits for the time when the protocol processing unit 3 performs the header processing, and then sends the received frame to the switch 6.

Then, the switch 6 performs a switching operation to replace the header X of the received frame output from the delay unit 5 with the header Y from the protocol processing unit 3 and outputs the transmission frame as the header X of the received frame. I do. The transmission frame is stored in the memory 2 and read out by the data transfer unit 4 and transferred to another network.

As described above, the received frame is not immediately stored in the memory 2 but is stored in the memory 2 after the received frame is generated as a transmission frame by the protocol processing unit 3, the delay unit 5, and the switch 6. The number of accesses to the memory 2 as a whole can be reduced to two times as indicated by the symbol 中 in the figure. That is, since the operation of writing the frame data into the memory 2 and the operation of rewriting the frame data are simultaneously performed, the processing performed by the protocol processing unit 3 has been completed before the writing to the memory 2. The number of accesses can be reduced as compared with the conventional device. As a result, the speed of the gateway device can be increased.

Next, FIG. 2 is a block diagram showing a second embodiment of the present gateway apparatus, in which a switch 7 is added to the apparatus of FIG. Here, in the protocol processing unit 3, when the header processing of the received frame is performed,
MAC that searches for the destination of a frame based on header data
Routing table search processing, IP routing table search processing for searching for an IP (Internet Protocol) address, TTL (Time to Live) subtraction indicating the maximum life time of a frame packet, and TTL subtraction check processing for checking the same, protocol type And a checksum subtraction check process of subtracting the checksum of the header and data and checking the result. Here, the protocol processing unit 3 separates each of the above processes so that each process can be executed in parallel. That is, as shown in FIG. 2, a MAC routing table search processing unit 31, an IP routing table search processing unit 32, a TTL subtraction check processing unit 33, a protocol discrimination processing unit 34, and a checksum subtraction check process are performed in the protocol processing unit 3. A part 35 is provided.

In this case, a switch 7 is provided on the input side of the protocol processing unit 3. When the switch 7 receives a header of a received frame output from the network interface unit 1, the processing unit 31 of the protocol processing unit 3 receives the switch. ~ 3
5 With this configuration, the header data of the received frame is transferred to each processing unit 3 of the protocol processing unit 3 by the pipeline operation of the switch 7.
1 to 35, and are processed in parallel by the processing units 31 to 35. As a result, the processing of the protocol processing unit 3 can be speeded up. Also, as described later, when a plurality of frame data is input to the apparatus, each processing unit 31 of the protocol processing unit 3
To 35 can be used in common, so that an increase in the hardware scale of the apparatus can be suppressed.

FIG. 3 is a block diagram showing a third embodiment of the present gateway device. This device inputs and processes frame data from six real networks.
It is an example of an input configuration. In FIG. 3, when each of the six network interface units 1A to 1F receives frame data from the corresponding real network, it converts the frame data and outputs it on the bus BUS as a received frame. When the switch 7 receives the header of the received frame of each network interface unit, the switch 7 distributes the necessary data to each processing unit of the protocol processing unit 3 as in FIG. When each of the six delay units 5A to 5F receives a reception frame from each of the corresponding network interface units, the delay unit 5A waits for the header data processing time of the protocol processing unit 3 and then switches the reception frame.
Is output to

Six switches 6A constituting the judging unit 10
Upon receiving the received frames output from the corresponding delay units 5 and the results of the header processing of the protocol processing unit 3, the headers 6 to 6F replace the headers of the received frames with the headers processed by the protocol processing unit 3. Things. Note that each of the six memories 2A to 2F stores each frame data from the determination unit 6 in each of the six memories 2A to 2F.
Each of the data transfer units 4A to 4F reads out the stored data of the corresponding memory and transfers it as each transmission frame.

FIG. 4 shows the network interface unit 1.
FIG. 7 is a diagram showing a format of a received frame converted by the above. The received frames A to F output from the respective network interface units 1A to 1F have basically the same format. That is, the frame input and converted to the gateway device includes a header portion and a data portion as shown in FIG. 4, and the header portion includes a DestMAC region indicating a destination region of the MAC frame, a source of the MAC frame, SourceMAC area indicating the area, Type area indicating the type of this frame, full length area indicating the entire length of the frame, identifier area indicating the identification of the frame, Flag area indicating the position of the frame, TTL area indicating the lifetime of the frame, and TTL area of the frame. PRT area indicating protocol type, checksum area of frame, destination I
A D-IP area indicating a P address and an S-IP area indicating a source IP address are sequentially provided.

A data area is provided following the header section. In addition, in each of the network interface units 1A to 1F of the present apparatus, when each of the temporally random frame data is received from the real network,
Each frame data is provided to each of the delay units 5A to 5F and the switch 7 at the timing shown in FIG.

Next, the operation of the gateway device will be described with reference to FIGS. As described above, temporally random frame data is transmitted from the real network to this apparatus. In this case, each of the network interface units 1A to 1F performs a conversion process when random frame data is input, and then converts the converted frame data into a predetermined time t as shown in FIG. The signals are output to the corresponding delay units 5A to 5F at the shifted timing, and are also output to the switch 7.

Upon receiving the header of the received frame from each of the network interface units 1A to 1F, the switch 7 performs a process of allocating necessary header data to each of the processing units 31 to 35 in the protocol processing unit 3. Each of the processing units 31 to 35 in the protocol processing unit 3 performs a predetermined process, and outputs the processing result to the determination unit 6.

On the other hand, each of the delay units 5A to 5F sequentially receives each received frame, waits for a time necessary for the processing of the protocol processing unit 3, and then sequentially outputs the received frames to the determination unit 10. In this case, the determination unit 10 determines that the delay unit 5A
5F and the processing results of the processing units 31 to 35 of the protocol processing unit 3 are input. When it is determined that the header of the reception frame from the delay unit 5 needs to be rewritten, the corresponding switch 6 is used. Then, the header of the received frame is replaced with the processing data of the protocol processing unit 3 and output as a transmission frame. Thus, each transmission frame output from the determination unit 10 is sequentially stored in the corresponding memories 2A to 2F. Each transmission frame stored in each of the memories 2A to 2F is taken out individually by each of the data transfer units 4A to 4F and transferred to each real network.

As described above, when temporally random frame data is input from the real network, each network interface unit shifts the input frame data by a predetermined time, and also shifts the frame data shifted by the predetermined time. By being provided to the protocol processing unit 3 via the switch 7, each of the processing units 31 to 35 of the protocol processing unit 3 performs a continuous operation without a break, thereby improving the processing speed of the protocol processing unit 3 itself. be able to. In this case, since the switch 7 does not need to be provided for each network interface unit, an increase in the hardware scale of the device can be suppressed.

As described above, by arranging the protocol processing unit 3 in the preceding stage of the memory 2, the access to the memory 2 can be reduced. Therefore, the data processing speed of the device can be improved to the transmission speed of the bus BUS through which data passes. Further, by providing the frame data input to the protocol processing unit 3 in the form of a pipeline, the hardware scale can be reduced. As a result, it is possible to increase the speed and reduce the size of the gateway device.

[0023]

As described above, according to the present invention, when data input from a network and converted into a predetermined frame is input, a search process for searching a transmission destination of the frame data and a check process of the frame data are performed. And the like, and accumulate in the memory, the number of accesses to the memory can be reduced when the received frame is processed and transferred, so that the speeding up of the apparatus can be realized. In addition, a first switch is provided on the input side of the protocol processing unit for inputting frame data output from the interface unit by a pipeline operation and supplying the frame data to the protocol processing unit, and the protocol processing unit is provided with a first switch. When the frame data is input, a plurality of processing units for executing the above-described plurality of processes in parallel are provided, so that high-speed data processing of the protocol processing unit can be realized without increasing the hardware scale of the apparatus, and Higher speed of the device can be realized. Further, the protocol processing unit processes the header data of the input frame data and sends the processing result to the second switch, and the delay unit waits for the input frame data for the processing time of the protocol processing unit and then waits for the second processing. The second switch replaces the header of the frame data input from the delay unit with the header input from the protocol processing unit and stores it in the memory, so that the data to be processed can be processed accurately and at high speed. it can. When a plurality of interface units input frame data from a plurality of networks, the plurality of interface units convert the frame data into predetermined frame data, and transmit the converted frame data to each of the corresponding delay units and the first switch with a predetermined time offset from each other. And the first
Switches extract the header data in the frame data and distribute it to each of the multiple processing units of the protocol processing unit.
Each of the plurality of second switches receives the frame data from the corresponding delay unit, replaces the header data with the processing data from the protocol processing unit, and stores the data in the corresponding memory. Is processed and transmitted as a transmission frame, each processing unit of the protocol processing unit can be efficiently processed, and as a result, high-speed processing of the device can be performed without increasing the hardware scale.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a gateway device according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the gateway device.

FIG. 3 is a block diagram showing a third embodiment of the gateway device.

FIG. 4 is a diagram showing a format of frame data input and converted to the device shown in FIG. 3;

FIG. 5 is a block diagram showing a configuration of a conventional device.

[Explanation of symbols]

1, 1A to 1F: Network interface unit, 2,
2A to 2F: memory, 3: protocol processing unit, 4, 4A
-4F: Data transfer unit, 5, 5A-5F: Delay unit, 6,
6A to 6F: switch (second switch), 7: switch (first switch), 10: determination unit, 31: MAC routing table search processing unit, 32: IP routing table search processing unit, 33: TTL subtraction check Processing unit 34: Protocol discrimination processing unit 35: Checksum subtraction check processing unit

Claims (4)

[Claims] An interface unit that converts frame data from a network into predetermined frame data when it is input, a search process that searches for a transmission destination of the frame data when the frame data is input from the interface unit, and a search process of the frame data. A gateway device comprising: a protocol processing unit that executes a plurality of processes such as a right / wrong check process; and a memory that stores frame data processed by the protocol processing unit. 2. The system according to claim 1, further comprising: a first switch that inputs the frame data output from the interface unit in a pipeline operation and supplies the frame data to the protocol processing unit on an input side of the protocol processing unit. A gateway device, comprising: a plurality of processing units that execute the plurality of processes in parallel when frame data from a first switch is input to the protocol processing unit. 3. The delay unit according to claim 1, wherein the delay unit delays frame data output from the interface unit, and the frame data from the delay unit and the frame data processed by the protocol processing unit. A second switch for inputting the data, wherein the protocol processing unit processes the header data of the input frame data and sends out a processing result to the second switch. After waiting for the processing time of the processing unit, the data is transmitted to the second switch. When the second switch receives the frame data from the delay unit, the second switch replaces the header of the frame data with the header input from the protocol processing unit and stores the data in the memory. A gateway device. 4. The apparatus according to claim 3, further comprising a plurality of interface units, a delay unit, a second switch, and a memory, wherein the plurality of interface units convert frame data into predetermined frame data when each frame data is input from a plurality of networks. At the same time, each of the converted frame data is sent to the corresponding delay unit and the first switch with a predetermined time offset from each other, and the first switch extracts the header data from the frame data and outputs the header data to the plurality of processing units of the protocol processing unit. A plurality of second switches, each receiving frame data from a corresponding delay unit, replacing header data with processing data from a protocol processing unit, and storing the data in a corresponding memory. .