JP2652972B2 - D2 standard synchronous signal detector - Google Patents
D2 standard synchronous signal detectorInfo
- Publication number
- JP2652972B2 JP2652972B2 JP2083593A JP8359390A JP2652972B2 JP 2652972 B2 JP2652972 B2 JP 2652972B2 JP 2083593 A JP2083593 A JP 2083593A JP 8359390 A JP8359390 A JP 8359390A JP 2652972 B2 JP2652972 B2 JP 2652972B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- detection
- standard
- logical product
- operation means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明はD2規格のディジタルビデオ信号から水平同期
信号又は等化パルスを検出するD2規格同期信号検出器に
関する。The present invention relates to a D2 standard synchronous signal detector for detecting a horizontal synchronizing signal or an equalizing pulse from a D2 standard digital video signal.
［従来の技術］ 従来、この種の同期信号検出器は第３図に示すように
構成されている。即ち、ディジタルビデオ信号DVINはコ
ンパレータＣの一方の入力端に入力されている。このコ
ンパレータＣは他方の入力端にしきい値信号が入力され
て所定のしきい値DTHが設定されていて、第４図のタイ
ミングチャート図に示すように、入力信号DVINがしきい
値DTH以下になった時点で、これを水平同期信号又は等
化パルスとして検出し、その出力端から検出信号HEOUT
を出力する。[Prior Art] Conventionally, this kind of synchronization signal detector is configured as shown in FIG. That is, the digital video signal DV IN is input to one input terminal of the comparator C. The comparator C is being input threshold signal to the other input terminal is configured with a predetermined threshold D TH, as shown in the timing chart of FIG. 4, the input signal DV IN threshold D At the point of time when it becomes TH or less, this is detected as a horizontal synchronization signal or an equalization pulse, and a detection signal HE OUT is output from its output terminal.
Is output.
［発明が解決しようとする課題］ しかしながら、上述した従来の同期信号検出器におい
ては、入力されるディジタルビデオ信号DVINが水平同期
信号又は等化パルス以外の部分でしきい値DTH以下にな
った場合、これを誤って水平同期信号又は等化パルスと
して検出してしまうという問題点がある。[Problems to be Solved] However, in the conventional synchronizing signal detector described above, falls below the threshold D TH digital video signal DV IN horizontal synchronizing signal or a portion other than the equalizing pulse input In this case, there is a problem that this is erroneously detected as a horizontal synchronization signal or an equalization pulse.
本発明はかかる問題点に鑑みてなされたものであっ
て、水平同期信号又は等化パルスを正確に検出すること
ができるD2規格同期信号検出器を提供することを目的と
する。The present invention has been made in view of the above problems, and has as its object to provide a D2 standard synchronous signal detector that can accurately detect a horizontal synchronous signal or an equalizing pulse.
［課題を解決するための手段］ 本発明に係るD2規格同期信号検出器は、D2規格により
規定された複数の設定値からなる水平同期信号及び／又
は等化パルスを含むディジタル信号を入力し前記水平同
期信号及び／又は前記等化パルスの複数の設定値を夫々
検出する第１乃至第ｎのｎ個の信号検出手段と、この各
信号検出手段の検出信号の論理積を演算する第１乃至第
（ｎ−１）の（ｎ−１）個の論理積演算手段とを有し、
第１の論理積演算手段は、第１の信号検出手段の検出信
号を１ディジタルデータ分遅延した信号と第２の信号検
出手段の検出信号との論理積を演算するものであり、第
ｍ（ｍは２乃至ｎ−１）の論理積演算手段は、第（ｍ−
１）の論理積演算手段の出力信号を１ディジタルデータ
分遅延した信号と第（ｍ＋１）の信号検出手段の検出信
号との論理積を演算するものであることを特徴とする。[Means for Solving the Problems] A D2 standard synchronization signal detector according to the present invention is configured to input a horizontal synchronization signal composed of a plurality of set values specified by the D2 standard and / or a digital signal including an equalization pulse, and First to n-th n signal detecting means for detecting a plurality of set values of the horizontal synchronizing signal and / or the equalizing pulse, respectively, and first to n for calculating the logical product of the detection signals of the respective signal detecting means. (N-1) th (n-1) AND operation means,
The first AND operation means calculates the AND of a signal obtained by delaying the detection signal of the first signal detection means by one digital data and the detection signal of the second signal detection means. (m is 2 to n-1) AND operation means
The present invention is characterized in that a logical product of a signal obtained by delaying the output signal of the logical product calculating means of 1) by one digital data and a detection signal of the (m + 1) th signal detecting means is calculated.
［作用］ 本発明においては、D2規格により規定された複数の設
定値からなる水平同期信号及び／又は等化パルス（D2規
格同期信号）を含むデイジタル信号を複数の信号検出手
段に入力し、これらの信号検出手段において前記D2規格
同期信号の複数の設定値を夫々検出する。そして、全て
の前記信号検出手段の検出信号を論理積演算手段により
論理演算して、その論理積を求める。このため、D2規格
同期信号に含まれる全ての設定値を検出した場合に、こ
れをD2規格同期信号として検出することができる。従っ
て、入力信号のD2規格同期信号以外の部分を誤って同期
信号として検出することがなく、D2規格同期信号を正確
に検出することができる。[Operation] In the present invention, a digital signal including a horizontal synchronization signal and / or an equalization pulse (D2 standard synchronization signal) composed of a plurality of set values specified by the D2 standard is input to a plurality of signal detection units. A plurality of set values of the D2 standard synchronization signal are detected respectively. Then, the detection signals of all the signal detection means are logically operated by the logical AND operation means, and the logical product is obtained. Therefore, when all the setting values included in the D2 standard synchronization signal are detected, this can be detected as the D2 standard synchronization signal. Therefore, a portion other than the D2 standard synchronization signal of the input signal is not erroneously detected as a synchronization signal, and the D2 standard synchronization signal can be accurately detected.
［実施例］ 次に、本発明の実施例について添付の図面を参照して
説明する。Example Next, an example of the present invention will be described with reference to the accompanying drawings.
第１図は本発明の実施例に係るD2規格同期信号検出器
を示すブロック図である。FIG. 1 is a block diagram showing a D2 standard synchronous signal detector according to an embodiment of the present invention.
第１図に示すように、D2規格のディジタルビデオ信号
DVINはコンパレータC1乃至Cnの一方の入力端に入力され
ている。このコンパレータC1乃至Cnは、夫々他方の入力
端にしきい値信号が入力されて所定のしきい値D1乃至Dn
が設定されていて、入力信号DVINがしきい値D1乃至Dnと
等しくなる時点でパルス信号を出力する。As shown in Fig. 1, D2 standard digital video signal
DV IN is inputted to one input terminal of the comparator C 1 to C n. Each of the comparators C 1 to C n receives predetermined threshold values D 1 to D n when a threshold signal is input to the other input terminal.
There have been set, the input signal DV IN outputs a pulse signal at the time equal to the threshold D 1 to D n.
コンパレータC1の出力信号は遅延器DL1に入力され
る。この遅延器DL1はコンパレータC1の出力信号を１デ
ィジタルデータ分遅延させて出力信号CD1を出力する。The output signal of the comparator C 1 is input to the delay unit DL 1. The delay unit DL 1 outputs an output signal C D1 and the output signal of the comparator C 1 is delayed by one digital data content.
遅延器DL1の出力信号CD1及びコンパレータC2の出力信
号は論理積算器A1に入力される。この論理積算器A1は入
力される信号の双方の論理積（AND）をとって出力す
る。論理積算器A1の出力信号は遅延器DL2に入力され
る。この遅延器DL2は論理積算器A1の出力信号を１ディ
ジタルデータ分遅延させて出力信号CD2を出力する。Output signal C D1 and the output signal of the comparator C 2 delay element DL 1 is input to the logic accumulator A 1. The logical multiplier A 1 and outputs a logical product of both signals input (the AND). The output signal of the logical product operation unit A 1 is input to delayer DL 2. The delay unit DL 2 outputs an output signal C D2 delays 1 digital data content of the output signal of the logical product operation unit A 1.
このようにして、コンパレータC1乃至Cnに対応する遅
延器DL1乃至DLn-1及び論理積算器A1乃至An-1が順次接続
されていて、論理積算器An-1の出力端から出力信号HE
OUTが出力される。In this manner, the comparators C 1 to have delayer DL 1 to DL n-1 and a logic multiplier A 1 to A n-1 corresponding to C n are sequentially connected, the logic accumulator A n-1 of the output Output signal HE from the end
OUT is output.
次に、上述したD2規格同期信号検出器の動作につい
て、第２図のタイミングチャート図を使用して説明す
る。Next, the operation of the above-described D2 standard synchronous signal detector will be described with reference to the timing chart of FIG.
ディジタルビデオ信号DVINは、水平同期信号がD2規格
で規定された値D1乃至Dnからなる信号パターンにより構
成されている。Digital video signal DV IN is constituted by the signal pattern horizontal synchronizing signal is comprised of defined values D 1 to D n in D2 standard.
コンパレータC1乃至Cnの一方の入力端に入力信号DVIN
を入力すると、コンパレータC1乃至Cnは夫々水平同期信
号のパターンD1乃至Dnを検出する。Input signal DV IN to one input terminal of the comparator C 1 to C n
If you enter, the comparator C 1 to C n detects a pattern D 1 to D n of the respective horizontal synchronizing signals.
遅延器DL1はコンパレータC1により検出されたパター
ンD1の検出信号を１ディジタルデータ分遅延させて検出
信号CD1を出力する。Delayer DL 1 outputs a detection signal C D1 and 1 digital data content delays the detection signal of the detection pattern D 1 by the comparator C 1.
論理積算器A1はコンパレータC2により検出されたパタ
ーンD2の検出信号と遅延器DL1の検出信号CD1との論理積
をとってパターンD1及びD2を検出する。Logic multiplier A 1 detects the pattern D 1 and D 2 by taking the logical product of the detection signal C D1 of the detection signal delayer DL 1 of the detected pattern D 2 by the comparator C 2.
遅延器DL2は論理積算器A1の検出信号を１ディジタル
データ分遅延させて検出信号CD2を出力する。Delayer DL 2 outputs a detection signal C D2 delays 1 digital data content of the detection signal of the logical product operation unit A 1.
論理積算器A2はコンパレータC3により検出されたパタ
ーンD3の検出信号と遅延器DL2の検出信号CD2との論理積
をとってパターンD1及びD2を加えてパターンD3を検出す
る。Logic multiplier A 2 is detecting the pattern D 3 by adding patterns D 1 and D 2 by taking the logical product of the detection signal of the pattern D 3 that is detected and the detection signal C D2 of the delay circuit DL 2 by the comparator C 3 I do.
このようにして、コンパレータC1乃至Cnにより検出さ
れたパターンD1乃至Dnの検出信号の論理積を出力信号HE
OUTとして検出する。In this manner, the comparators C 1 to C n output signals a logical product of the detection signal of the detection pattern D 1 to D n by HE
Detect as OUT .
本実施例によれば、D2規格で規定されたパターンD1乃
至Dnの全てを検出した場合に、これを水平同期信号とし
て検出することができるので、水平同期信号以外の部分
を誤って水平同期信号として検出することはない。従っ
て、水平同期信号を正確に検出することができる。According to this embodiment, when detecting any defined pattern D 1 to D n in D2 standard, which can be detected as a horizontal synchronizing signal, erroneously portions other than the horizontal synchronizing signal horizontal It is not detected as a synchronization signal. Therefore, the horizontal synchronization signal can be accurately detected.
なお、本実施例においては、水平同期信号と同様にし
て、D2規格で規定された等化パルスも正確に検出するこ
とができる。Note that, in the present embodiment, similarly to the horizontal synchronization signal, the equalization pulse specified by the D2 standard can be accurately detected.
［発明の効果］ 以上説明したように本発明によれば、D2規格同期信号
に含まれる複数の設定値の全てを検出し、この検出信号
の論理積を求めることにより前記D2規格同期信号を検出
するから、D2規格同期信号を正確に検出することができ
る。[Effects of the Invention] As described above, according to the present invention, the D2 standard synchronization signal is detected by detecting all of a plurality of setting values included in the D2 standard synchronization signal and calculating the logical product of the detection signals. Therefore, it is possible to accurately detect the D2 standard synchronization signal.
第１図は本発明の実施例に係るD2規格同期信号検出器を
示すブロック図、第２図はそのタイミングチャート図、
第３図は従来の同期信号検出器を示すブロック図、第４
図はそのタイミングチャート図である。 C,C1,C2,C3,Cn;コンパレータ、A1,A2,An-1;論理積算
器、DL1,DL2,DL3;遅延器FIG. 1 is a block diagram showing a D2 standard synchronous signal detector according to an embodiment of the present invention, FIG. 2 is a timing chart thereof,
FIG. 3 is a block diagram showing a conventional synchronization signal detector, and FIG.
The figure is the timing chart. C, C 1 , C 2 , C 3 , C n ; Comparator, A 1 , A 2 , A n-1 ; Logic integrator, DL 1 , DL 2 , DL 3 ; Delay
Claims (2)
なる水平同期信号を含むディジタル信号を入力し前記水
平同期信号の複数の設定値を夫々検出する第１乃至第ｎ
のｎ個の信号検出手段と、この各信号検出手段の検出信
号の論理積を演算する第１乃至第（ｎ−１）の（ｎ−
１）個の論理積演算手段とを有し、第１の論理積演算手
段は、第１の信号検出手段の検出信号を１ディジタルデ
ータ分遅延した信号と第２の信号検出手段の検出信号と
の論理積を演算するものであり、第ｍ（ｍは２乃至ｎ−
１）の論理積演算手段は、第（ｍ−１）の論理積演算手
段の出力信号を１ディジタルデータ分遅延した信号と第
（ｍ＋１）の信号検出手段の検出信号との論理積を演算
するものであることを特徴とするD2規格同期信号検出
器。A digital signal including a horizontal synchronizing signal comprising a plurality of setting values defined by the D2 standard is inputted, and first to n-th detecting means respectively detect a plurality of setting values of the horizontal synchronizing signal.
N signal detection means, and first to (n-1) th (n-
1) AND operation means, wherein the first AND operation means includes a signal obtained by delaying the detection signal of the first signal detection means by one digital data and a detection signal of the second signal detection means. To calculate the logical product of m-th (m is 2 to n−
The AND operation means of (1) calculates the AND of a signal obtained by delaying the output signal of the (m-1) th AND operation means by one digital data and the detection signal of the (m + 1) th signal detection means. D2 standard synchronous signal detector, characterized in that:
なる等化パルスを含むディジタル信号を入力し前記等化
パルスの複数の設定値を夫々検出する第１乃至第ｎのｎ
個の信号検出手段と、この各信号検出手段の検出信号の
論理積を演算する第１乃至第（ｎ−１）の（ｎ−１）個
の論理積演算手段とを有し、第１の論理積演算手段は、
第１の信号検出手段の検出信号を１ディジタルデータ分
遅延した信号と第２の信号検出手段の検出信号との論理
積を演算するものであり、第ｍ（ｍは２乃至ｎ−１）の
論理積演算手段は、第（ｍ−１）の論理積演算手段の出
力信号を１ディジタルデータ分遅延した信号と第（ｍ＋
１）の信号検出手段の検出信号との論理積を演算するも
のであることを特徴とするD2規格同期信号検出器。2. A first to nth n-th digital signal including an equalizing pulse composed of a plurality of set values specified by the D2 standard and detecting a plurality of set values of the equalized pulse.
Signal detecting means, and first to (n-1) th (n-1) logical product calculating means for calculating the logical product of the detection signals of the respective signal detecting means. AND operation means,
It calculates the logical product of the signal obtained by delaying the detection signal of the first signal detection means by one digital data and the detection signal of the second signal detection means, and calculates the m-th (m is 2 to n-1) The AND operation means outputs a signal obtained by delaying the output signal of the (m-1) th AND operation means by one digital data and the (m +
A D2 standard synchronous signal detector for calculating a logical product of the signal and the detection signal of the signal detecting means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2083593A JP2652972B2 (en) | 1990-03-30 | 1990-03-30 | D2 standard synchronous signal detector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2083593A JP2652972B2 (en) | 1990-03-30 | 1990-03-30 | D2 standard synchronous signal detector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03283874A JPH03283874A (en) | 1991-12-13 |
| JP2652972B2 true JP2652972B2 (en) | 1997-09-10 |
Family
ID=13806789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2083593A Expired - Lifetime JP2652972B2 (en) | 1990-03-30 | 1990-03-30 | D2 standard synchronous signal detector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2652972B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5933611A (en) * | 1983-07-01 | 1984-02-23 | Hitachi Denshi Ltd | Generating and detecting circuit of synchronizing signal |
-
1990
- 1990-03-30 JP JP2083593A patent/JP2652972B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03283874A (en) | 1991-12-13 |
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