JP2647862B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the same, and mainly relates to a bipolar IC and a complementary metal oxide semiconductor (CMOSFET).
de Semiconductor Field Effect Transistor) IC and 1
The present invention relates to a technology for increasing the breakdown voltage of a semiconductor device (hereinafter abbreviated as BiCMOS IC) incorporated in one semiconductor chip.

[Conventional technology]

Bipolar ICs tend to be faster and more integrated, and miniaturization techniques and self-alignment techniques using selective oxide films are being pursued as means to achieve this. Along with this, the complexity of the process and the decrease in breakdown voltage have become problems. The above is from NIKKEIELECTRONICS published by Nikkei McGraw-Hill 1983
6.20 p.179-207.

[Problems to be solved by the invention]

Bipolar IC on one semiconductor substrate (semiconductor chip)
In particular, it has been found that the withstand voltage of a bipolar transistor is limited with the miniaturization of a BiCMOS IC coexisting with a CMOS IC.

In a BiCMOS IC, the base-collector junction breakdown voltage BV _CBO of a bipolar transistor particularly determines the upper voltage limit of the IC. In the current BiCMOS IC, the line width is 5
It is manufactured using a μm manufacturing process, but the BV _CBO in that case is limited to 40V. As a means for further increasing the breakdown voltage, it is necessary to increase the curvature of the base-collector junction of the bipolar transistor.

The present invention has been made to overcome the above-described problems, and an object of the present invention is to provide a semiconductor device having a bipolar semiconductor element coexisting with a CMOS IC.
The object is to improve the withstand voltage without particularly complicating the process.

Another object of the present invention is to provide a method for manufacturing a semiconductor device in which a bipolar semiconductor element finely processed at a high withstand voltage and a MOS FET coexist.

Still another object of the present invention is to provide a method of manufacturing a high-withstand-voltage BiCMOS IC by a simple manufacturing process.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. A related application of the present invention is Japanese Patent Application No. 61-225944 (Japanese Patent Application Laid-Open No. 63-81970).

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, one of the plurality of island-shaped semiconductor regions electrically isolated from each other has lateral pn
In a method of manufacturing a BiMOS type semiconductor device in which a p-type bipolar transistor is formed and a MOSFET is formed in another island-like p-type semiconductor region, p-type impurities for channel stopper are introduced into the p-type semiconductor region. At the same time, an electric field concentration preventing layer is formed by introducing a p-type impurity so as to be located in the peripheral portion of the collector P layer of the lateral bipolar transistor and to cover a part of the isolation silicon oxide film.

(Operation)

According to the above-described means, the withstand voltage BV _CBO of the bipolar semiconductor element portion can be effectively increased without significantly changing the conventional BiMOS IC manufacturing process, and the above object can be achieved.

〔Example〕

Prior to describing embodiments of the present invention, a bipolar np
A diffusion layer for preventing electric field concentration for increasing the withstand voltage of a bipolar transistor in a BiCMOS IC in which a bipolar transistor such as an n transistor and / or a bipolar pnp transistor and a MOS FET are formed on the same substrate will be described in detail.

When a large reverse voltage is applied between the base and the collector, between the base and the emitter, and between the emitter and the collector of the bipolar transistor, a breakdown phenomenon occurs. This is basically due to the avalanche phenomenon.

When a reverse voltage is applied to the PN junction and the voltage is gradually increased, the reverse current suddenly increases from a certain voltage, a phenomenon called breakdown or breakdown. This phenomenon occurs because the electric field strength in the space charge region becomes extremely large. The mechanism is considered to be avalanche breakdown or zener breakdown.

In avalanche breakdown, electrons in the P-side semiconductor are accelerated by a strong electric field in the space charge region while moving toward the N-side, and the electrons that form covalent bonds in the crystal with their large kinetic energy. Collides with the electron to create electrons that can move, that is, electrons as carriers. Considering the energy band structure, the electrons in the full band are raised to the conduction band by the kinetic energy of the electrons due to the electric field, and the newly generated conduction electrons repeat the same in a high electric field. The number will suddenly increase in the avalanche. This is called the avalanche multiplication effect or the avalanche multiplication effect, and the voltage at which the reverse current increases rapidly is called the avalanche breakdown voltage.

The reverse withstand voltage between the base and the collector and the reverse withstand voltage between the base and the emitter are regulated by this voltage. The avalanche breakdown phenomenon occurs when the maximum electric field intensity in the depletion layer caused by the reverse applied voltage becomes higher than the avalanche electric field intensity of the crystal, due to the multiplication development of the carriers in the depletion layer. This value depends on the material of the single crystal and its impurity concentration (resistivity).

Now, assuming that the multiplication coefficient is M and the ionization coefficient is α, the following equation is obtained, similar to the Townsend equation of gas discharge.

Xm; thickness of depletion layer If this integral value approaches 1, the multiplication factor M becomes infinite, meaning avalanche breakdown. Therefore, the avalanche conditional expression is as follows.

Therefore, assuming the electric field dependence of the ionization coefficient, the shape of the junction is determined, and when the electric field distribution is obtained, the relationship between the crystal impurity concentration and the breakdown voltage can be obtained by using equation (2).

On the other hand, in the base of a bipolar transistor with a planar structure, the electric field is concentrated at the end of the PN junction between the base and the collector due to the bending of the junction surface, and the avalanche breakdown occurs earlier than the flat part of the PN junction, and the breakdown voltage is increased. Lower.

For this reason, the diffusion layer for preventing electric field concentration of the present invention, which is provided to obtain a high withstand voltage, is formed at a bent portion of a PN junction such as between the base and the collector to increase the curvature or reduce the impurity concentration. It has an effect of increasing the avalanche breakdown voltage.

Specifically, a BiCMOS IC in which a bipolar npn transistor and a MOS FET are formed on the same substrate will be described below.

If the diffusion layer for preventing electric field concentration provided for improving the breakdown voltage BV _CBO of the bipolar npn transistor is a p-type layer that is deeper than the p-type base diffusion layer and has a higher impurity concentration than the p-type base diffusion layer, Breakdown voltage BV between collector and base
_CBO can be improved.

Also, the diffusion layer for preventing electric field concentration provided for improving the breakdown voltage BV _CBO of the bipolar npn transistor is a p-type layer which is shallower than the p-type base diffusion layer and has an impurity concentration smaller than that of the p-type base diffusion layer. Thus, the breakdown voltage BV _CBO between the collector and the base can be improved.

In one embodiment of the present invention, a diffusion layer for preventing electric field concentration, that is, a semiconductor layer for reducing electric field concentration is formed by the same process as that for forming a diffusion layer for a channel stopper. The amount of ion implantation of boron impurities into the n-epitaxial layer in the formation of the diffusion layer for preventing electric field concentration is about 2 × 10 ¹⁷ atoms / cm ³ on the surface of the n-epitaxial layer, whereas the p-type base diffusion of the NPN transistor is The amount of ion implantation of boron impurities for forming a layer is 2 × 10 ¹⁸ atoms / cm ³ in the direction of the n-epitaxial layer.

1 to 8 are cross-sectional views at respective steps for explaining a manufacturing process of a reference example for explaining a diffusion layer for preventing electric field concentration according to the present invention.

(1) p as substrate ^- -type silicon substrate 1 is prepared, the ion implantation of the diffusion impurity for the n ⁺ embedded layer 2 and the isolation layer forming the buried p ⁺ layer 3 formed of the PN junction to the surface (FIG. 1). Antimony (Sb) is used to form the n ⁺ buried layer 2, and boron (B) is used to form the p ⁺ layer 3.
, Each using a selective diffusion technique.

(2) The entire surface of the n ⁻ epitaxial layer 4 is formed thick by the epitaxial technique, and the n ⁺ buried layer 2 is embedded.
Diffusing impurities of p ⁺ layer 3 for forming isolation layer
n ^- layer (epitaxial layer) 4 (second
Figure).

(3) Boron (B) is ion-implanted from the surface of the n ^- epitaxial layer 4 and then diffused to form an isolation layer.
By forming the p ⁺ layer 5, the island region I for the bipolar element formation region and the island region II for the CMOS FET element formation region are separated.

Part of the island region II has p for n-channel MOS FET.
The well 6 is formed (FIG. 3).

(4) n ^- silicon nitride film (SiN) 8 for the mask for selective oxidation through the thin silicon oxide film 7 in the epitaxial layer 4 surface, by selectively using the photoresist 9 as a mask for selective etching n ^- It is formed on the surface of the epitaxial layer 4 (FIG. 4).

(5) Photomask 10 for forming a channel stopper around the N-channel MOS FET
And a mask 10 made of photoresist for forming a diffusion layer for preventing electric field concentration around the base of the NPN transistor.
Are formed by the same process. Boron (B) is ion-implanted using the photoresist mask 10 and the silicon nitride film 8 described above as an impurity diffusion mask (FIG. 5).

(6) In this state, selective oxidation is performed to obtain LOCOS (loc
al oxidation of silicon) thick silicon oxide film 1
Form one. At the same time, a p-layer 12 for preventing electric field concentration is formed along the peripheral portion of the thick silicon oxide film 11 having the LOCOS structure in the region I, and the thick LOCOS structure in the peripheral portion of the p-well layer 6 in the region II is formed. A P layer 13 for a channel stopper is formed around the silicon film 11.
Figure).

(7) A gate insulating film for a CMOS FET is formed on the surface of the region II, and a gate electrode 14 is formed on the gate insulating film. Then, n of the region I ^- p diffusion layer serving as a base layer surface
15 is formed by self-alignment, while a source / drain p-layer 16 for a p-channel MOS FET element is formed by self-alignment on the n-layer surface of the region II (FIG. 7).

(8) An n ⁺ layer 17 for the emitter is formed on a part of the base surface of the region I.
Is formed by selective diffusion, and n is formed on the surface of the p well 6 in the region II.
Source and drain n-layers 18 for the channel MOS FET elements are formed in a self-aligned manner (FIG. 8).

(9) As shown in the later ,, Fig. 9, regions I n ⁺
An n ⁺ diffusion layer 19 for taking out a collector contact electrode is formed in an adjacent region sharing the buried layer 2. Finally, passivation film 20 made of SiO ₂ , PSG, etc. formed by CVD
After performing photoetching for forming a contact electrode, an electrode of each element and a wiring 21 are formed through aluminum (Al) vapor deposition and wiring patterning steps to complete a BiCMOS IC.

FIG. 9 is a cross-sectional view of the BiCMOS IC shown in FIGS. 1 to 8 viewed from a different angle from the cross-sectional view of the process. This is performed to illustrate the collector contact portion and the like.

In a BiCMOS IC in which a bipolar npn transistor manufactured in this way and a CMOS FET having an N-channel MOS FET and a p-channel MOS FET coexist, the effect is obtained for the following reasons.

(1) In a bipolar npn transistor, since the p-layer 12 is provided along the periphery of the base-collector junction, the curvature at the surface of the base junction is increased, electric field concentration is eliminated, and the breakdown voltage BV _{CBO of the} bipolar portion is reduced. Current 40V
From 100V to 100V. As a result, a BiCMOS IC and its manufacturing process can be applied to a product having a working voltage of 100 V.

(2) Since the p-layer 12 around the base-collector junction of the bipolar npn transistor is formed simultaneously with the formation of the channel stopper p-layer 12 of the N-channel MOS FET in the CMOS FET, a conventional BiCMOS IC is manufactured. It can be realized only by changing a part of the mask pattern in the process. As a result, the cost can be reduced without complicating the process as a method of manufacturing a semiconductor device.

(3) When a BiCMOS IC is formed by microfabrication, the withstand voltage of the bipolar transistor decreases due to the shallow diffusion layer. However, by providing the diffusion layer for preventing electrolytic concentration of the reference example, the withstand voltage of the bipolar transistor can be increased. Therefore, a semiconductor device with a high withstand voltage can be provided even with a micro-processed BiCMOS IC.

FIG. 10 shows an embodiment of the present invention and is a longitudinal sectional view of a BiCMOS IC in which a lateral pnp transistor and a CMOS FET coexist on one substrate.

In the region I, reference numeral 22 denotes a p diffusion layer serving as a collector of a lateral pnp transistor. An electrolytic concentration preventing p-layer 12 is provided around the collector p-layer 22 so as to cover a part of the isolation silicon oxide film.

23 is a p-diffusion layer serving as an emitter. Reference numeral 24 denotes an n ⁺ diffusion layer serving as a base contact electrode extraction portion.

Region II has p-channel MOS FET and n-channel MOS
FETs are formed, which are the same as those in FIG. 9 described in the first embodiment, and use the same designation symbols.

Electric field concentration preventing p layer 12 around collector p layer in region I
Is formed at the same time as the channel stopper p layer 13 at the periphery of the n-channel MOS FET in the region II.

The effect of improving the withstand voltage in such a semiconductor device is that the provision of the p-layer 12 for preventing electric field concentration reduces the electric field concentration by the p-layer 12, resulting in a semiconductor device having a high withstand voltage structure. ing.

The present invention is not limited to the above embodiment, and can be variously modified without departing from the gist thereof.

In the above embodiment, the bipolar transistor and the CM
BiCMOS ICs with OS FETs formed on the same semiconductor substrate, in which a bipolar transistor is formed with a diffusion layer for preventing electric field concentration to increase the breakdown voltage at the same time as the formation of the diffusion layer for the channel stopper of the CMOS FET of the BiCMOS IC. That is, the case where the formation of the diffusion layer for preventing electric field concentration and the formation of the diffusion device for the channel stopper are performed by the same process has been described. In this case, the shape and the impurity concentration of the diffusion layer for preventing electric field concentration are determined to some extent by the impurity concentration by ion implantation for forming the channel stopper diffusion layer and the diffusion diffusion conditions of the ion-implanted diffusion impurity by heat treatment. Things.

As a specific BiCMOS IC to which the present invention can be applied, a VTR
There are BiCMOS ICs for various electric circuits such as switching regulators for power supply circuits, auto white balance for video cameras, and controllers for floppy disks.

〔The invention's effect〕

The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application.

That is, the present invention relates to a BiMOS IC such as a BiCMOS IC and a method of manufacturing the same, and relates to a bipolar transistor and a MOS FET.
Bipolar np of BiMOS IC formed on the same semiconductor substrate
In order to improve the withstand voltage of a bipolar transistor such as a p-type layer serving as the base of an n-transistor, the electric field is concentrated on the bipolar transistor simultaneously with or separately from the formation of a diffusion layer such as a channel stopper p-type layer in a MOS FET. A diffusion layer for prevention is provided. This makes it possible to improve the withstand voltage of the bipolar semiconductor element without significantly changing the manufacturing process of the BiMOS IC.
S IC can be provided.

[Brief description of the drawings]

1 to 8 show a BiCMOS IC according to a reference example of the present invention.
FIG. 6 is a cross-sectional view of each step of the manufacturing process. FIG. 9 is a completed sectional view of a BiCMOS IC as a reference example of the present invention. FIG. 10 is a cross-sectional view of a BiCMOS IC having a lateral pnp transistor according to one embodiment of the present invention. 1 ... p ^- Si substrate, 2 ... n ⁺ buried layer, 3 ... isolation p ⁺ buried layer, 4 ... epitaxial n ^- Si layer, 5 ... isolation p layer, 6 ... p-well , 7 ... oxide film,
8 silicon nitride film, 9 photoresist, 10 photoresist mask, 11 selective oxide film (LOCOS), 12
... p layer for preventing electric field concentration, 13 ... p layer for channel stopper,
14 ... gate electrode, 15 ... base p layer, 16 ... source
Drain p layer, 17 ... emitter n ⁺ layer, 18 ... source / drain n ⁺ layer.

Claims (1)

(57) [Claims] A lateral pn-type semiconductor region is provided in one of the plurality of island-like semiconductor regions electrically isolated from each other.
In a method of manufacturing a BiMOS type semiconductor device in which a p-type bipolar transistor is formed and a MOSFET is formed in another island-shaped p-type semiconductor region, p-type impurities for channel stopper are introduced into the p-type semiconductor region. In addition, a semiconductor is characterized in that a p-type impurity is introduced to form an electric field concentration prevention layer so as to be located at a peripheral portion of a collector P layer of a lateral bipolar transistor and to cover a part of a silicon oxide film for isolation. Device manufacturing method.