JP2646329B2 - Method for manufacturing multilayer bump connection board - Google Patents

Method for manufacturing multilayer bump connection board

Info

Publication number
JP2646329B2
JP2646329B2 JP5207084A JP20708493A JP2646329B2 JP 2646329 B2 JP2646329 B2 JP 2646329B2 JP 5207084 A JP5207084 A JP 5207084A JP 20708493 A JP20708493 A JP 20708493A JP 2646329 B2 JP2646329 B2 JP 2646329B2
Authority
JP
Japan
Prior art keywords
bump
substrate
tin
circuit pattern
connection board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5207084A
Other languages
Japanese (ja)
Other versions
JPH0745960A (en
Inventor
昌己 木下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Radio Co Ltd
Original Assignee
Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Radio Co Ltd filed Critical Japan Radio Co Ltd
Priority to JP5207084A priority Critical patent/JP2646329B2/en
Publication of JPH0745960A publication Critical patent/JPH0745960A/en
Application granted granted Critical
Publication of JP2646329B2 publication Critical patent/JP2646329B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/368Assembling printed circuits with other printed circuits parallel to each other
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、多層バンプ接続基板の
製造方法に関し、特に熱的履歴を経過しても剥離等の生
じない信頼性の高い多層バンプ接続基板の製造方法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a multi-layer bump connection board, and more particularly to a method of manufacturing a multi-layer bump connection board having high reliability without peeling even after a thermal history.

【0002】[0002]

【従来の技術】従来、この種の多層バンプ接続基板の製
造方法においては、図3に示すように、予め部品を実装
した複数枚の樹脂基板を半田バンプ接続して積層してか
ら、更に熔融温度の低い半田材料を使用して半田バンプ
接続した多層バンプ接続基板が知られている。
2. Description of the Related Art Conventionally, in a method of manufacturing a multilayer bump connection board of this kind, as shown in FIG. 3, a plurality of resin boards on which components are mounted in advance are connected by solder bumps and laminated, and then melted. 2. Description of the Related Art A multilayer bump connection substrate in which solder bumps are connected using a low-temperature solder material is known.

【0003】即ち、図3において、部品を実装した下層
側樹脂基板1に形成した回路パターンの一部である下層
側回路パターン2と中間層側回路パターン21を有する
中間層側樹脂基板4を比較的高い温度の熔融点221℃
の錫銀共晶半田材料を使用して形成したバンプ部分を衝
合し、基板の表面に押圧を加えながら昇温して、高熔融
点回路パターンバンプ接合部5を介して張り合わせる。
That is, in FIG. 3, a comparison is made between a lower-layer circuit pattern 2 which is a part of a circuit pattern formed on a lower-layer resin substrate 1 on which components are mounted and an intermediate-layer resin substrate 4 having an intermediate-layer circuit pattern 21. High melting point 221 ° C
The bump portions formed using the tin-silver eutectic solder material are brought into contact with each other, the temperature is increased while applying pressure to the surface of the substrate, and the substrates are bonded via the high-melting-point circuit pattern bump bonding portion 5.

【0004】更に、中間層側回路パターン22を有する
表面層側樹脂基板6を比較的低い温度の熔融点183℃
の錫銀共晶半田材料を使用して形成したバンプ部分を衝
合し、押圧を加えながら昇温して、半田を再熔融してバ
ンプ接合し張り合わせ、3枚の複合基板を作成する。こ
のような製造方法によれば、下層側樹脂基板1及び表面
層側樹脂基板6に立体的に電気部品を取り付けた高密度
実装基板を得ることができる。
Further, the surface layer side resin substrate 6 having the intermediate layer side circuit pattern 22 is melted at a relatively low temperature of 183 ° C.
The bump portions formed using the tin-silver eutectic solder material are abutted, the temperature is increased while applying pressure, the solder is re-melted, and the bumps are bonded to each other to form three composite substrates. According to such a manufacturing method, it is possible to obtain a high-density mounting substrate in which electric components are three-dimensionally attached to the lower resin substrate 1 and the surface resin substrate 6.

【0005】[0005]

【発明が解決しようとする課題】従来、この種の多層バ
ンプ接続基板は、ヒートサイクル等熱的履歴を経過した
場合、最初に接続した高熔融温度の半田バンプ基板の周
辺部分に位置する接続部分に亀裂を発生し易いという不
具合を有していた。
Conventionally, this kind of multi-layer bump connection board has a connection portion located at a peripheral portion of a high melting temperature solder bump board connected first after a thermal history such as a heat cycle has passed. Had the disadvantage that cracks were easily generated in the steel.

【0006】即ち、熔融点183℃の低温側錫鉛共晶半
田材料を使用して押圧を加えながら昇温しバンプ接合す
る際に、樹脂基板の熱膨脹によって発生した応力が集中
する張り合わせ基板の端面周辺部分に位置する、高温側
の錫銀共晶半田による高熔融点回路パターンバンプ接合
部5が、高温域にさらされるため低い抗張力を示すとと
もに、応力集中現象により高熔融点基板中央領域バンプ
接合部52と比較して結晶が粗大化するという現象を有
していた。この結果、ヒートサイクル等の熱的履歴を加
えた際、張り合わせ基板端部領域の高温側の錫銀結晶半
田バンプ部分は疲労破壊を発生し易いという不具合を有
していた。
That is, when a low-temperature side tin-lead eutectic solder material having a melting point of 183 ° C. is used to increase the temperature while applying pressure to perform bump bonding, stress generated by thermal expansion of the resin substrate is concentrated on the end face of the bonded substrate. The high-melting-point circuit pattern bump bonding portion 5 made of tin-silver eutectic solder on the high-temperature side, which is exposed to a high-temperature region, exhibits a low tensile strength. There was a phenomenon that the crystal became coarser than the portion 52. As a result, when a thermal history such as a heat cycle is added, the tin-silver crystal solder bump portion on the high-temperature side in the end region of the bonded substrate has a problem that fatigue fracture is likely to occur.

【0007】本発明は上記従来技術の課題を解決するよ
うにした多層バンプ接続基板の製造方法を提供すること
を目的とする。
An object of the present invention is to provide a method of manufacturing a multilayer bump connection board which solves the above-mentioned problems of the prior art.

【0008】[0008]

【課題を解決するための手段】本発明は、このような従
来技術の課題を解決するために、回路部分に設けられた
バンプ接合部と回路パターンとをそれぞれ有する複数の
樹脂基板を高熔融点の半田材料を使用して押圧しながら
バンプ接合した後、次に低熔融点の半田材料を使用して
押圧しながらバンプ接合する多層バンプ接続基板の製造
方法において、複数の樹脂基板の端面周辺部分にもバン
プ接合部を設け、複数の樹脂基板の積層接合後、結晶粗
大化した端面周辺部分を切削除去する製造方法を特徴と
する。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, the present invention relates to a method of forming a plurality of resin substrates each having a bump joint provided on a circuit portion and a circuit pattern by using a high melting point. In a method of manufacturing a multilayer bump connection board in which bump bonding is performed while pressing using a solder material of the following, and then bump bonding is performed while pressing using a solder material having a low melting point, peripheral portions of the end surfaces of a plurality of resin substrates are provided. The method is characterized in that a bump bonding portion is also provided, and after laminating and bonding a plurality of resin substrates, a peripheral portion of a crystal-enlarged end face is cut and removed.

【0009】[0009]

【作用】本発明は、複数の樹脂基板の端面周辺部分にバ
ンプ接合部を設け、複数の樹脂基板の積層接合後、結晶
粗大化した端面周辺部分を切削除去する製造方法である
ため、ヒートサイクル等の熱的履歴を加えても、張り合
わせ基板端部領域の高温側の錫銀共晶半田バンプ部分に
疲労破壊が例え発生したとしても、その張り合わせ基板
端部領域の高温側の錫銀共晶半田バンプ部分を切削除去
するので、信頼性の高い多層バンプ接続基板の製造方法
が得られる。
The present invention relates to a manufacturing method in which a bump bonding portion is provided in a peripheral portion of an end face of a plurality of resin substrates, and after laminating and bonding the plurality of resin substrates, a peripheral portion of the crystal-enlarged end face is cut and removed. Even if the thermal history is added, even if fatigue fracture occurs in the tin-silver eutectic solder bump on the high-temperature side of the bonded substrate end region, the tin-silver eutectic on the high-temperature side of the bonded substrate end region Since the solder bumps are removed by cutting, a highly reliable method for manufacturing a multilayer bump connection board can be obtained.

【0010】[0010]

【実施例】以下、本発明の実施例につき図1及び図2を
参照して詳細に述べる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS.

【0011】図1において、コンデンサやIC等の部品
を実装した下層側樹脂基板1に形成した下層側回路パタ
ーン2の一部分及び下層側基板周辺領域バンプ接合パタ
ーン3と、中間層側回路パターン21の一部分及び中間
層側基板周辺領域バンプ接合パターン31を有する中間
層側樹脂基板4とを、比較的高い熔融点221℃の錫銀
共晶合金半田材料を使用して、押圧を加えながら昇温し
て、高熔融点回路パターンバンプ接合部5及び高熔融点
基板周辺領域バンプ接合部51を介して接合する。
In FIG. 1, a part of a lower-layer circuit pattern 2 formed on a lower-layer resin substrate 1 on which components such as a capacitor and an IC are mounted and a bump bonding pattern 3 around a lower-layer substrate and an intermediate-layer circuit pattern 21 are formed. The intermediate layer side resin substrate 4 having a part and the intermediate layer side substrate peripheral region bump bonding pattern 31 is heated while applying pressure using a tin silver eutectic alloy solder material having a relatively high melting point of 221 ° C. Then, bonding is performed via the high melting point circuit pattern bump bonding portion 5 and the high melting point substrate peripheral region bump bonding portion 51.

【0012】中間層側樹脂基板4の中間層側回路パター
ン22の一部分及び中間層側基板周辺領域バンプ接合パ
ターン32と、表面層側樹脂基板6の表面層側回路パタ
ーン23の一部分及び表面層側基板周辺領域バンプ接合
パターン33とを、比較的低熔融点183℃の錫銀共晶
合金の半田材料を用いて、押圧を加えながら昇温して低
熔融点回路パターンバンプ接合部7及び低熔融点基板周
辺領域バンプ接合部71を介して接合し、3枚積層の樹
脂複合基板を完成する。更にルーター加工機等を使用し
て、点線で示す切断除去面8の部分から分離して、基板
の端部周辺の張り合わせバンプ部分を除去する。
A part of the intermediate-layer-side circuit pattern 22 of the intermediate-layer-side resin substrate 4 and the intermediate-substrate-side-substrate peripheral-area bump bonding pattern 32, and a part of the surface-layer-side circuit pattern 23 of the surface-layer-side resin substrate 6 and the surface-layer-side Using a solder material of a tin-silver eutectic alloy having a relatively low melting point of 183 ° C., the temperature is increased while applying pressure to the low-melting point circuit pattern bump bonding section 7 and the low-melting point. The three-layer resin composite substrate is completed by bonding via the point substrate peripheral region bump bonding portion 71. Further, using a router machine or the like, the substrate is separated from the portion of the cut removal surface 8 indicated by the dotted line, and the bonded bump portion around the edge of the substrate is removed.

【0013】このような製造方法によれば、基板の張り
合わせと押圧によって発生する基板相互間の熱膨脹差、
基板の反りの変位量の押圧による平面化等により発生し
た基板端面周辺域への応力の集中と、低温半田材料張り
合わせ時の昇温により発生した高温半田材料の結晶粗大
化領域を切断除去することが可能となる。また、押圧、
昇温を加える際、下層側樹脂基板、中間層側樹脂基板、
表面層側樹脂基板とも、断面構成上Z軸方向となる垂直
面に対して同一領域にバンプ接合部分を設けることによ
り押圧時に均一な加圧条件を与えることが、半田材料の
結晶粗大化を抑制することに寄与する。
According to such a manufacturing method, the difference in thermal expansion between the substrates caused by the bonding and pressing of the substrates,
Concentration of stress in the area around the end face of the board caused by flattening, etc., due to the pressing of the displacement of the board warpage, and cutting and removing the crystal coarse area of the high-temperature solder material caused by the rise in temperature during bonding of the low-temperature solder material. Becomes possible. Pressing,
When increasing the temperature, the lower resin substrate, the intermediate resin substrate,
Both the surface layer side resin substrate and the bump bonding portion are provided in the same area with respect to the vertical plane which is the Z-axis direction in the cross-sectional configuration, so that a uniform pressing condition can be given at the time of pressing, thereby suppressing crystal coarsening of the solder material. To help you.

【0014】図2は、断面構成的均一押圧化を示す断面
説明図で、押圧面に対して中間層側均圧化パターン9と
表面層側均圧化パターン91と低熔融点均圧バンプ接合
部72を介することにより、高熔融点回路パターンバン
プ接合部5の結晶粗大化を抑制することができる。
FIG. 2 is a cross-sectional explanatory view showing the uniform pressing of the cross-sectional structure, in which the intermediate layer side pressure equalizing pattern 9, the surface layer side pressure equalizing pattern 91, and the low melting point pressure equalizing bump bonding to the pressing surface. Through the portion 72, the crystal coarsening of the high melting point circuit pattern bump bonding portion 5 can be suppressed.

【0015】以下、その一実施例について説明する。銅
箔による回路パターンと0.3mm直径の高熔融点基板周
辺領域バンプ接合部を有するFR−4樹脂基板にステン
レススクリーンを使用して錫銀共晶合金半田クレームを
スクリーン印刷し部品実装すると共に半田バンプを作成
する。
An embodiment will be described below. Using a stainless steel screen on a FR-4 resin substrate having a circuit pattern of copper foil and a bump junction of a high melting point substrate having a diameter of 0.3 mm and using a stainless screen, a tin-silver eutectic alloy solder claim is screen printed and components are mounted and soldered. Create a bump.

【0016】更に、銅箔による回路パターンと0.3mm
直径のバンプ接合部を基板の両面に有するFR−4樹脂
基板をピンガイド穴などを介して位置合わせして衝合
し、20Kg/cm2 の押圧を加え、窒素雰囲気中で昇温し
てバンプ接合する。更に銅箔による回路パターンと0.
3mm直径のバンプ接合部を基板の両面及び片面に有する
FR−4樹脂基板に半田スクリーンを介して、錫鉛共晶
合金半田クレームをスクリーン印刷し、リフローを行い
半田バンプを作成する。次に前述のピンガイド穴を介し
て位置合わせして半田バンプ部分を衝合し、20Kg/cm
2 の押圧を加え、窒素雰囲気中で昇温して3枚の樹脂共
有結晶合金を張り合わせる。その後、ルーター加工機を
使用して外形加工を行い、所定の回路部分から基板端部
の応力集中領域となり結晶が粗大化した銀錫共晶合金に
よる周辺のバンプ専用領域を切削除去する。
Further, a circuit pattern made of copper foil and 0.3 mm
FR-4 resin substrates having bump joints with a diameter on both sides of the substrate are aligned and abutted through pin guide holes and the like, pressurized at 20 kg / cm 2 , heated in a nitrogen atmosphere, and bumped. Join. Furthermore, the circuit pattern of copper foil and 0.
A tin-lead eutectic alloy solder claim is screen-printed on an FR-4 resin substrate having a 3 mm-diameter bump joint on both sides and one side of the substrate via a solder screen, and reflowed to form a solder bump. Next, the solder bumps are abutted by positioning them through the above-described pin guide holes, and 20 kg / cm.
The pressure of 2 is applied, and the temperature is raised in a nitrogen atmosphere to bond the three resin co-crystal alloys. Thereafter, external processing is performed by using a router machine, and a peripheral bump-dedicated area made of a silver-tin eutectic alloy having a coarse crystal which has become a stress concentration area at the end of the substrate from a predetermined circuit portion is cut and removed.

【0017】更に、切削除去する基板周辺のバンプ専用
領域は、予め使用する基板構成と熔融点の異なる半田材
料によってバンプ接合し、基板接合面を断面顕微鏡観察
して結晶の粗大化傾向を観察することにより、一定領域
値を決定する。また、基板部分に例えば歪み計により発
生応力を測定し、導出することができる。
Further, a bump-dedicated area around the substrate to be cut and removed is bump-bonded with a solder material having a melting point different from that of the substrate used in advance, and the substrate bonding surface is observed with a cross-sectional microscope to observe the tendency of crystal growth. Thus, a constant area value is determined. Further, the generated stress can be measured and derived from the substrate portion using, for example, a strain gauge.

【0018】この種の手法は多数の部品を実装し多層化
するため、錫銅共晶合金、錫鉛共晶合金、ビスマス/鉛
/錫合金、インジウム/錫合金など多岐にわたる熔融点
の異なる半田材料を使用する構成においても有効であ
る。特に、高温条件下で本実施例で説明した錫銀共晶半
田合金のように機械的伸展性が大きい鉛、インジウムを
多量に含有しない半田材料を高温側に使用した場合には
著しい効果を得ることが可能となる。
In this type of method, a large number of components are mounted and multilayered, so that a wide variety of solders having different melting points such as tin-copper eutectic alloy, tin-lead eutectic alloy, bismuth / lead / tin alloy, and indium / tin alloy are used. It is also effective in a configuration using a material. In particular, a remarkable effect is obtained when a lead material having a large mechanical extensibility, such as a tin-silver eutectic solder alloy described in this embodiment, is used on a high temperature side under a high temperature condition without using a large amount of indium. It becomes possible.

【0019】前述した実施例では、MILSTD883
Dによる低温部−55℃、5分、高温部+125℃、5
分の液相熱衝撃試験で、錫銀共晶合金のみによる3枚バ
ンプ接合基板は、ほぼ3000回サイクル、錫銀共晶合
金と錫鉛共晶合金による従来の実施例によるバンプ接合
基板は、ほぼ1,800回で錫銀共晶合金、バンプ接合
部分に疲労破壊を生じた。本発明の実施例に基づく錫銀
共晶合金による試料は実にほぼ3000回サイクルの耐
性を得た。
In the embodiment described above, MILSTD883
D at -55 ° C for 5 minutes, high temperature at + 125 ° C for 5 minutes
In the liquid phase thermal shock test, the three-sheet bump bonded substrate using only the tin-silver eutectic alloy was subjected to almost 3000 cycles, and the bump bonded substrate according to the conventional example using the tin-silver eutectic alloy and the tin-lead eutectic alloy was: After about 1,800 times, the tin-silver eutectic alloy and the bump joints caused fatigue fracture. The sample made of the tin-silver eutectic alloy according to the embodiment of the present invention actually obtained a resistance of almost 3000 cycles.

【0020】[0020]

【発明の効果】以上述べたように、本発明によれば異な
る熔融点の半田材料を使用してバンプ接合した複数の張
り合わせ基板において、基板端部周辺にバンプ接合専用
の領域を設け、多層化し、該当する一定領域を切削除去
する製造方法であるから、ヒートサイクルなどの熱的履
歴を経過しても剥離等の全くない信頼性の高い多層バン
プ接続基板を製造することが可能となる。
As described above, according to the present invention, in a plurality of bonded substrates bump-bonded by using solder materials having different melting points, a region dedicated to bump bonding is provided around the edge of the substrate to form a multilayer structure. Since this manufacturing method cuts and removes a certain area, it is possible to manufacture a highly reliable multi-layer bump connection substrate without any peeling even after a thermal history such as a heat cycle.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示す概略断面図である。FIG. 1 is a schematic sectional view showing one embodiment of the present invention.

【図2】本発明の他の実施例を示す概略断面図である。FIG. 2 is a schematic sectional view showing another embodiment of the present invention.

【図3】従来の多層バンプ接続基板の製造方法を示す概
略断面図である。
FIG. 3 is a schematic cross-sectional view illustrating a method for manufacturing a conventional multilayer bump connection substrate.

【符号の説明】[Explanation of symbols]

1 下層側樹脂基板 2 下層側回路パターン 21、22 中間層側回路パターン 23 表面層側回路パターン 3 下層側基板周辺領域バンプ接合パター
ン 31、32 中間層側基板周辺領域バンプ接合パタ
ーン 33 表面層側基板周辺領域バンプ接合パタ
ーン 4 中間層側樹脂基板 5 高熔融点回路パターンバンプ接合部 51 高熔融点基板周辺領域バンプ接合部 52 高熔融点基板中央領域バンプ接合部 6 表面層側樹脂基板 7 低熔融点回路パターンバンプ接合部 71 低熔融点基板周辺領域バンプ接合部 72 低熔融点均圧化バンプ接合部 8 切断除去面 9 中間層側均圧化パターン 91 表面層側均圧化パターン
DESCRIPTION OF SYMBOLS 1 Lower layer side resin board 2 Lower layer side circuit pattern 21, 22 Intermediate layer side circuit pattern 23 Surface layer side circuit pattern 3 Lower layer side substrate peripheral area bump joint pattern 31, 32 Middle layer side substrate peripheral area bump joint pattern 33 Surface layer side substrate Peripheral area bump bonding pattern 4 Intermediate layer side resin substrate 5 High melting point circuit pattern bump bonding part 51 High melting point substrate Peripheral area bump bonding part 52 High melting point substrate Central area bump bonding part 6 Surface layer side resin substrate 7 Low melting point Circuit pattern bump joint part 71 Low melting point substrate peripheral area bump joint part 72 Low melting point equalizing bump joint part 8 Cutting removal surface 9 Intermediate layer side equalizing pattern 91 Surface layer side equalizing pattern

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 回路部分に設けられたバンプ接合部と回
路パターンとをそれぞれ有する複数の樹脂基板を高熔融
点の半田材料を使用して押圧しながらバンプ接合した
後、次に低熔融点の半田材料を使用して押圧しながらバ
ンプ接合する多層バンプ接続基板の製造方法において、 前記複数の樹脂基板の端面周辺部分にもバンプ接合部を
設け、前記複数の樹脂基板の積層接合後、結晶粗大化し
た該端面周辺部分を切削除去することを特徴とする多層
バンプ接続基板の製造方法。
A plurality of resin substrates each having a bump bonding portion provided on a circuit portion and a circuit pattern are bump-bonded while pressing using a high-melting-point solder material. In a method of manufacturing a multilayer bump connection board for performing bump bonding while pressing using a solder material, a bump bonding portion is also provided around an end surface of the plurality of resin substrates, and after the plurality of resin substrates are stacked and bonded, crystal coarseness is increased. A method for manufacturing a multilayer bump connection board, characterized by cutting and removing the peripheral portion of the end face.
【請求項2】 請求項1において、前記樹脂基板の各端
面周辺部分が同軸上に積層配列されていることを特徴と
する多層バンプ接続基板の製造方法。
2. The method according to claim 1, wherein peripheral portions of the end faces of the resin substrate are coaxially stacked and arranged.
JP5207084A 1993-07-29 1993-07-29 Method for manufacturing multilayer bump connection board Expired - Fee Related JP2646329B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5207084A JP2646329B2 (en) 1993-07-29 1993-07-29 Method for manufacturing multilayer bump connection board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5207084A JP2646329B2 (en) 1993-07-29 1993-07-29 Method for manufacturing multilayer bump connection board

Publications (2)

Publication Number Publication Date
JPH0745960A JPH0745960A (en) 1995-02-14
JP2646329B2 true JP2646329B2 (en) 1997-08-27

Family

ID=16533937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5207084A Expired - Fee Related JP2646329B2 (en) 1993-07-29 1993-07-29 Method for manufacturing multilayer bump connection board

Country Status (1)

Country Link
JP (1) JP2646329B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6237218B1 (en) * 1997-01-29 2001-05-29 Kabushiki Kaisha Toshiba Method and apparatus for manufacturing multilayered wiring board and multi-layered wiring board
JP6847780B2 (en) * 2017-06-29 2021-03-24 京セラ株式会社 Circuit board and probe card

Also Published As

Publication number Publication date
JPH0745960A (en) 1995-02-14

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