JP2645133B2 - Code error measurement device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital transmission line and a code error measuring device for detecting a code error occurring in a device connected to the transmission line, a digital storage device, or the like.

[Conventional technology]

Such devices include a reading method and a 1-bit shift method. FIG. 3 is a block diagram of a code error measuring device to which the reading method is applied. A shift register 1 is provided, and a code to be measured is input to the shift register 1 through a switch circuit 2. The code to be measured is a maximum long period sequence code (hereinafter referred to as M
(Referred to as a sequence code) has passed through the system to be measured.
The shift register 1 has 23 stages of D-type flip-flops 1-1 to 1-1.
1-23 are connected in series. An exclusive OR circuit 3 is connected between the 18th and 19th stages of the shift register 1 and the 23rd stage, and the output of the exclusive OR circuit 3 is connected to the switch circuit 2 And the exclusive OR circuit 4. The code to be measured is input to the other input terminal of the exclusive OR circuit 4.
By the way, the shift register 1, the exclusive OR circuit 3,
An M-sequence code generation circuit as shown in the equivalent circuit of FIG. This M-sequence code generation circuit complies with CCITT recommendation O.151.
It generates an M-sequence code having a 2 ²³ -1 bit period, and the bit period can be changed by changing the number of stages of the D-type flip-flop. However, the switch circuit 2 is normally connected to the terminal A, and the code to be measured is taken into the shift register 1 in this state. When the switch circuit 2 is switched to the low end at an appropriate time after the code to be measured is fetched and shifted by 23 bits or more, an M-sequence code generation circuit is formed. And generates the same reference M-sequence code. Therefore, when the reference M-sequence code is input to the exclusive OR circuit 4 and the code to be measured is input to the exclusive OR circuit 4 and there is a code error in the code to be measured, the exclusive OR circuit 4 Output an error pulse.

On the other hand, FIG. 6 is a block diagram of a code error measuring device to which the 1-bit shift method is applied, which measures a code error of an mB1C code as a code to be measured. Here, in the mB1C code, m indicates a natural number, B indicates a binary number, and C indicates a replacement bit to be inverted. For example, when the M-sequence code shown in FIG. 4 (a) is converted into a 10B1C code, as shown in FIG. 4 (b), the tenth code J from the code A is replaced and becomes the next code position. Is replaced with the tenth code U from the code L to become the next code position. The measured code is input to the synchronization detection circuit 6 through the exclusive OR circuit 5, and is sent from the synchronization detection circuit 6 to the inhibit gate circuit 7. A clock signal is input to the other end of the inhibit gate circuit 7, and the output of the gate circuit 7 is sent to a reference code generation circuit 8 that generates the same code as the code to be measured. Here, if the phase relationship between the code to be measured and the code generated by the reference code generation circuit 8 at the input terminal of the exclusive OR circuit 5 does not match, the clock signal is changed by 1 until the synchronization is detected by the synchronization detection circuit 6. The bit is inhibited bit by bit and the phase is shifted bit by bit. When the phases match, the synchronization detection circuit 6 stops the inhibit signal. Therefore, if there is a code error in the code to be measured, the exclusive OR circuit 5 outputs an error pulse.

[Problems to be solved by the invention]

However, the devices of the above-described methods have the following problems. First, in a device to which the reading method is applied, the code to be measured is limited to the M-sequence code. For this reason, the mB1C code used for digital transmission using an optical fiber in recent years cannot be measured.

Further, in a device to which the 1-bit shift method is applied, the synchronization pull-in time between the code to be measured and the reference code becomes long. However, has been recommended as according to the CCITT Recommendation No. O · 151 in 139.246Mbit / s or more transmission rates using M-sequence code having a period of 2 ²³ -1, for example in the code example 10B1
When C substitution is performed, 2 ²³ −1, that is, 8388607 and substitution synchronization 11
Is relatively prime, and its cycle is 82246677 bits. Therefore, for example, even if it is assumed that a period of 100 clocks is necessary for the synchronization detection circuit 6 to determine whether or not the period is normal, at 139.264 Mbit / s, the synchronization pull-in time is about 1
There is a problem in practical use because it takes 0 minutes and a waiting time of about 10 minutes is required for each measurement.

Therefore, the present invention provides a simple code error measuring device that can shorten the synchronization pull-in time even with an M-sequence code that has undergone mB1C substitution, thereby shortening the maintenance time and thus reducing the line cost. With the goal.

[Means for solving the problem]

The present invention receives an mB1C code in which the maximum long-frequency sequence code is replaced by C bits every m + 1 bits, and
In a code error measuring device for detecting a code error included in a code, a position of a C bit in a measured mB1C code is detected.
The mB1C synchronization circuit receives the measured mB1C code, and
A code restoration circuit for restoring the 1C code to the maximum long-period sequence code, and a code sequence identical to the maximum long-period sequence and synchronized by reading the maximum long-period sequence code restored by the composite restoration circuit And a reference pattern generation circuit that obtains a reference mB1C code by performing a measured mB1C code conversion on the code sequence with a synchronization signal from the mB1C synchronization circuit, and receives the mB1C code from the reference pattern generation circuit. An error detecting circuit for detecting an error in the code by comparing the mB1C code with the mB1C code.

Further, the present invention provides a code error measuring device which receives an mB1C code in which a maximum long-period sequence code is replaced with C bits every m + 1 bits and detects a code error contained in the mB1C code. An MB1C synchronization circuit for detecting the position of the measured mB1C code, a maximum long-period sequence code generation circuit for taking in a code other than the C bit of the measured mB1C code and generating a maximum long-period sequence code synchronized with the measured mB1C code, and mB1C A replacement circuit that receives the synchronization signal from the synchronization circuit and replaces the maximum-length-period sequence code from the maximum-length-period sequence code generation circuit with C bits for every m + 1 bits of the mB1C code, and becomes a reference replaced by this replacement circuit. This is a code error measuring device that includes an error detection circuit that compares the mB1C code with the received mB1C code to be measured and detects a code error, thereby achieving the above object.

[Action]

With the provision of such means, the code restoration circuit receives the mB1C code and restores the mB1C code to the maximum long-period sequence code, and the reference pattern generation circuit reads the restored maximum long-period sequence code and synchronizes with the mB1C code. The maximum length synchronization sequence code is converted into the mB1C code by synchronizing with the mB1C code by the synchronization signal at the C bit position from the circuit. Then, the mB1C code from the reference pattern generation circuit and the received mB1C code are compared by an error detection circuit to detect a code error.

Also, with the provision of the above means, the maximum long-period sequence code generation circuit taking in a part of the mB1C code generates a maximum long-period sequence code synchronized with the mB1C code, and the reference pattern circuit is generated from the mB1C synchronization circuit. Receiving the C-bit synchronization signal of the maximum length period sequence code from the maximum length period sequence code generation circuit.
Convert to mB1C code. Then, the mB1C code converted by the reference pattern circuit and the received mB1C code are compared by an error detection circuit to detect a code error.

〔Example〕

Hereinafter, a first embodiment of the present invention will be described with reference to the overall configuration diagram of the code error measuring device shown in FIG. The M-sequence code shown in FIG. 4A output from the M-sequence code generation circuit 10 is converted into an mB1C signal as shown in FIG.
The signal is converted into a code, for example, a 10B1C code, sent to the system under test 12, and sent to the code error measuring device 20 through the system under test 12.

Hereinafter, the configuration of the code error measurement device 20 will be described.
The code to be measured from the system under test 12, that is, the 10B1C code, is a code recovery circuit 21, a switch circuit 22, an mB1C (10B1C) synchronization circuit 23.
And sent to the exclusive OR circuit 24. The code restoration circuit 21
It has a function of restoring a 10B1C code into an M-sequence code, and is composed of a shift register 25 and an exclusive OR circuit 26. The shift register 25 and the exclusive OR circuit 26 have the same configuration as that of the M series code generating circuit shown in FIG. 5 in which the D-type flip-flop 1-1 and the exclusive OR circuit 3 are opened. , Shift register 25 has 23 stages D
Type flip-flops are connected in series, and an exclusive OR circuit 26 is connected between the 18th and 19th stages and the 23rd stage. The output terminal of the exclusive OR circuit 26 is connected to the terminal A of the switch circuit 2. mB1C synchronous circuit 23
Takes the mB1C code and detects the position of the C bit contained in the mB1C code, that is, the code shown in FIG.
It has a function of outputting a synchronization signal s synchronized with this position.

On the other hand, 27 is a reference pattern generation circuit,
The M-sequence code restored through the switch circuit 22 is input to 27. Specifically, a switch circuit
The switch circuit 28 has an A terminal connected to the switch circuit 22 and an output terminal connected to a shift register.
Connected to 29. The shift register 29 has a 23-stage D-type flip-flop connected in series similarly to the M-sequence code generation circuit shown in FIG.
An exclusive OR circuit 30 is connected between the stage and the stage.
A one-bit register 31 is commonly connected to the exclusive OR circuit 30 and the lower end of the switch circuit 28, and the lower end of a switch circuit 33 is connected through an inverter 32. The end of the switch circuit 33 is connected to the exclusive OR circuit 30. And this switch circuit
The output terminal 33 is connected to the exclusive OR circuit 24.

The switch circuit 22 is normally connected to the low terminal, and switches to the low terminal when a C-bit synchronization signal is input. The switch circuit 33 is normally connected to the A terminal and switches to the B terminal when a C-bit synchronization signal is input.

Next, regarding the operation of the device configured as described above, 10B1C
The replacement will be described as an example. The M-sequence code output from the M-sequence code generation circuit 10 is subjected to mB1C (10B1C
C) The signal is replaced by a code and input to the system under test 12, and is taken into the code error measuring device 20 through the system under test 12.

When the 10B1C code is taken in this way, the 10B1C code is stored in the shift register 25, the switch circuit 22, and the mB1C (10B1C).
It is sent to the synchronization circuit 23 and the exclusive OR circuit 24. However, an M-sequence code is output from the output terminal of the exclusive OR circuit 26 except that the C bit of the 10B1C code is stored in the 18th or 23rd stage of the D-type flip-flop in the shift register 25. Is done. When the mB1C (10B1C) synchronizing circuit 23 detects the C bit and outputs the synchronizing signal, the switch circuit 22 switches to the end A only when this code is obtained. By the way, at this time, the eleventh shift register 25
The C bit is stored in each of the D-type flip-flops of the stage and the 22nd stage, and the C bit is stored at the low end of each of the D-type flip-flops and the switch circuit 22 of the 18th and 23rd stages. Is appearing. However, since the switch circuit 22 has been switched to the end A at this time, an M-sequence code not including the C bit is sent from the switch circuit 22 to the reference pattern generation circuit 27.

Then, when the switch circuit 28 is switched to the low end at an appropriate time after the M-sequence code is taken into the shift register 29 through the switch circuit 28 and shifted by 23 bits or more, the exclusive OR circuit 30 An M-sequence code having the same content as that of the acquired M-sequence code is generated. At the same time, the M-sequence code is inverted by passing through the 1-bit register 31 and the inverter 32 and sent to the low end of the switch circuit 33. However, when the switch circuit 33 receives the synchronization signal s, it switches to the low end.
The 10B1C code is output and sent to the exclusive OR circuit 24. As a result, the exclusive OR circuit 24 determines the 10B1C code from the system under test 12 and the reference 10B1C from the switch circuit 33.
The codes are compared, and an error pulse is transmitted if an error code is included in the 10B1C code from the system under measurement 12.

Thus, in the first embodiment, the mB1C code is M
Since the M-sequence code was converted to the reference mB1C code by synchronizing with the mB1C code by restoring to the sequence code, the code error was detected by comparing the reference mB1C code with the received mB1C code, Even with the M-sequence code converted into the mB1C code, the reference mB1C code can be obtained in a short time with synchronization. Therefore, a code error generated in the measured system 12 can be detected in a short time using the M-sequence code converted into the mB1C code. As a result, maintenance and management of the system under measurement 12 can be performed in a short time, and the line cost can be reduced.

Next, a second embodiment of the present invention will be described with reference to the block diagram of the code error measuring device shown in FIG. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. The mB1C code from the measured system is sent to the shift register 25 through the switch circuit 40. The output terminal of the exclusive OR circuit 26 is connected to the terminal A of the switch circuit 41. Further, the output terminal of the first stage D-type flip-flop 25-1 of the shift register 25 is connected via the inverter 42. The lower end of the switch circuit 41 is connected. The switch circuit 40 is normally connected to the terminal A, and switches to the terminal B every time the code to be measured becomes C bits by the signal s1 from the 10B1C synchronous circuit 23. Then, at the appropriate time when 23 bits or more are read into the shift register 25, the state constantly switches to the low end.
Also, the switch circuit 41 is normally connected to the terminal A and the synchronization signal s2
In response to this, when the input measured mB1C becomes the C bit, it is switched to the low end.

With such a configuration, a code other than the C bit of the measured mB1C code passes through the end of the switch circuit 40 and
When mB1C is a C bit, the bit restored to M series by the register 25 and the exclusive OR circuit 26 is a shift register
When the signal is taken into the switch 25 and the switch circuit 40 is switched to the low end, an M-sequence code generation circuit is formed through the shift register 25, the exclusive OR circuit 26 and the switch circuit 40, and the exclusive OR circuit 26 A sequence code is output. When the mB1C synchronization circuit 23 detects the C bit in this state, the switch circuit 41 is switched to the low end by the synchronization signal s2. At this time, the mB1C synchronization circuit 23 operates, for example, as shown in FIG.
If a bit block is detected, the shift register
The 25 D-type flip-flops 25-1 output the code J. Accordingly, the code J is inverted by the inverter 42, and the same code is sent to the exclusive OR circuit 24 through the low end of the switch circuit 41. As a result, the reference mB1C code is sent from the switch circuit 41 to the exclusive OR circuit 24, and the exclusive OR circuit 24 receives the mB1C code from the system under measurement 12 and the reference from the switch circuit 41. The mB1C code is compared, and if the mB1C code from the system under measurement 12 contains an error code, an error pulse is transmitted.

As described above, in the second embodiment, an M-sequence code synchronized with the mB1C code is generated by capturing a part of the mB1C code,
And, receiving the synchronization signal s2 from the mB1C synchronization circuit 23, the M-sequence code is converted into a reference mB1C code, and the reference mB1C code is compared with the received mB1C code to detect a code error. The same effects as those of the first embodiment can be obtained, and the configuration can be simpler than that of the first embodiment.

The present invention is not limited to the above embodiments, and may be modified without departing from the gist thereof. In each of the above embodiments, a description has been given of an example of a period of 2 ²³ -1. However, the present invention is not limited to this and may be changed to an M sequence code having a period of 2 ^N -1.

〔The invention's effect〕

As described above in detail, according to the present invention, a simple code error measuring device that can shorten the synchronization pull-in time even with an M-sequence code subjected to mB1C substitution, thereby shortening maintenance time and reducing line cost. Can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a code error measuring device according to the present invention, FIG. 2 is a block diagram showing a second embodiment of the device of the present invention, and FIG. FIG. 4 (a) is a schematic diagram of an M-sequence code, FIG. 4 (b) is a schematic diagram of an mB1C code, FIG. 5 is a schematic diagram of an M-sequence generation circuit, FIG. 1 is a configuration diagram of a code error measuring device to which a conventional one-bit shift method is applied. 10 ... M-sequence code generation circuit, 11 ... mB1C code generation circuit,
12 ………………………………………………………………………………………………………………………………………………………………………………………………………………………. 27: Reference pattern generation circuit, 29: Shift register, 31: 1-bit register, 32: Inverter, 40, 41: Switch circuit, 4
2 …… Inverter.

Claims (2)

(57) [Claims] 1. An mB1C code in which a maximum long-period sequence code is replaced by C bits every m + 1 bits, and the measured mB1C
In a code error measuring device for detecting a code error included in a code, an mB1C synchronizing circuit (23) for detecting a position of a C bit in the measured mB1C code, and receiving the measured mB1C code in response to the measured mB1C code. And a code restoration circuit (21) for restoring the maximum length period sequence code to the maximum length period sequence code, and by reading the maximum length period sequence code restored by the code restoration circuit, the same sequence as the maximum long period sequence is obtained and synchronization is obtained. Get the code string,
A reference pattern generation circuit (27) for obtaining the reference mB1C code by performing the measured mB1C code conversion on the code sequence by the synchronization signal from the mB1C synchronization circuit, and an mB1C code from the reference pattern generation circuit. The received mB
A code error measuring device comprising: an error detection circuit (24) for detecting a code error by comparing with a 1C code. 2. A code error measuring device for receiving an mB1C code obtained by replacing a maximum long-period sequence code with C bits every m + 1 bits and detecting a code error contained in the mB1C code, wherein the C bit in the mB1C code is An MB1C synchronizing circuit (23) for detecting the position of the measured mB1C code, and a maximum long-period sequence code generator for taking in a code other than the C bits of the measured mB1C code and generating a maximum long-period sequence code synchronized with the measured mB1C code Circuit (2
And a replacement circuit (41, 26) which receives the synchronization signal from the mB1C synchronization circuit and replaces the longest-period sequence code from the longest-period sequence code generation circuit with C bits every m + 1 bits for the mB1C code. 42), and an error detection circuit (24) for detecting a code error by comparing the received mB1C code to be measured with the reference mB1C code replaced by the replacement circuit. Error measurement device.