JP2633568B2 - Structure where electronic circuits are arranged - Google Patents

Structure where electronic circuits are arranged

Info

Publication number
JP2633568B2
JP2633568B2 JP62165744A JP16574487A JP2633568B2 JP 2633568 B2 JP2633568 B2 JP 2633568B2 JP 62165744 A JP62165744 A JP 62165744A JP 16574487 A JP16574487 A JP 16574487A JP 2633568 B2 JP2633568 B2 JP 2633568B2
Authority
JP
Japan
Prior art keywords
housing
electronic
circuit
predetermined
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62165744A
Other languages
Japanese (ja)
Other versions
JPS649695A (en
Inventor
安弘 片岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP62165744A priority Critical patent/JP2633568B2/en
Publication of JPS649695A publication Critical patent/JPS649695A/en
Application granted granted Critical
Publication of JP2633568B2 publication Critical patent/JP2633568B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明電子回路が配置された構造体を以下の項目に従
って説明する。
DETAILED DESCRIPTION OF THE INVENTION A structure on which an electronic circuit of the present invention is arranged will be described in accordance with the following items.

A.産業上の利用分野 B.発明の概要 C.背景技術 D.発明が解決しようとする問題点 E.問題点を解決するための手段 F.実施例 a.電子回路が配置された構造体の構造[第1図、第2
図] b.電子回路が配置された構造体の製造工程[第3図] G.発明の効果 (A.産業上の利用分野) 本発明は新規な電子回路が配置された構造体に関す
る。詳しくは、所謂チップ型の電子回路、即ち、表面に
接続端子を備えた電子部品と該電子部品の接続端子が接
続され所定の配線パターンを為す略箔状の導体とから成
る電子回路が配置された構造体に関するものであり、絶
縁性の積層板等の特別な基板部材を用いなくても所定の
電子機器等に必要な電子回路を設けることができると共
に、回路の実装密度を向上させることができるようにし
た新規な電子回路が配置された構造体を提供しようとす
るものである。
A. Industrial applications B. Summary of the invention C. Background art D. Problems to be solved by the invention E. Means for solving the problems F. Embodiment a. Structure in which electronic circuits are arranged [FIG. 1, FIG.
Figure] b. Manufacturing process of structure in which electronic circuit is arranged [FIG. 3] G. Effect of the Invention (A. Industrial Application Field) The present invention relates to a structure in which a new electronic circuit is arranged. Specifically, a so-called chip-type electronic circuit, that is, an electronic circuit including an electronic component having a connection terminal on the surface and a substantially foil-shaped conductor connected to the connection terminal of the electronic component and forming a predetermined wiring pattern is arranged. It is possible to provide an electronic circuit necessary for a predetermined electronic device or the like without using a special substrate member such as an insulating laminated board, and to improve a circuit mounting density. It is an object of the present invention to provide a structure in which a new electronic circuit is arranged.

(B.発明の概要) 本発明電子回路が配置された構造体は、表面に接続端
子が設けられた電子部品と所定の配線パターンをなす導
体とを備え、合成樹脂製の筺体の複数の壁部にまたがっ
て配置され、前記筺体の壁部の表面に固着される導体
と、前記壁部内に埋め込まれ、前記導体の一方の面の所
定箇所にその接続端子が半田付けされる第1の電子部品
群と、前記導体の他方の面の所定箇所にその接続端子が
半田付けされ、前記筺体の内面上に装着される第2の電
子部品群とから成ることにより、特別な基板部材を用い
なくても必要な回路を設けることができると共に回路の
実装密度を向上させることができるようにしたものであ
る。
(B. Summary of the Invention) A structure in which an electronic circuit of the present invention is arranged includes an electronic component having connection terminals on its surface and a conductor forming a predetermined wiring pattern, and a plurality of walls of a synthetic resin housing. A conductor fixed to the surface of the wall of the housing, and a first electronic component embedded in the wall and having its connection terminal soldered to a predetermined location on one surface of the conductor. By using a component group and a second electronic component group whose connection terminal is soldered to a predetermined position on the other surface of the conductor and mounted on the inner surface of the housing, a special substrate member is not used. However, it is also possible to provide necessary circuits and improve the packaging density of the circuits.

(C.背景技術) 電子回路が配置された構造体は、一般に、各種の電子
部品を導体で接続することにより形成される。
(C. Background Art) A structure in which electronic circuits are arranged is generally formed by connecting various electronic components with conductors.

そして、今日の電子回路が配置された構造体は、上記
導体を所定の絶縁性表面、例えば、所謂積層板の表面に
所定の配線パターンを為す状態で表面的に形成すると共
に上記配線パターンの所定の箇所に所定の電子部品を装
着することにより回路基板として構成されるのが一般的
である。
In a structure in which today's electronic circuits are arranged, the conductor is formed on a predetermined insulating surface, for example, a surface of a so-called laminated board in a state where a predetermined wiring pattern is formed, and at the same time, a predetermined wiring pattern is formed. Is generally configured as a circuit board by mounting a predetermined electronic component at the location.

(D.発明が解決しようとする問題点) ところで、このような回路基板は、その電子回路を電
子機器等に設けられる他の構成要素とは別に独立して取
り扱うことができるという利点はあるが、その反面、回
路基板を適当な支持部材、例えば、シャーシや基板保持
用のラックあるいは筺体壁等に保持せしめる必要がある
ので、この保持のために何らかの保持手段を用いること
が必要になり、その分電子機器等の構造は複雑化し、あ
るいは形状が大きくなり、また、コスト高になるという
問題がある。
(D. Problems to be Solved by the Invention) By the way, such a circuit board has an advantage that its electronic circuit can be handled independently of other components provided in an electronic device or the like. On the other hand, it is necessary to hold the circuit board on a suitable support member, for example, a chassis or a rack for holding the board, or a housing wall, so that it is necessary to use some kind of holding means for this holding. There is a problem that the structure of the electronic components becomes complicated, the shape becomes large, and the cost increases.

そして、上記した回路基板の保持は、その基板をシャ
ーシや筺体壁にねじ止めしたり、あるいは基板の側縁部
をラック等の係合部に係合せしめることによって為され
るので、ねじを挿通するための孔を形成したり上記係合
を為すためのスペースを基板に設けておく必要があり、
このスペースが回路基板における実装密度を低下させる
ことになるという問題がある。
Since the above-described holding of the circuit board is performed by screwing the board to a chassis or a housing wall or by engaging a side edge of the board with an engaging portion such as a rack, the screw is inserted. It is necessary to provide a space on the substrate for forming a hole for making
There is a problem that this space reduces the mounting density on the circuit board.

更に、近時の電子機器等は益々小型化されてきている
ため、その筺体内部の空間がかなり小さくなっており、
従って、回路基板の配置についての設計が非常にやり難
くなってきている。
Furthermore, since electronic devices and the like have recently been increasingly miniaturized, the space inside the housing has been considerably reduced.
Therefore, it has become very difficult to design the layout of the circuit boards.

そして、回路基板に装着されている電子部品には、通
常、環境に対する保護手段、即ち、熱や塵埃あるいは異
物の接触等に対する保護手段が講じられていない状態で
基板に設けられているので、一般に、耐環境特性やその
動作についての信頼性が低くなり易いという問題があ
り、また、回路基板にその回路形成面を被覆するような
保護部材を設けると、回路基板の形状が著しく大型化
し、重量も増してしまうという別の問題が生じることに
なる。
The electronic components mounted on the circuit board are usually provided on the board in a state where no means for protecting against the environment, that is, no means for protecting against contact of heat, dust, or foreign matter, is provided on the board. In addition, there is a problem that the reliability of environmental resistance characteristics and its operation is likely to be low. Also, if a protective member is provided on the circuit board to cover the circuit forming surface, the shape of the circuit board becomes extremely large, and the weight becomes large. Another problem arises.

そして、回路基板は、その製造工程上の制約により、
電子回路を三次元的に、即ち、屈曲した面や凹凸がある
面あるいは互いに向きの異なる複数の平面に連続して形
成することが極めて困難であるため、どうしても平面的
に大きくなり易く、また、平面的形状を小さくするため
には複数の回路基板に分けて構成することを余儀なくさ
れるという問題がある。
And the circuit board, due to restrictions in its manufacturing process,
Since it is extremely difficult to form an electronic circuit three-dimensionally, that is, it is extremely difficult to continuously form a curved surface, a surface having irregularities, or a plurality of planes having different directions, it is inevitably easily enlarged in a planar manner, In order to reduce the planar shape, there is a problem that it is necessary to divide the circuit board into a plurality of circuit boards.

(E.問題点を解決するための手段) そこで、本発明電子回路が配置された構造体は、上記
した様々な問題点を解決するために、表面に接続端子が
設けられた電子部品と所定の配線パターンをなす導体と
を備え、合成樹脂製の筺体の複数の壁部にまたがって配
置され、前記筺体の壁部の表面に固着される導体と、前
記壁部内に埋め込まれ、前記導体の一方の面の所定箇所
にその接続端子が半田付けされる第1の電子部品群と、
前記導体の他方の面の所定箇所にその接続端子が半田付
けされ、前記筺体の内面上に装着される第2の電子部品
群とから成るようにしたものである。
(E. Means for Solving the Problems) Therefore, in order to solve the various problems described above, the structure in which the electronic circuit of the present invention is arranged is an electronic component having connection terminals provided on the surface thereof. A conductor that is arranged over a plurality of walls of a synthetic resin housing and is fixed to the surface of the wall of the housing; and a conductor that is embedded in the wall and embedded in the wall. A first electronic component group whose connection terminal is soldered to a predetermined position on one surface;
The connection terminal is soldered to a predetermined location on the other surface of the conductor, and the second electronic component group is mounted on the inner surface of the housing.

従って、本発明電子回路が配置された構造体によれ
ば、電子回路が配置された構造体を構成している導体及
び電子部品は所定の筺体に支持されるので、特別な基板
部材を用いなくても電子機器等に必要な回路を設けるこ
とができると共に、その電子回路の筺体への支持は当該
筺体の成形工程において為されるので、特別な支持作業
を行なう必要がなく、また、電子回路を筺体に支持せし
めるための特別な支持手段も必要なく、しかも、電子回
路の形態を当該筺体の外面の形態の中で自由に選ぶこと
ができ、三次元的な形態とすることもできる。
Therefore, according to the structure in which the electronic circuit of the present invention is arranged, the conductors and electronic components constituting the structure in which the electronic circuit is arranged are supported by a predetermined housing, so that a special substrate member is not used. In addition, a circuit necessary for an electronic device or the like can be provided, and since the supporting of the electronic circuit on the housing is performed in a molding process of the housing, there is no need to perform a special supporting operation. There is no need for a special support means for supporting the housing on the housing, and the form of the electronic circuit can be freely selected from among the forms of the outer surface of the housing.

(F.実施例) 以下に、本発明電子回路が配置された構造体の詳細を
添付図面に示した実施例に従って説明する。
(F. Example) Hereinafter, details of the structure in which the electronic circuit of the present invention is arranged will be described with reference to the example shown in the accompanying drawings.

尚、図面に示した実施例は、電子回路を筺体壁に埋込
状に設けた場合のものである。
The embodiment shown in the drawings is a case where the electronic circuit is provided in a state of being embedded in the housing wall.

(a.電子回路が配置された構造体の構造)[第1図、第
2図] 1は所定の動作機能を有する電子回路が配置された構
造体であり、該構造体は、接続端子がケースの表面に位
置した各種所定の電子部品と該電子部品の接続端子が接
続され所定の配線パターンを為す導体と筺体壁とから成
る。
(A. Structure of Structure Having Electronic Circuit Arranged) [FIGS. 1 and 2] Reference numeral 1 denotes a structure having an electronic circuit having a predetermined operation function, and the structure has connection terminals. It comprises various predetermined electronic components located on the surface of the case, conductors to which connection terminals of the electronic components are connected to form a predetermined wiring pattern, and a housing wall.

2は、電子機器の筺体であり、合成樹脂により形成さ
れている。そして、筺体2を構成している2つの部分筺
体3及び4の一方3の2つの壁部5、6、例えば、背面
壁と底面壁とが連続する角部、即ち、他の所定の機構と
干渉し合うことが比較的少ない部分に電子回路が配置さ
れている。
Reference numeral 2 denotes a housing of the electronic device, which is formed of a synthetic resin. Then, two wall portions 5 and 6 of one of the two partial housings 3 and 4 constituting the housing 2, for example, a corner portion where the back wall and the bottom wall are continuous, that is, with another predetermined mechanism. The electronic circuit is arranged in a portion where the interference is relatively small.

7、7、・・・は導電性を有する材料により略箔状に
形成された導体であり、これら導体7、7、・・・は所
定の配線パターンを有すると共に、前記2つの壁部5、
6の表面5a、6aに固着されている。
Are conductors formed in a substantially foil shape from a conductive material. These conductors 7, 7,... Have a predetermined wiring pattern and have the two wall portions 5, 7,.
6 are fixed to the surfaces 5a and 6a.

8、8、・・・及び8′、8′、・・・はリードレス
タイプの電子部品、いわゆるチップ部品であり、所定の
電子デバイスチップが封入されたモールドケース9、
9、・・・、9′、9′、・・・の両端部の外表面もし
くは側面部にそれぞれ複数の接続端子10、10、・・・、
10′、10′、・・・が形成されて成る。
, And 8 ′, 8 ′,... Are leadless type electronic components, so-called chip components, and a molded case 9, in which a predetermined electronic device chip is enclosed.
, 9 ′, 9 ′,..., A plurality of connection terminals 10, 10,.
.. Are formed.

そして、これら電子部品8、8、・・・及び8′、
8′、・・・の一方の群を為すもの8、8、・・・は前
記壁部5、6の表面5a、6a寄りの位置に埋め込まれた状
態でその接続端子10、10、・・・が前記導体7、7、・
・・の一方の面7a、7a、・・・、即ち、上記表面5a、6a
に露出していない方の面の所定の箇所に半田付けされて
おり、また、他方の群を為す電子部品8′、8′、・・
・はその接続端子10′、10′、・・・が導体7、7、・
・・の他方の面7b、7b、・・・、即ち、壁部5、6の表
面5a、6aに露出している方の面の所定の箇所に半田付け
されている。
And these electronic components 8, 8, ... and 8 ',
, Which form one group of 8 ′,..., Are buried at positions near the surfaces 5a, 6a of the walls 5, 6, and their connection terminals 10, 10,. Are the conductors 7, 7,.
..One surface 7a, 7a,..., That is, surface 5a, 6a
Are soldered to predetermined portions of the surface that is not exposed to the other, and electronic components 8 ', 8',.
Are connection terminals 10 ', 10',... Are conductors 7, 7,.
.. Are soldered to predetermined portions of the other surfaces 7b, 7b,..., That is, the surfaces exposed to the surfaces 5a, 6a of the walls 5, 6.

尚、図示を省略してあるが、導体7、7、・・・の接
続端部には構造体1と他の回路との間を接続するための
接続手段が設けられている。
Although not shown, a connection means for connecting the structure 1 and another circuit is provided at a connection end of the conductors 7, 7,....

(b.電子回路が配置された構造体の製造工程)[第3
図] 第3図は上記した構造体1の製造工程の一例を(A)
から(F)へ順を追って示すものであり、以下、この
(A)乃至(F)に示すところに従って電子回路が配置
された構造体1の製造工程を説明する。
(B. Manufacturing process of the structure on which the electronic circuit is arranged) [Third
FIG. 3 shows an example of a manufacturing process of the above-described structure 1 (A).
From (F) to (F), and the manufacturing process of the structure 1 in which the electronic circuits are arranged in accordance with (A) to (F) will be described below.

(A)先ず、適宜な仮基板11の一方の面に前記導体7、
7、・・・の材料となる導電箔12を設ける。この導電箔
12は予めメッキ形成された所謂電解銅箔あるいは延圧銅
箔等を仮基板11に貼着しても良いし、あるいは仮基板11
に直接メッキすることによって設けても良い。
(A) First, the conductor 7 is provided on one surface of an appropriate temporary substrate 11.
The conductive foil 12 which becomes the material of 7, ... is provided. This conductive foil
12 may be a pre-plated so-called electrolytic copper foil or rolled copper foil or the like may be attached to the temporary substrate 11, or the temporary substrate 11
May be provided by direct plating.

尚、仮基板11はある程度の可撓性を有するものであれ
ば、その材料が特に限定されることは無いが、導電箔12
からの剥離を比較的容易に行なうことができるものを用
いることが望ましい。
The material of the temporary substrate 11 is not particularly limited as long as it has a certain degree of flexibility.
It is desirable to use a material that can be relatively easily peeled off.

(B)次に、上記導電箔12を必要な部分を残してエッチ
ング処理する。即ち、例えば、導電箔12に前記所定の配
線パターンを為すエッチングレジストを設け、その状態
で導電箔12をエッチングして上記導電箔12のうち上記エ
ッチングレジストが設けられた部分以外の部分を溶解
し、その後でエッチングレジストを除去する。
(B) Next, the conductive foil 12 is subjected to an etching process while leaving necessary portions. That is, for example, an etching resist for forming the predetermined wiring pattern is provided on the conductive foil 12, and in that state, the conductive foil 12 is etched to dissolve portions of the conductive foil 12 other than the portion where the etching resist is provided. Then, the etching resist is removed.

これにより、仮基板11に所定の配線パターンを有する
導体7、7、・・・が形成される。
Thus, the conductors 7, 7,... Having a predetermined wiring pattern are formed on the temporary substrate 11.

(C)そこで、このように形成された導体7、7、・・
・の一方の面7aに前記した電子部品8、8、・・・を装
着する。この装着は電子部品8、8、・・・の接続端子
10、10、・・・を導体7、7、・・・の所定の箇所に半
田付けすることにより行なう。
(C) Then, the conductors 7, 7,.
The electronic components 8, 8,... Are mounted on one surface 7a. This mounting is a connection terminal for the electronic components 8, 8,.
Are soldered to predetermined portions of the conductors 7, 7,....

しかして、仮基板11を基板とする回路13が構成され
る。
Thus, a circuit 13 using the temporary substrate 11 as a substrate is configured.

(D)そして、このように構成された回路13を所定の成
形用金型14、15にセットする。即ち、14、15は前記一方
の部分筺体3を合成樹脂によって成形するための一対の
金型であり、16はこれら成形用金型14と15の突合面14
a、15aが互いに突き合わせられることによって画成され
るキャビティ、即ち、部分筺体3と同じ形状を有する空
間であり、回路13はその仮基板11が一対の成形用金型1
4、15の一方14の突合面14aにぴったり接触した状態でセ
ットされる。従って、この状態において、回路13の導体
7、7、・・・はキャビティ16の厚み方向における一方
の内面に沿って位置され、電子部品8、8、・・・は上
記内面から突出するように位置される。
(D) Then, the circuit 13 configured as described above is set in predetermined molding dies 14 and 15. That is, 14 and 15 are a pair of molds for molding the one partial housing 3 with synthetic resin, and 16 is an abutting surface 14 of these molding dies 14 and 15.
a, 15a are cavities defined by abutting each other, that is, a space having the same shape as the partial housing 3, and the circuit board 13 includes a temporary substrate 11 and a pair of molding dies 1
It is set in a state in which it is exactly in contact with the butting surface 14a of one of the four 14 and 15. Therefore, in this state, the conductors 7, 7, ... of the circuit 13 are located along one inner surface in the thickness direction of the cavity 16, and the electronic components 8, 8, ... project from the inner surface. Is located.

(E)そこで、上記キャビティ16に所定の溶融樹脂を射
出する。これによって部分筺体3が成形されると共に、
該部分筺体3に電子部品8、8、・・・が埋込状に位置
され、また、導体7、7、・・・が部分筺体3の壁部
5、6の表面5a、6aに位置されることになる。
(E) Then, a predetermined molten resin is injected into the cavity 16. Thereby, the partial housing 3 is formed,
The electronic components 8, 8,... Are embedded in the partial housing 3, and the conductors 7, 7,... Are positioned on the surfaces 5a, 6a of the walls 5, 6 of the partial housing 3. Will be.

尚、キャビティ16内に射出されて来る溶融樹脂の射出
圧の大きさによっては、電子部品8、8、・・・が仮基
板11から外れてしまう惧れがある場合は、回路13を成形
用金型14、15にセットする前に、例えば、略クリーム状
の適当なダンパー材17を電子部品8、8、・・・がその
中に埋め込まれるように仮基板11に塗布して該ダンパー
材17を固化あるいは半固化しておけば良い。
If there is a possibility that the electronic components 8, 8,... May come off the temporary substrate 11 depending on the magnitude of the injection pressure of the molten resin injected into the cavity 16, the circuit 13 is used for molding. Before setting in the molds 14 and 15, for example, a suitable cream-like damper material 17 is applied to the temporary substrate 11 so that the electronic components 8, 8,. 17 may be solidified or semi-solidified.

(F)そして、このように成形された部分筺体3を成形
用金型14、15から取り出して仮基板11を剥離する。
(F) Then, the partial housing 3 thus formed is removed from the molding dies 14 and 15, and the temporary substrate 11 is peeled off.

これにより、導体7、7、・・・の他方の面7b、7b、
・・・が部分筺体3の表面5a、6aに露出されることにな
る。
Thereby, the other surfaces 7b, 7b of the conductors 7, 7,.
Are exposed on the surfaces 5a and 6a of the partial housing 3.

しかして、導体7、7、・・・の他方の面7b、7b、・
・・の所定の箇所に前記電子部品8′、8′、・・・を
装着する。
Thus, the other surfaces 7b, 7b,... Of the conductors 7, 7,.
Attach the electronic components 8 ', 8',... To predetermined locations.

これによって、電子回路が配置された構造体1が完成
することになる。
As a result, the structure 1 on which the electronic circuit is arranged is completed.

(G.発明の効果) 以上に記載したところから明らかなように、本発明電
子回路が配置された構造体は、表面に接続端子が設けら
れた電子部品と所定の配線パターンをなす導体とを備
え、合成樹脂製の筺体の複数の壁部にまたがって配置さ
れ、前記筺体の壁部の表面に固着される導体と、前記壁
部内に埋め込まれ、前記導体の一方の面の所定箇所にそ
の接続端子が半田付けされる第1の電子部品群と、前記
導体の他方の面の所定箇所にその接続端子が半田付けさ
れ、前記筺体の内面上に装着される第2の電子部品群と
から成るようにしたものである。
(G. Effects of the Invention) As is clear from the above description, the structure on which the electronic circuit of the present invention is arranged is composed of an electronic component having connection terminals on the surface and a conductor forming a predetermined wiring pattern. And a conductor that is disposed across a plurality of walls of the synthetic resin housing and is fixed to the surface of the wall of the housing, and is embedded in the wall and is disposed at a predetermined position on one surface of the conductor. A first electronic component group to which connection terminals are soldered, and a second electronic component group to which the connection terminals are soldered to predetermined positions on the other surface of the conductor and are mounted on the inner surface of the housing It is made to become.

従って、本発明電子回路が配置された構造体によれ
ば、電子回路が配置された構造体を構成している導体及
び電子部品は所定の筺体に支持されるので、特別な基板
部材を用いなくても電子機器等に必要な回路を設けるこ
とができると共に、その電子回路の筺体への支持は当該
筺体の成形工程において為されるので、特別な支持作業
を行なう必要がなく、また、電子回路を筺体に支持せし
めるための特別な支持手段も必要がない。
Therefore, according to the structure in which the electronic circuit of the present invention is arranged, the conductors and electronic components constituting the structure in which the electronic circuit is arranged are supported by a predetermined housing, so that a special substrate member is not used. In addition, a circuit necessary for an electronic device or the like can be provided, and since the supporting of the electronic circuit on the housing is performed in a molding process of the housing, there is no need to perform a special supporting operation. There is no need for special support means for supporting the housing on the housing.

また、電子回路を筺体に支持せしめるための特別な支
持手段を必要としないので、筺体の所定の部分の全体に
回路を配置することができ、従って、実装密度を高める
ことができる。
In addition, since no special supporting means for supporting the electronic circuit on the housing is required, the circuit can be arranged over the entire predetermined portion of the housing, so that the mounting density can be increased.

そして、本発明電子回路が配置された構造体によれ
ば、その導体を三次元方向へ延びる状態で配置すること
ができるので、電子回路の形態が平面的なものに限定さ
れることがなく、当該筺体の外面の形態の中で由に選ぶ
ことができる。従って、屈曲している面や凹凸のある面
にも電子回路を設けることができる。
According to the structure in which the electronic circuit of the present invention is arranged, the conductor can be arranged in a state of extending in the three-dimensional direction, so that the form of the electronic circuit is not limited to a planar one. It can be freely selected in the form of the outer surface of the housing. Therefore, an electronic circuit can be provided on a bent surface or a surface having irregularities.

【図面の簡単な説明】[Brief description of the drawings]

図面は本発明電子回路が配置された構造体の実施の一例
を示すものであり、第1図は筺体の一部を切断して示す
断面図、第2図は筺体壁の一部を切断して示す要部斜視
図、第3図は電子回路が配置された構造体の製造工程を
(A)から(F)へ順を追って示す工程図である。 符号の説明 1……構造体、2……筺体、5、6……壁部、5a、6a…
…壁部の表面、7……導体、7a……導体の一方の面、7b
……導体の他方の面、8……第1の電子部品、8′……
第2の電子部品、10、10′……接続端子、13……電子回
The drawings show an embodiment of a structure in which the electronic circuit of the present invention is arranged. FIG. 1 is a cross-sectional view showing a part of a casing, and FIG. 2 is a sectional view showing a part of a casing wall. FIG. 3 is a process diagram showing the manufacturing process of the structure on which the electronic circuit is arranged in order from (A) to (F). DESCRIPTION OF SYMBOLS 1 ... structure, 2 ... housing, 5, 6 ... wall, 5a, 6a ...
... wall surface, 7 ... conductor, 7a ... one side of conductor, 7b
... the other surface of the conductor, 8 ... the first electronic component, 8 '...
Second electronic component, 10, 10 '... connection terminal, 13 ... electronic circuit

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】表面に接続端子が設けられた電子部品と所
定の配線パターンをなす導体とを備え、合成樹脂製の筺
体の複数の壁部にまたがって配置され、 前記筺体の壁部の表面に固着される導体と、 前記壁部内に埋め込まれ、前記導体の一方の面の所定箇
所にその接続端子が半田付けされる第1の電子部品群
と、 前記導体の他方の面の所定箇所にその接続端子が半田付
けされ、前記筺体の内面上に装着される第2の電子部品
群と から成る電子回路が配置された構造体。
An electronic component having a connection terminal provided on a surface thereof and a conductor forming a predetermined wiring pattern, the electronic component being disposed over a plurality of walls of a synthetic resin housing, and a surface of the wall of the housing. A first electronic component group embedded in the wall and having its connection terminal soldered to a predetermined location on one surface of the conductor; and a first electronic component group embedded at a predetermined location on the other surface of the conductor. A second electronic component group to which the connection terminals are soldered and which is mounted on the inner surface of the housing;
JP62165744A 1987-07-02 1987-07-02 Structure where electronic circuits are arranged Expired - Fee Related JP2633568B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62165744A JP2633568B2 (en) 1987-07-02 1987-07-02 Structure where electronic circuits are arranged

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62165744A JP2633568B2 (en) 1987-07-02 1987-07-02 Structure where electronic circuits are arranged

Publications (2)

Publication Number Publication Date
JPS649695A JPS649695A (en) 1989-01-12
JP2633568B2 true JP2633568B2 (en) 1997-07-23

Family

ID=15818253

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62165744A Expired - Fee Related JP2633568B2 (en) 1987-07-02 1987-07-02 Structure where electronic circuits are arranged

Country Status (1)

Country Link
JP (1) JP2633568B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050029247A (en) * 2002-08-05 2005-03-24 코닌클리즈케 필립스 일렉트로닉스 엔.브이. An electronic product, a body and a method of manufacturing
JP5359550B2 (en) * 2009-05-22 2013-12-04 オムロン株式会社 Manufacturing method of electronic component mounting apparatus

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59140492U (en) * 1983-03-10 1984-09-19 三菱電機株式会社 Electronics
JPH0326689Y2 (en) * 1984-11-19 1991-06-10

Also Published As

Publication number Publication date
JPS649695A (en) 1989-01-12

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