JP2628744B2 - Subcode playback device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sub-code reproducing apparatus of a rotary head type digital audio tape recorder (hereinafter, referred to as "R-DAT").

[Conventional technology]

FIG. 3 shows the arrangement of the head, drum and magnetic tape of the R-DAT. In the figure, the magnetic head A (502A) and the magnetic head B (502B) are at an angle of 180 ° to each other on the drum (501).
Attached to. 2000r.pm for magnetic tape (504)
Wound at a winding angle of 90 ° around a drum (501) with a diameter of 30 mm rotating at a angle of 90 °. Tracks are sequentially formed and recorded.

FIG. 4 is a diagram showing a magnetization pattern when a signal is recorded on the magnetic tape (504). In the figure, the arrow (50
6) is the running direction of the magnetic tape (504), the arrow (507) is the scanning direction of the magnetic head, and the magnetization pattern (track) (50
5A) and (505B) are recorded by A magnetic head (502A) and B magnetic head (502B), respectively.

FIG. 4 shows one track (here, (505)
A) shows only the signal recording area.
PCM area (510) for recording audio signals and subcode area for recording additional information (subcode) such as time information
1, 512 (512) and 1 in PCM area (510)
Each of the 28 blocks and the subcode areas 1, 2 (511) and (512) is composed of 8 blocks.

FIG. 5 shows the PCM area (510) and the subcode area (51).
1) and (512) are diagrams showing the structure of one block constituting a block synchronization signal (600) of the first byte and identification signals of the second and third bytes (hereinafter referred to as "ID code"). ) And an ID section (610) in which a block address is recorded, and parity check data of the fourth byte (611).
And a data portion (620) of the 5th to 36th bytes. The data portion (620) records an audio signal in the PCM area (510), and the subcode area (511). , (512), subcode data is recorded.

Since the present invention relates to subcode playback,
Hereinafter, the configuration of the sub-code of the R-DAT will be further described.

The sub-codes include the elapsed time within the music (P-time), the absolute time (A-time), and the like, which are each transmitted as one pack P.

Figure 6 is shows the configuration of one of the packed, one the packed consists of 8 bytes from D ₀ to D _7, at the beginning of the first byte D _0, corresponding to the contents of the the packed 4 By adding a bit item code, 16 types of items can be identified. The subcode data is the first byte D ₀
Recorded from the second half of the 4-bit to the seventh byte D ₆ of the eighth byte D ₇ is The parity determined by is recorded. This parity D ₇ can reliability checkstop of the packed data.

Figure 7 is a sub-code area 1 (511) is a diagram showing a signal arrangement of the packed data P ₀ to P ₇ which is recorded in the (512). The subcode areas 1 and 2 are composed of 16 blocks as described above, and block addresses from 0 to 15 are added to the ID part (610) of each block.

In FIG. 7, the block addresses are represented by 2n, 2n + 1, where n is an integer from n = 0 to 7. Also, P ₀
To P ₆ represents a the packed data, the redundancy signal for error correction in the packed P ₇ is recorded. Therefore, in two blocks, 7
Subcodes up to a pack can be recorded. One track is provided with a subcode recording area for 7 × 8 = 56 packs. Since the subcode is identified by the 16 types of item codes as described above, an arbitrary pack can be multiplex-recorded an arbitrary number of times using a recording area for 56 packs.

FIG. 8 is a block circuit diagram of a conventional sub-code reproducing apparatus for retrieving desired code data by retrieving an item code when reproducing a sub-code recorded in the above format. In the figure, (201) is a terminal for inputting data reproduced by a magnetic head, (202) is a demodulation circuit, (203) is a memory having an 8-bit input / output terminal, (204) is a parity data circuit for packet data,
(205) is a selector, (206) is an input terminal of an item designation code, (207) is a match detection circuit, (208) is a memory control circuit, (209) is a pack data output terminal, and (210) is an item search start. A signal input terminal (211) is a clock generation circuit.

 Next, the operation will be described.

The reproduction data input from the terminal (201) is demodulated to the original data by the demodulation circuit (202) and then written to the memory (203). At this time, the clock for data writing and the ID information are transmitted from the demodulation circuit (202) to the memory control circuit (20).
8), and the memory control circuit (208) controls the sub-code data of all the blocks of the sub-code areas 1 and 2 to be written into the areas corresponding to the predetermined memory addresses, as shown in FIG. I do. The numbers from 0 to 55 in the figure indicate the area numbers of the packs (for a total of 56 packs).
The shaded portion indicates the area where the error-correcting redundant signal is written.

Next, an operation of extracting desired packet data from the packet data stored in the memory (203) by designating an item code from the terminal (206) will be described. An item search start signal is input from the terminal (210), and the clock generation circuit (211) is set to the search mode. In this mode, the first area of each pack is sequentially assigned from the area number 0 of the pack.
Reads the item code contained in byte D ₀ from the memory (203), repeat until it matches whether the checkstop matches the item code specified by the coincidence detection circuit (207) es. When the coincidence detection circuit (207) detects a match, switch to read mode clock generating circuit (211) from the search mode, through a sequential selector (205) from the first byte D ₀ of the packed which matched the item terminal At the same time as outputting the pack data from (209), the pack data is simultaneously input to the parity check circuit (204). Last byte D ₇ input B by a selector (205), i.e. Pariteichietsuku result is output from the selected terminal (209).

Processing such as time display is performed by a microcomputer or the like (not shown) based on the check result and the pack data.

The above operation is performed by the clock generation circuit (211) and the memory control circuit (208), which sequentially generate memory addresses for performing a packet search, and generate timing clocks for each circuit.

[Problems to be solved by the invention]

Since the conventional sub-code reproducing apparatus is configured as described above, for example, from the input of an item search start signal to the start of item detection and the output of desired pack data, for example, the last pack (pack area) In the case where 56) is the desired packet data, it takes a long time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to obtain a subcode reproducing apparatus having a short search time.

[Means for solving the problem]

The subcode reproducing apparatus according to the present invention has 16
Provide memory areas corresponding to each type of item code,
When the playback pack data is written to the memory, the item code of the pack is detected and written to the memory area corresponding to the item code, and at the same time, the parity check of the pack data is performed.If the parity check result is OK, Thereafter, even if pack data of the same item code is input, writing to the memory is prohibited, and at the time of reading, pack data in a memory area corresponding to a desired item code is read.

[Action]

Since the memory according to the present invention has a memory area corresponding to the item code, it does not require an item search time at the time of reading a pack, thereby realizing a higher processing speed.

In addition, writing of pack data to the area corresponding to the item code of the memory is prohibited after rewriting the pack data for which the parity check result is OK. Will not be written to.

(Example of the invention)

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, (1) is a latch for holding an item code of reproduced packet data, (2) is a memory control circuit, (3) is a designated item code and an output from the latch (1). A selector for selecting, (4) a flag register for storing the parity check result of the reproduced packet data for each of the 16 types of items, and a memory (203) having an area for storing the packet data of 0 to 15 items. .

FIG. 2 shows the addresses of the pack data storage area in the memory (203). The x address corresponds to the byte number in one pack, and the y address is the item number of the pack data.
It corresponds to.

By generating these x and y addresses in the memory control circuit (2) and supplying them to the memory (203), desired pack data in the reproduced data can be written to a predetermined memory area. That is, the demodulation circuit (202) extracts the first 4-bit item code of the first byte of the packet data and outputs it to the latch (1), and the item code of the reproduced packet data is held in the latch (1). The memory control circuit (2) receives the output of the latch (1), supplies a corresponding y address to the memory (203), and counts the clock output from the demodulation circuit (202) for each byte. The x address is sequentially advanced by counting the x address by the memory (20).
3), and the sequentially input packet data is stored in the memory (2).
Write to 03). At the same time as the write operation to the memory (203), the packet data is transferred to the parity check circuit (204).
The parity check is input to the flag register (4), and the result of the parity check is input to the flag register (4).

The flag register (4) is provided for each item code from 0 to 15, and stores the parity check results inputted after the initial setting. The item code of the latch (1) is supplied to the flag register (4) via the selector (3), and any one of the flag registers 0 to 15 corresponding to the item code is selected, and the result of the parity check is OK. In the case of (
In “parity OK”, the flag register of the item code is reset. Then, in order to prevent data from being written again in the area in the memory (203) where the parity OK packet data has been written,
It is controlled by the memory control circuit (2). That is, when the output of the flag register (4) specified by the item code stored in the latch (1) is in a reset state, writing to the memory (203) is prohibited. This prohibition operation prevents the parity OK packet data from being rewritten to the parity NG packet data.

As a result of the operation of writing the reproduction pack data as described above, only the parity OK pack data is stored in the area corresponding to each item code in the memory (203). The memory area in which the pack data is not recorded and the memory area in which the parity data of the parity check NG are recorded can be identified because the flag register (4) corresponding to the item code is not reset.

Next, when reading desired packet data from the memory (203), a desired item code is inputted from the terminal (206) as in the conventional case. In this embodiment, since the address of the memory (203) and the number of the flag register (4) corresponding to the item code are known in advance, there is no need to perform the conventional item search.

That is, the memory control circuit (2) reads desired 8-byte packet data from the memory (203) by changing the x address while holding the y address corresponding to the designated item, and from the terminal (209). Output. To output the parity check result, select the selector (20
By selecting and outputting the B input of 5), a parity check result corresponding to the designated item can be output. Since the parity check result has already been passed, sending the parity check result to the beginning of the output data enables processing such as not receiving the parity NG data on the receiving side, thus reducing the processing load on the receiving side Also useful.

In the above embodiment, the memory address for writing the pack data is determined by the x address and the y address. However, if the area where the pack data is recorded and the address correspond one-to-one with each item code, another address is specified. It may be a method.

Further, in the above-described embodiment, the reproducing apparatus has been described. However, needless to say, the same effect can be obtained by applying the present invention to the reproducing circuit section of the recording / reproducing apparatus.

[Effects of the Invention] As described above, according to the present invention, when writing reproduced packet data to the memory, the item of the packet data is determined, and the packet data is written to a predetermined memory area based on the item. Since the parity check is also performed, there is an effect that a DAT subcode reproducing apparatus capable of reading out desired packet data from the memory in a short time is obtained.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a subcode reproducing apparatus according to one embodiment of the present invention, FIG. 2 is a diagram showing a memory map of this embodiment, and FIG. 3 is a positional relationship between a head, a drum and a tape of an R-DAT. FIG. 4 is a diagram showing a DAT magnetization pattern and a signal recording area on one track, FIG. 5 is a diagram showing a signal configuration in one block, and FIG. 6 is a diagram showing a subcode area. FIG. 7 shows the data structure of one pack and the position of the item code. FIG. 7 shows the structure of one or two packs of a subcode area recorded in one track. FIG. 8 shows the conventional subcode reproducing apparatus. FIG. 9 is a diagram showing a memory map of the conventional device. (1) Latch, (2) Memory control circuit,
(3), (205) ... selector, (4) ... flag register, (202) ... demodulation circuit, (203) ... memory, (20)
4) ... Pari-tech check circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Continuation of the front page (56) References JP-A-64-49193 (JP, A) JP-A-63-247977 (JP, A) JP-A-63-96774 (JP, A) JP-A-62-232768 (JP) JP-A-61-190755 (JP, A) JP-A-64-31555 (JP, U)

Claims (1)

(57) [Claims] 1. An information code, an item code indicating a classification of information data, and an error generated from the information data and the item code in a partial area of a track formed obliquely to a longitudinal direction of the tape. A sub-code reproducing apparatus that reproduces the above-mentioned pack data from a magnetic tape on which n pieces of pack data consisting of redundant signals are recorded using m rotary heads, and stores the pack data for each item code. A predetermined memory area, error detecting means for detecting an error in the reproduced pack data, storage means for storing an error detection result of the pack data for each item code, and When writing to memory, write the pack data to the memory area corresponding to the item code of the pack. In the area of the memory in which the pack data of the item code once determined to be error-free is written, means for prohibiting the subsequent writing, and when reading the pack data from the memory, the area corresponding to the desired item code is read. Means for reading pack data stored from a memory area to be read.