JP2627664B2 - Progressive scan converter - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an interpolation signal necessary for progressive scan conversion,
In particular, the present invention relates to a progressive scanning conversion device which performs low noise (noise reduction) and vertical contour compensation (enhancement) and outputs an adaptive interpolation signal.

2. Description of the Related Art In response to the demand for higher image quality of television receivers, IDTV, E
Systems such as DTV have been developed or realized. In these systems, sequential scanning (non-interlaced scanning) in which the developing signal and the interpolation signal are alternately scanned at a double scanning speed is performed, and therefore, it is necessary to create an interpolation signal. This interpolated signal is created by inter-line interpolation or inter-field interpolation. Inter-line interpolation or inter-field interpolation is appropriately switched according to the presence or absence of image movement and the degree thereof, or the mixing of video signals between lines and between fields. It is preferred to change the ratio. Further, it is desired that the interpolation signal be created so as to minimize flicker (line flicker).

On the other hand, in order to improve the sharpness of an image, not only horizontal contour enhancement but also vertical contour enhancement is required. Since the interpolation signal is a kind of average value signal, it works in the direction of blurring the contour, so vertical contour compensation is an indispensable technique.

The vertical contour enhancement is generally performed by adding an inter-field difference signal or an inter-frame difference signal to an original signal, but it is necessary to consider the degree of motion of an image. The level of the difference signal is related to the contour in the vertical direction when the motion is small or almost nonexistent. However, when the motion is large, the difference component due to the motion becomes large.

On the other hand, in the reproduction process of the video signal, the noise reduction process of the video signal is also indispensable. The basic idea of the noise reduction circuit is to take advantage of the fact that the video signal has a strong vertical correlation with adjacent horizontal scanning lines, extract the noise component by taking the difference signal between lines, and include this noise component In other words, the difference signal is subtracted from the original video signal.
Since the noise reduction processing is a kind of averaging processing, the density of the image is averaged in the vertical direction, and a clear boundary may be blurred. Therefore, a vertical contour compensation circuit for enhancing the vertical contour is required.

SUMMARY OF THE INVENTION As described above, a noise reduction circuit indispensable for video signal processing, a circuit capable of generating an interpolation signal capable of preventing occurrence of flicker, and a vertical contour compensation circuit complementary to these circuits However, providing these circuits separately complicates the circuit configuration.

The present invention achieves noise reduction of an input video signal, creates an interpolation signal from the noise-reduced video signal in consideration of the motion of the image, and can prevent the occurrence of flicker. It is an object of the present invention to provide a progressive scan conversion device capable of performing appropriate vertical contour compensation according to the requirements and further simplifying the circuit configuration as much as possible.

Means for Solving the Problems A progressive scan converter according to the present invention comprises a 262H delay circuit for delaying a noise-reduced input video signal by 262H, a 263H delay circuit for delaying a noise-reduced input video signal by 263H, and the 263H delay circuit. The output signal of the 262H delay circuit is switched between the output signal of the 262H delay circuit and the output signal of the 263H delay circuit during one field scan, and the output signal of the 263H delay circuit is selected during the other field scan. A first subtraction circuit that calculates a difference between an input video signal and an output signal of the switching circuit and outputs a first inter-field difference signal; and a first subtraction circuit that is output from the first subtraction circuit. A first non-linear processing circuit for performing a predetermined non-linear processing for noise reduction on one inter-field difference output signal; and an output signal of the first non-linear processing circuit from an input video signal. A second subtraction circuit that calculates and outputs the noise-reduced video signal as a noise-reduced video signal, a 1H delay circuit that delays the noise-reduced video signal output from the second subtraction circuit by 1H, and a noise reduction output from the second subtraction circuit. A first averaging circuit which receives a video signal and a signal delayed by 1H by the 1H delay circuit and outputs an average signal of these input signals; an output signal of the 263H delay circuit and the first averaging circuit A third subtraction circuit for calculating a difference from an output signal of the circuit to output a second inter-field difference signal, a noise-reduced current video signal output from the second subtraction circuit, and an input from the 263H delay circuit Done26
Inputting a 3H delay signal and a 1H delay signal output from the 1H delay circuit, and mixing the noise low band current video signal and the 1H delay signal according to a comparison result of levels of these three input signals. An interpolation filter circuit for generating and outputting an adaptive interpolation signal according to the formula (1), and a second contour difference signal outputted from the third subtraction circuit for vertical contour compensation according to the level of the inter-field difference signal. A non-linear processing circuit for performing a predetermined non-linear processing, and an output signal of the second non-linear processing circuit is added to the adaptive interpolation signal to generate an interpolation signal which has been subjected to noise reduction and vertical contour compensation. It is characterized by comprising a first addition circuit for outputting.

The interpolation filter circuit detects a level difference between the noise low band current video signal and the noise low band 263H delay signal and a level difference between the noise low band 263H delay signal and the noise low band 1H delay signal, respectively. A comparison processing circuit, a decoding circuit for converting an output signal of the comparison processing circuit into a mixed control signal, and the level of the noise-reduced current video signal and the noise-reduced 1H delay signal controlled by the mixed control signal given from the decoding circuit. It comprises a mixing circuit that outputs an adaptive interpolation signal by mixing at a predetermined ratio according to the difference.

The first inter-field difference signal output from the first subtraction circuit is supplied to the first non-linear processing circuit,
, A non-linear process for noise reduction according to the level of the inter-field difference signal is applied, and then the image signal is subjected to noise reduction by being subtracted from the input video signal in the second subtraction circuit.

The noise-reduced current video signal, the noise-reduced 1H delay signal in the same field as the noise reduction signal, and the noise-reduction 263H delay circuit in the previous field are input, and the level difference between these signals (that is, the image Movement)
By changing the mixing ratio of the noise-reduced current video signal and the 1H delay signal, an adaptive interpolation signal with reduced noise (without using the 263H delay signal) is created. This adaptive interpolation signal is subjected to vertical contour enhancement processing. That is, a signal (third average signal) representing the average value of the noise-reduced current video signal and the noise-reduced 1H delay signal is created, and the third average signal and the noise-reduced 263H delay signal are generated. , A second inter-field difference signal is obtained. The second inter-field difference signal is applied to the second non-linear processing circuit, and a non-linear process for vertical contour enhancement according to the level of the second inter-field difference signal is performed. By adding the output signal of the second non-linear processing circuit to the adaptive interpolation signal, an adaptive interpolation signal with vertical contour compensation is finally obtained.

Embodiment 1 FIG. 1 shows a progressive scan conversion apparatus including a noise reduction circuit (a noise reducer utilizing two-line field correlation) and a vertical contour compensation circuit. This progressive scanning converter applies vertical contour compensation to both a current video signal and an interpolation signal created from the current video signal, and has a feature that a part of the circuit can be shared.

 First, the noise reduction circuit will be described.

The input video signal (the luminance signal Y after Y / C separation) is supplied to the first subtraction circuit 1 and the second subtraction circuit 2.

The output signal of the second subtraction circuit 2 is supplied to the interpolation filter circuit and the vertical contour emphasizing circuit as a noise-reduced video signal as will be described later, and a 262H delay circuit (field memory) 4 for delaying one field period. (H is one horizontal scanning period). 262H delay circuit 4
The signal delayed by 262H is applied to the addition circuit 8, the TB terminal of the switching circuit 6, and the 1H delay circuit (line memory) 5. 1H
The signal applied to delay circuit 5 is further delayed by 1H and output (263H delay), and the TA terminal of switching circuit 6 and addition circuit 8
Respectively. A 263H delay circuit is configured by the 262H delay circuit and the 1H delay circuit.

A 1/21 coefficient unit 9 is connected to the next stage of the adding circuit 8. A second averaging circuit is constituted by the adding circuit 8 and the 1/2 coefficient unit 9, whereby the video signal delayed by 262 H
A signal representing an arithmetic mean value with the video signal delayed by 3H is supplied to a fourth subtraction circuit 14 described later. This arithmetic average signal is on a scanning line exactly corresponding to the development signal as shown in FIG.

The switching circuit 6 switches one of the scanning screens based on the switching control signal.
The TA terminal and the TB terminal are switched for each field, and a signal (a video signal delayed by 263H or 262H) selected according to the switching is fed back to the first subtraction circuit 1
Given to.

In the subtraction circuit 1, the output video signal of the switching circuit 6 is subtracted from the input video signal, and a difference signal X is output during the first field. This inter-field difference signal X is provided to the first nonlinear processing circuit 3. First nonlinear processing circuit 3
Detects the degree of vertical movement of the image according to the magnitude of the input inter-field difference signal X and outputs a noise (noise) component Y included in the inter-field difference signal according to the detected degree of movement. I do. The specific configuration of the first nonlinear processing circuit 3 will be described later in detail, but this circuit 3 has characteristics as shown in FIG. 14, FIG. 17, or FIG.

The noise component signal Y output from the first non-linear processing circuit 3 is supplied to the second subtraction circuit 2 and the noise component is subtracted from the input video signal, so that a video signal with reduced noise components is obtained.

Next, a vertical contour compensation circuit for the current video signal will be described.

A third inter-field difference signal for vertical contour compensation is created by a fourth subtraction circuit 14. The subtraction circuit 14 receives the noise-reduced video signal output from the second subtraction circuit 2 and the arithmetic average signal of the 262H delay signal and the 263H delay signal output from the second averaging circuit. I have entered
A third inter-field difference signal is created by subtracting the arithmetic mean signal from the noise reduced video signal.

The third inter-field difference signal output from the fourth subtraction circuit 14 is input to a third non-linear processing circuit 16 via a second low-pass filter 15 (this inter-field difference signal is
Represented by X _0). The second inter-field difference signal X ₀ (specifically its high-frequency signal of 15.7 kHz) vertical high-frequency component of the image contains. The low-pass filter 15 allows a signal of about 0.5 MHz or 1 MHz or less to pass therethrough, thereby removing a high-frequency component in the horizontal direction (which is generally high-frequency noise) from the third inter-field difference signal. In this way, only the signal components in the vertical direction are input to the third nonlinear processing circuit 16. An example of a specific configuration of the nonlinear processing circuit 16 will also be described later. For example, the nonlinear processing circuit 16 has characteristics as shown in FIG. 22, and detects the degree of vertical movement based on the level of an input signal. A vertical contour compensation signal component to be enhanced is output accordingly.

The output signal Z of the third nonlinear processing circuit 16 is then provided to a second adding circuit 17. This addition circuit 17 is also supplied with the output video signal of the second subtraction circuit 2 in which the above-mentioned noise has been reduced, and a video signal which has been subjected to vertical contour compensation by adding a vertical contour compensation signal component to this video signal. (This is called a current video signal with respect to the interpolation signal) is output from the adding circuit 17. That is, the rounding of the waveform generated in the vertical direction by the noise reduction processing is compensated by the vertical contour enhancement.

Next, a circuit for generating an adaptive interpolation signal for progressive scan conversion and its vertical contour compensation circuit will be described.

The video signal reduced in noise by the second subtraction circuit 2 is
1H delay circuit 21 and adder circuit 22 are provided.
The output signal of the 1H delay circuit 21 is provided to the addition circuit 22. Therefore, the noise reduction video signal and its
The 1H delay signal is added, and the signal is further multiplied by 1/2 by the 1/2 coefficient unit 23 to generate a line interpolation signal. Adder circuit
22 and a 1/2 coefficient unit 23 constitute a first averaging circuit.

The line interpolation signal output from the 1/2 coefficient unit 23 is supplied to a third subtraction circuit 24. This subtraction circuit 24 has a 263H delay signal (previous field signal) output from the 1H delay circuit 5.
Is input, and the second inter-field difference signal of the interpolation signal is obtained by subtracting the line interpolation signal from the 263H delay signal. Since the line interpolation signal is the arithmetic mean of the current video signal and the 1H delay signal, as shown in FIG.
It will be on the scan line exactly corresponding to the delay signal.

The interpolation filter circuit 28 includes a noise-reduced current video signal output from the second subtraction circuit 2 (represented by a symbol A) and a 1H delay signal output from the 1H delay circuit 21 (represented by a symbol C). 263) output from the 1H delay circuit 5
An H-delay signal (represented by the symbol B) is input.
The interpolation filter circuit 28 detects a level difference between the signals A and B and a level difference between the signals B and C, as will be described in detail later.
According to the detection result, the signals A and C are mixed at a predetermined ratio (the signal B is not mixed) to generate and output an adaptive interpolation signal. This adaptive interpolation signal is supplied to the first adding circuit 27.

A second inter-field difference signal of the interpolation signal output from the subtraction circuit 24 is supplied to a second nonlinear processing circuit 26 via a first low-pass filter 25. These filters 25,
The processing circuit 26 has the same configuration as the filter 15 and the processing circuit 16 described above. The vertical contour compensation component signal of the interpolation signal output from the nonlinear processing circuit 26 is input to the addition circuit 27 and added to the adaptive interpolation signal provided from the interpolation filter circuit 28. In this way, the addition circuit 27 outputs an adaptive interpolation signal with reduced noise and vertical contour compensation.

The specific configuration of the interpolation filter circuit 13 will be described with reference to FIGS.

FIG. 4 shows a schematic configuration of the interpolation filter circuit 28. The interpolation filter circuit 28 is a comparison processing and decoding circuit
31 and a mixing circuit 32. The current video signal A, the 263H delay signal B and the 1H delay signal C are provided to the comparison and decoding circuit 31. In the mixing circuit 32, the developed video signals A and 1H
And a delay signal C. The comparing and decoding circuit 31 generates control signals S1 and S2 for controlling the changeover switch in the mixing circuit 32, which will be described in detail later, based on the comparison processing of these input signals A, B and C, and outputs the control signals to the mixing circuit 32. give.

The comparison and decoding circuit 31 includes a comparison processing circuit and a decoding circuit. Details of the comparison processing circuit are shown in FIG. 5, and details of the decoding circuit are shown in FIG.

In FIG. 5, the comparison processing circuit includes two subtraction circuits 33 and 34.
Contains. One subtraction circuit 33 subtracts the current video signal A from the input 263H delay signal B, and outputs the result as an absolute value circuit.
Give to 35. Therefore, a signal having a level represented by | B−A | is output from the absolute value circuit 35. The other subtraction circuit 34
Then, the 1H delay signal C is subtracted from the 263H delay signal B, and the result is given to the absolute value circuit 36 to be converted into an absolute value.
This circuit 36 outputs a signal representing the level of | B-C |.

The comparison processing circuit further comprises seven comparators 37L, 37M, 37S, 38L,
Includes 38M, 38S and 39. Comparators 37L, 37M and 37
Reference levels R _L , R _M , and R _S are provided to the positive input terminal of S, respectively. R _L > R _M > R _S. These comparators
Output signals | B−A | of the absolute value circuit 35 are given to negative input terminals of 37L, 37M and 37S. Therefore, the absolute value circuit
If the output | B−A | of 35 is smaller than the reference level R _S , the outputs D _AS , D _AM and D _AL of all the comparators 37S, 37M and 37L go to H level. This state is called “equivalent”. When the level of the signal | B−A | is between the reference levels R _S and R _M , only the output _DAS becomes L level, and the other outputs D _AM and D _AL maintain H level. This state is called “small difference”. When the level of signal | B−A | is between reference levels _RM and _RL , outputs _DAS and D _AM
Becomes L level, and the output _DAL keeps H level. This state is called “difference”. Level of signal | B-A | is reference level
When _RL is exceeded, all comparators 37L, 37M, 37S
Outputs D _AL , D _AM , and D _{AS go} to L level. This state is called “large difference”. The above comparison operation is summarized in a table in FIG. In this table, the H level of the output signal is represented by 0, and the L level is represented by 1.

Similarly, reference levels R _L , R _M , and R _S are provided to the positive input terminals of the comparators 38L, 38M, and 38S, respectively. The output signal | B−C | of the absolute value circuit 36 is input to the negative input terminals of these comparators 38L, 38M, 38S. These comparators 38L, 38M, 38
S is the input signal | B-C | level reference level R _L of, R _M, R _S and respectively compared, the output signal D _CL representing the comparison result, D _CM, D _CS
Is output. The output signal D _CL, D _CM, D _CS also collectively shown in Figure 6.

The comparator 39 compares the magnitudes of the absolute difference signal | B−A | and | B−C |. When | B−A | <| B−C |, the comparator 39 is at the H level (represented by the sign 0). ), And outputs the signal T1 at the L level (represented by reference numeral 1) when the signal T1 is reversed. This signal T1 is not particularly used in the decoding circuit of this embodiment (FIG. 7).

The output D of the comparator 38S the AND circuit 40 and the output D _AS of the comparator 37S
When both _CS are at the H level, that is, when the signals | B−A |
When | B−C | is small (when there is almost no difference between the signals A, B, and C), the signal T2 of the H level (represented by code 0)
Is output.

Output signals D _AL , D _AM , D _AS , T 2, DC _L , D _CM , and D _CS representing the above-mentioned comparison results of the comparison processing circuit (FIG. 5) are given as input signals to the decoding circuit shown in FIG. Can be This decoding circuit, based on the input signal, switches the switching control signals S1 (1 bit) and S2
(Composed of two bits, MSB and LSB). As shown in FIG. 7, EX-OR circuits 41a, 41b, 41c and
It is configured by a combination of OR circuits 42a and 42b.

The operation of the decoding circuit, that is, the relationship between the input signal and the output signal is shown in the form of a table in FIG.
FIG. 8 also shows an output mixed signal (output adaptive interpolation signal of the interpolation filter circuit 28) of the mixing circuit 32 whose mixing ratio is controlled by the signals S1 and S2. Here, the mixed signal expressed in the form of a fraction represents the mixed state of the input signals A and C in the mixing circuit 32. For example, (A + C) / 2 represents the arithmetic mean of input signals A and C.

In FIG. 8, the mixing ratio of input signals A and C is
It is determined according to the difference between C and signal B. That is, of the input signals A and C, the one with the smaller difference from the signal B is used with a larger mixing ratio.

For example column D _AS = 0 and D _CS = 0 the top, the difference signal
| B−A | and | B−C | are both very small (equivalent), in which case the current video signal A and the 1H delay signal C
Is output as an adaptive interpolation signal (line interpolation). Also, D _AS = 0 and D _CS =
In the case of 1, there is almost no difference between the signals A and B (equal) and there is a little difference between the signals B and C (small difference). The current video signal A having almost no difference is output as an interpolation signal. D _AS = 1, D _CS = 0
In this case, the 1H delay signal C having almost no difference from the signal B is output as an interpolation signal.

The concept is the same when the difference between the signals A and B and the difference between the signals B and C increase. For example, D _AL = D _AM = 0
And when D _CL = D _CM = 1, the signal A is conversely D _AL = D _AM
= 1 and D _CL = D signal C in the case of _CM = 0 is adopted as the interpolation signal. D _AL = D _AM = 0, D _AS = 1, and
_{D CL = 0, D CM =} D CS = mixing ratio of the signal A in the case of 1 3/4,
The mixing ratio of the signal C is 1/4.

As described above, the smaller of the difference between the previous field and the 263H delay signal B of the current video signal A and the 1H delay signal C of the current field is mixed at a larger ratio (including 1).
The occurrence of flicker due to the movement of the image is reduced as much as possible (a large difference from the signal B means that the movement is large). This interpolation filter is suitable for creating an interpolation signal for a moving image.

A specific example of the mixing circuit 32 for achieving the above-described mixing processing is described in ninth embodiment.
It is shown in the figure.

The mixing circuit (the alpha ₁ mixed output) mixing under the control of the control signal S2 and the input signal A and C coefficient switching the circuit 51, the input signal A and the arithmetic mean of the B alpha ₂ = (A + C)
/ 2, and the outputs α ₁ ,
alpha (and alpha selective output) is selected in accordance with the control signal S1 to one of ₂ and a change-over switch 53. The output signal of the changeover switch 53 becomes an adaptive interpolation signal. The changeover switch 53 is controlled by a control signal S1 (0 or 1), as indicated by 0 and 1 adjacent to the switch 53, as shown in FIG.
Switching is controlled. Further, although shown as a contact type, it goes without saying that the switch 53 is constituted by a semiconductor element or the like. These apply to other changeover switches described later.

A specific configuration example of the coefficient switching circuit 51 is shown in FIG. 10, and the operation of the mixing circuit including the operation of the coefficient switching circuit 51 (the mixing ratio of the signals A and C with respect to the state of the control signals S1 and S2, and The output signals α ₁ , α ₂ , α) are shown in FIG.

The structure and operation of the coefficient switching circuit 51 are shown in FIGS.
As is clear from the figure, a brief description will be given. This circuit consists of a circuit that creates A / 4, 3A / 4, C / 4, and 3C / 4,
A changeover switch for switching these signals including A and C,
An addition circuit for adding the switching result.

1/3 coefficient unit 61a, 1/4 coefficient unit 62a and addition circuit 63a
A signal representing A / 4 is created. A or 3A / 4 is selected by the changeover switch 64a. Selector switch
65a selects either a signal representing A / 4 or a signal representing 0, which is the output of the 1/4 coefficient unit 62a. These changeover switches 64a and 65a are controlled by the LSB of the control signal S2. One of the outputs of the changeover switches 64a and 65a is selected by the changeover switch 66a. This changeover switch 6
6a is controlled by the MSB of the control signal S2.

The 1/2 coefficient unit 61b, the 1/4 coefficient unit 62b, and the addition circuit 63b provide 3
A signal representing C / 4 is created. Either C or 3C / 4 is selected by the changeover switch 64b. Selector switch
65b selects either a signal representing C / 4 or a signal representing 0, which is the output of the 1/4 coefficient unit 62b. These changeover switches 64b and 65b are controlled by the LSB inverted by the NOT circuit 68b of the control signal S2. Changeover switch 64b
Either one of the outputs 65b and 65b is selected by the changeover switch 66b. The changeover switch 66b is controlled by the MSB inverted by the NOT circuit 68a of the control signal S2.

The output signal of the changeover switch 66a and 66b are formed by adding the output signal alpha ₁ in the addition circuit 67.

Next, each of the nonlinear processing circuits 3, 16, and 26 will be described.

First, a first specific configuration example of the first nonlinear processing circuit 3 will be described. FIG. 12 is a circuit diagram showing an example of the first nonlinear processing circuit 3. FIG. 13 is a graph showing the relationship between the level of an inter-field difference signal (hereinafter simply referred to as difference signal X) input to the first nonlinear processing circuit 3 and the nonlinear coefficient k of the nonlinear processing circuit 3. FIG. 14 is a graph showing the relationship between the input difference signal X and the output signal (hereinafter denoted by the symbol Y) Y of the nonlinear processing circuit 3.

As is apparent from FIG. 14, the nonlinear processing circuit shown in FIG. 12 has a proportional relationship between the level of the input X and the level of the output Y until the input X reaches the predetermined value Δ. , The output Y is kept at a constant value ΔK. Input difference signal X
Contains a component representing the motion of the image in addition to the noise component. It is considered that the level of the input difference signal X increases as the component representing the movement increases. On the other hand, the level of the noise component may be considered to be almost constant. Therefore, in this nonlinear processing circuit, when the level of the input X exceeds a predetermined value Δ, the level of the output Y representing the noise component is kept constant. This non-linear processing circuit has a feature that the configuration is simple.

Referring to FIG. 12, difference signal X input to nonlinear processing circuit 3 is applied to absolute value circuit 71, sign determination circuit 72, and coefficient unit 73a in first coefficient unit group 73. The absolute value circuit 71 converts the input difference signal X into an absolute value, and the output signal is supplied to one input terminal of a comparator 78 described later. The sign determination circuit 72 determines whether the input difference signal X is positive or negative.
The determination signal is provided to a switching circuit 77 described later as a switching control signal.

The first coefficient unit group 73 includes two coefficient units 73a and 73b. Each of these coefficient units 73a and 73b multiplies an input signal by a coefficient K and outputs the result. One coefficient unit 73a
Multiplies the input difference signal X by a factor K, and supplies a signal representing Y ₁ = KX to the switching circuit 79 in the next stage.

In this embodiment, it is possible to switch the degree of the low noise range in two stages, and for this purpose, a threshold value generating circuit 74 for generating two types of threshold values Δ ₁ and Δ ₂ is provided. These threshold values Δ ₁ and Δ ₂ are applied to two input terminals of the switching circuit 75, respectively. The switching circuit 75 is given a threshold selection signal from the outside to specify the degree of noise reduction, the threshold delta ₁ or delta in accordance with the selection signal
₂ is selected. Is selected is output from the switching circuit 75 threshold delta (2 kinds of collectively threshold delta ₁ and delta ₂ delta
Is represented by 2 in the second coefficient unit group 76.
The two input terminals of the two coefficient units 76a and 76b and the comparator 78 are provided. One of the coefficient units 76a in the second coefficient unit group 76 multiplies the input threshold value Δ by 1, and the other coefficient unit 76b multiplies the input threshold value Δ by −1, and outputs a signal representing them. Output. The output signals of the coefficient units 76a and 76b are supplied to two input terminals of the switching circuit 77, respectively.

The switching circuit 77 performs the switching based on the determination signal of the code determination circuit 72. That is, the switching circuit 77 determines the threshold value Δ input from the coefficient unit 76a if the input difference signal X determined by the sign determination circuit 72 is positive, and the coefficient unit 76b if the input difference signal X is negative.
Select the threshold value -Δ given by The threshold value Δ or −Δ selected by the switching circuit 77 is given to the coefficient unit 73b in the first coefficient unit group 73, multiplied by K, and Y ₂ = ΔK (Δ
Is also provided to the switching circuit 79.

On the other hand, the threshold delta ₁ or delta ₂ given to the comparator 78 and the input differential signal X which is the absolute value in the comparator 78 are compared. The comparator 78 supplies a switching control signal to the switching circuit 79 according to the magnitude. That is, if the input difference signal X is equal to or smaller than the selected threshold value, the switching circuit 79 outputs the signal Y ₁ = KX. If the input difference signal X is larger than the selected threshold value, the switching circuit 79 outputs the signal Y _2. = ΔK is output. Also, a signal for turning on and off the noise reduction circuit is provided to the switching circuit 79. When the ON signal is provided, the switching circuit 79 performs the above-described operation according to the output of the comparator 78. given is switched to Y ₃ terminal is grounded,
The output Y becomes 0.

Another specific configuration example of the first nonlinear processing circuit 3 for noise reduction will be described. FIG. 15 is a circuit diagram showing a second example of the first nonlinear processing circuit 3. FIG. 16 is a graph showing the relationship between the level of the inter-field difference signal X and the nonlinear coefficient k of the nonlinear processing circuit 3. FIG. 17 is a graph showing the relationship between the input difference signal X and the output signal Y of the nonlinear processing circuit 3. FIG.

In the nonlinear processing circuit shown in FIG. 15, the level of the input X and the level of the output Y are proportional to the input X up to the predetermined value Δ, as is apparent from FIG. Then, the output Y is kept at a constant value ΔK until 2Δ. When the input X exceeds 2Δ, the output Y decreases linearly with a constant gradient, and when the input X is 3Δ or more, the output Y is kept at zero. Thus, the nonlinear processing circuit is configured to generate an output Y whose level changes in a trapezoidal shape in accordance with an increase in the level of the input X.

The input difference signal X includes a component representing the motion of the image in addition to the noise component. It is considered that the level of the input difference signal X increases as the component representing the movement increases. No.
In the nonlinear processing circuit shown in FIG. 15, when the level of the input X exceeds a predetermined value Δ, the level of the output Y representing the noise component is kept constant, when the level exceeds 2Δ, the output Y decreases, and when the level exceeds 3Δ, the output Y decreases. It is set to zero so that the noise reduction processing is not performed. Therefore, when this nonlinear processing circuit is used, ideal noise reduction processing can be expected.

Referring to FIG. 15, difference signal X input to first nonlinear processing circuit 3 is applied to absolute value circuit 71, sign discrimination circuit 72, and coefficient unit 73a in first coefficient unit group 73. Absolute value circuit 71
Represents an absolute value of the input difference signal X, and its output signal is supplied to one input terminal of three comparators 78a to 78c in a comparator group 78 described later. The code discriminating circuit 72 calculates the input difference signal X
The discrimination signal is given as a switching control signal to a switching circuit 77 described later.

The first coefficient unit group 73 includes two coefficient units 73a and 73b. Each of these coefficient units 73a and 73b multiplies an input signal by a coefficient K and outputs the result. One coefficient unit 73a
Multiplies the input difference signal X by a coefficient K, and supplies a signal representing Y ₁ = KX to the next-stage switching circuit 79 and to the subtractor 80.

Also in this embodiment, the degree of noise reduction can be switched in two stages, and for that purpose, a threshold value generating circuit 74 for generating two types of threshold values, Δ ₁ and Δ ₂ , is provided. These threshold values Δ ₁ and Δ ₂ are applied to two input terminals of the switching circuit 75, respectively. The switching circuit 75 threshold selection signals are given these externally specifying the degree of noise reduction, the threshold delta ₁ or delta ₂ in response to the selection signal
Is selected. Signal representing a threshold that has been selected is outputted from the switching circuit 75 delta (collectively two thresholds delta ₁ and delta ₂ expressed in delta) is 4 in the second coefficient unit group 76 The two coefficient units 76a, 76b, 76c, 76d and the other input terminal of the comparator 78a. The coefficient unit 76a in the second coefficient unit group 76 multiplies the input threshold value Δ by 1, and the coefficient unit 76b multiplies the input threshold value Δ by −1, and outputs a signal representing them. is there. The output signals of the coefficient units 76a and 76b are switched by the switching circuit 7.
7 input terminals.

The switching circuit 77 performs the switching based on the determination signal of the code determination circuit 72. That is, the switching circuit 77 determines the threshold value Δ input from the coefficient unit 76a if the input difference signal X determined by the sign determination circuit 72 is positive, and the coefficient unit 76b if the input difference signal X is negative.
Select the threshold value -Δ given by The threshold value Δ or −Δ selected by the switching circuit 77 is supplied to the coefficient unit 73b of the first coefficient unit group 73, multiplied by K, and set as Y ₂ = ΔK (Δ includes negative values). And to the coefficient unit 76e.

The coefficient units 76c and 76d double and triple the signal representing the threshold value Δ given from the switching circuit 75, respectively.
Give to the other input terminal of c. Furthermore, the coefficient unit 76e
Represents the signal representing Y ₂ = ΔK output from the coefficient unit 73b as 3
The signal is multiplied and given to the subtractor 80 as a signal representing 3ΔK.

In the subtracter 80, 3ΔK-KX is calculated, the signal Y ₃ representing the calculation result is input to the switching circuit 79.

On the other hand, in the comparators 78a to 78c in the comparator group 78, the absolute value of the input difference signal X and the reference values (threshold values Δ, 2Δ, 3Δ) given to the comparators 78a to 78c are compared. The respective signals are compared, and a signal representing the result of the comparison is input to the switching circuit 79 as a switching control signal. In response to the switching control signal, switching circuit 79 outputs signal Y ₁ = KX when the level of input difference signal X is equal to or smaller than threshold value Δ, and outputs signal Y ₁ when Δ <X ≦ 2Δ. ₂ = ΔK is output, and when 2Δ <X ≤ 3Δ, a signal Y ₃ = 3ΔK-Y ₁ is output. When X exceeds 3Δ, a 0 level signal of the grounded Y ₄ terminal is output. Is switched. Also, a signal for turning on / off the noise reduction circuit is given to the switching circuit 79. When the ON signal is given, the switching circuit 79 performs the above-described operation according to the output of the comparator group 78. When given, is switched to Y ₄ terminal which is grounded, the output Y becomes 0.

FIG. 18 is a circuit diagram showing a third example of the first nonlinear processing circuit 3. FIG. 19 is a graph showing a function of the level of the input difference signal X and the nonlinear coefficient k of the nonlinear processing circuit, and FIG. 20 shows the relationship between the input difference signal X and the output signal Y of the nonlinear processing circuit. It is a graph.

In the non-linear processing circuit shown in FIG. 18, the level of the input X and the level of the output Y are proportional to the input X up to the predetermined value Δ, as is apparent from FIG. , The output Y decreases linearly with a constant gradient, and the input X
Is greater than or equal to 2Δ, the output Y is kept at zero. Thus, the nonlinear processing circuit is configured to generate an output Y whose level changes in a triangular shape in accordance with an increase in the level of the input X. According to this nonlinear processing circuit, a noise reduction process close to ideal can be expected, and the configuration is simpler than the circuit shown in FIG.

In FIG. 18, the same components as those shown in FIG. 15 are denoted by the same reference numerals, and only different points will be described.

Output Y ₂ of the coefficient unit 37b is not input to the switching circuit 79. The comparator group 78 does not include the comparator 78c. A signal representing 2Δ output from coefficient unit 76f is applied to subtractor 80. Therefore, from the subtractor 80, Y ₃ = 2Δ
A signal representing K-KX is input.

The switching circuit 79 operates as follows by the switching control signal input from the comparator group 78. That is, the switching circuit 79 to the input differential signal X delta selects and outputs the signal Y _1, delta <X
≦ outputs a signal Y ₃ when 2.DELTA., X is output exceeds the zero level signal Y ₄ a 2.DELTA.. Thus, the characteristics shown in FIGS. 19 and 20 are obtained.

Next, a second nonlinear processing circuit 26 and a third nonlinear circuit
Sixteen specific configuration examples will be described. The same circuit configuration can be used for the second nonlinear processing circuit 26 and the third nonlinear processing circuit 16. A circuit diagram showing an example of the second nonlinear processing circuit 26 or the third nonlinear processing circuit 16 is shown in FIG. FIG. 22 shows the circuits 26
16 is a graph showing a relationship between a difference signal input to 16 or an output signal. Hereinafter, the second nonlinear processing circuit 26 or the third
The signal input to the nonlinear processing circuit 16 by the symbol X ₀ of showing signals output from the circuits 26 or 16 by symbol Z.

In the nonlinear processing circuit shown in FIG. 21, the output Z is kept at zero regardless of the value of the input X ₀ until the input X ₀ reaches a predetermined value D, as is apparent from FIG. Input X ₀ is the until 2D from the predetermined value D is at a level proportional relationship level and output Z of the input X _0. Further, the output Z to 3D when the input X ₀ is equal to or greater than 2D is kept at an example value DS. Output Z and the input X ₀ exceeds 3D linearly decreases at a constant gradient, the input X ₀ is the least 4D is kept output Z is zero. Thus, the nonlinear processing circuit is configured to generate an output Z ₀ which level changes in a trapezoidal shape in response to an increase in the level of the input X _0.

The input differential signals X ₀ In addition to the components representing the vertical contour includes a component representing the movement of the noise component and images.
Level of the input difference signal X ₀ is considered noise component is large in the lower part. Also it is considered that the level of the input differential signals Y ₀ and components representing movement increases increases. The non-linear processing circuit shown in FIG. 21, the level of the input X ₀ is the noise component is large in the range of the predetermined value D maintaining the output signal Z to zero, also the level of the input X ₀ is motion in the range of more than 4D Since the output signal Z is kept at zero because of intense contour enhancement, no contour enhancement is performed. The level of the input X ₀ is a nonlinear processing circuit for an ideal contour compensating for the contour enhancement in accordance with the level of the input signal in the range of D～4D.

Difference signal X ₀ is an absolute value circuit 81 to be input to the second nonlinear processing circuit 26 or the third nonlinear processing circuit 16 with reference to Figure 21,
Sign discriminating circuit 82 and coefficient unit 83a in first coefficient unit group 83
Given to. The absolute value circuit 81 by way of the absolute value of the input differential signals X _0, the output signal in the comparator group 88 to be described later 4
The comparators 88a to 88d are provided to one input terminal. Code discriminating circuit 82 is a positive input differential signals X _0, it intended to determine the negative sign, the determination signal is provided as a switching control signal to the switching circuit 87 to be described later.

The first coefficient unit group 83 includes two coefficient units 83a and 83b. These coefficient units 83a and 83b both multiply an input signal by a coefficient S and output the result. One coefficient unit 83a
Multiplies the input difference signal X ₀ by a factor S, and supplies a signal representing Z ₁ = SX ₀ to the next-stage switching circuit 89 and also to the subtracters 90 and 91.

In this embodiment, the degree of contour emphasis can be switched between two levels, and for this purpose, a threshold value generating circuit 84 for generating two types of threshold values D ₁ and D ₂ is provided.
These threshold values D ₁ and D ₂ are applied to two input terminals of the switching circuit 851, respectively. The switching circuit 85 is given a threshold selection signal from the outside to specify the degree of edge enhancement, threshold D ₁ or D ₂ is selected according to the selection signal. Selected threshold value D output from switching circuit 85
A signal representing the two types of threshold values D ₁ and D ₂ is collectively represented by D is a signal representing five coefficient units 86 a,
86b, 86c, 86d, 86e and the other input terminal of the comparator 88a. A coefficient unit 86a in the second coefficient unit group 86 multiplies the input threshold value D by 1, and a coefficient unit 86b multiplies the input threshold value D by -1 and outputs a signal representing them. is there. Output signals of the coefficient units 86a and 86b are supplied to two input terminals of the switching circuit 87, respectively.

The switching circuit 87 performs the switching based on the determination signal of the code determination circuit 82. That switching circuit 87, a threshold D of the input differential signals X _0, which is determined by the code discrimination circuit 82 is inputted from the positive if the coefficient multiplier 86a, a coefficient unit 86b if negative
Select the threshold value -D given by The threshold value D or -D selected by the switching circuit 87 is given to a coefficient unit 83b in the first coefficient unit group 83, multiplied by S, and set as Z ₂ = DS (D includes negative). It is provided to 89 and to a coefficient unit 86f.

The coefficient units 86c, 86d and 86e double, triple and quadruple the signal representing the threshold value D supplied from the switching circuit 85, respectively, and supply the same to the other input terminals of the comparators 88b, 88c and 88d, respectively. Further, the coefficient unit 86f multiplies the signal representing Z ₂ = DS output from the coefficient unit 83b by four times and supplies the signal to the subtractor 91 as a signal representing 4DS.

In the subtracter 91, 4DS-SX ₀ is calculated, the signal Z ₃ representing a calculation result is input to the switching circuit 89. Further, a signal representing Z ₂ = DS output from the coefficient unit 83b is input to the subtractor 90, and Z ₁ = SX ₀ −DS is calculated by the subtracter 90, and a signal Z representing the calculation result is obtained. ₁ is input to the switching circuit 89.

On the other hand, the comparator 88 a to 88 d in the group of comparators 88, absolute-valued input differential signals X ₀ and the reference value given to the comparators 88 a to 88 d (threshold D, 2D, 3D, 4D ) Are compared with each other, and a signal representing the result of these comparisons is input to the switching circuit 89 as a switching control signal. The switching circuit 89 is responsive to the switching control signal, the level of the input differential signal X ₀ is the case of below the threshold value D outputs a 0-level signal Z ₄ terminal which is grounded, D <X outputs Z ₁ = SX ₀ -DS in case of ₀ ≦ 2D, 2D <
X ₀ outputs a signal Z ₂ = DS in the case of ≦ 3D, and outputs a signal Z ₃ = 4DS-SX ₀ in the case of 3D <X ₀ ≦ 4D, is grounded when X ₀ is greater than 4D switching the 0 level of the signal Z ₄ terminal is to output. A signal for turning on and off the contour compensation circuit is supplied to the switching circuit 89. When the ON signal is supplied, the switching circuit 89 performs the above-described operation according to the output of the comparator group 88. Is given,
Is switched to Z ₄ terminal which is grounded, the output Z becomes 0.

According to the present invention, a noise-reduced current video signal, a noise-reduced 1H delay signal in the same field as the noise-reduced video signal, and a noise-reduced 263H delay signal in the previous field are input, and the level difference between these signals is determined. Then, the noise reduction adaptive interpolation signal is created by changing the mixing ratio of the current video signal and the 1H delay signal. In particular, the degree of image motion is detected based on the level difference between the 263H delay signal of the previous field and the current video signal and 1H delay signal of the current field, and the current video signal of the current field and the 1H delay signal are determined according to the detection result. Is mixed, and flickering that is likely to occur when there is movement can be prevented. The adaptive interpolation signal according to the present invention is particularly effective for improving the quality of a moving image.

Further, according to the present invention, the above-described noise reduction adaptive interpolation signal is subjected to vertical contour emphasis processing. That is, the level of the second inter-field difference signal for the interpolation signal is detected, and nonlinear processing is performed on the inter-field difference signal in accordance with the detected level. By adding the non-linearly processed inter-field difference signal to the adaptive interpolation signal, an adaptive interpolation signal with vertical contour compensation is finally obtained. As described above, according to the present invention, it is possible to generate an adaptive interpolation signal which has been appropriately subjected to vertical contour compensation and which has been subjected to noise reduction processing for progressive scanning.

In addition, 263H (or 26
2H) Since the delay circuit (field memory) and the same delay circuit required for creating an interpolation signal and the same delay circuit for vertical contour compensation are shared, the circuit configuration is simplified accordingly. In addition, since the first nonlinear processing circuit for noise reduction and the second nonlinear processing circuit for contour enhancement are provided separately, nonlinear signals corresponding to respective purposes are provided for the respective field difference signals. Processing can be performed, and appropriate noise reduction and contour emphasis can always be performed in accordance with the motion of the image.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a progressive scan conversion apparatus according to the present invention. FIG. 2 shows the relationship between the current video signal, the 262H delay signal, and the 263H delay signal. FIG. 3 shows the current video signal, the 1H delay signal, and the 263H delay signal.
FIG. 4 is a diagram illustrating a relationship with a delay signal. FIG. 4 is a block diagram showing a schematic configuration of an interpolation filter circuit, FIG. 5 is a circuit diagram showing a configuration of a comparison processing circuit, FIG. 6 is a diagram showing the comparison operation collectively, and FIG. FIG. 8 is a diagram collectively showing the decoding operation and the mixed output, FIG. 9 is a block diagram showing the configuration of the mixing circuit, FIG. 10 is a circuit diagram showing the configuration of the coefficient switching circuit, and FIG. FIG. 11 is a diagram collectively showing the operation of the mixing circuit. FIG. 12 shows the first non-linear processing circuit for noise reduction.
13 is a graph showing the relationship between the level of the inter-field difference signal and the nonlinear processing coefficient, and FIG. 14 is a graph showing the relationship between the inter-field difference signal and the output signal of the non-linear processing circuit. is there. FIG. 15 shows the second non-linear processing circuit for noise reduction.
FIG. 16 is a graph showing the relationship between the level of the inter-field difference signal and the nonlinear processing coefficient, and FIG. 17 is a graph showing the relationship between the inter-field difference signal and the output signal of the non-linear processing circuit. is there. FIG. 18 shows the third non-linear processing circuit for noise reduction.
FIG. 19 is a graph showing the relationship between the level of the inter-field difference signal and the nonlinear processing coefficient, and FIG. 20 is a graph showing the relationship between the inter-field difference signal and the output signal of the non-linear processing circuit. is there. FIG. 21 is a circuit diagram showing an example of a second nonlinear processing circuit or a third nonlinear processing circuit for vertical contour compensation, and FIG. 22 shows a relationship between an inter-field difference signal and an output signal of the nonlinear processing circuit. It is a graph. 1 ... first subtraction circuit, 2 ... second subtraction circuit, 3 ... first non-linear processing circuit, 4 ... 262H delay circuit, 5,21 ... 1H delay circuit, 6 ... switching circuit, 8,22 addition circuit, 9,23 1/2 coefficient unit, 14 fourth subtraction circuit, 16 third nonlinear processing circuit, 17 second addition circuit, 24 Third subtraction circuit, 26 second non-linear processing circuit, 27 first addition circuit, 28 interpolation filter circuit, 31 comparison processing and decoding circuit, 32 mixing circuit.

Claims (8)

(57) [Claims] 1. A 262H delay circuit for delaying a noise-reduced input video signal by 262H, a 263H delay circuit for delaying a noise-reduced input video signal by 263H, an output signal of the 263H delay circuit, and an output signal of the 262H delay circuit And a switching circuit for selecting and outputting the output signal of the 263H delay circuit during one field scan, and selecting and outputting the output signal of the 263H delay circuit during the other field scan. A first subtraction circuit for calculating a difference from an output signal of the switching circuit to output a first inter-field difference signal, and a noise for the first inter-field difference output signal output from the first subtraction circuit A first non-linear processing circuit for performing predetermined non-linear processing for reduction, a second non-linear processing circuit for subtracting an output signal of the first non-linear processing circuit from an input video signal and outputting the result as a noise reduced video signal A subtraction circuit, and a noise reduction video signal output from the second subtraction circuit.
A 1H delay circuit for delaying 1H, a noise-reduced video signal output from the second subtraction circuit, and a signal delayed for 1H by the 1H delay circuit, and a first signal for outputting an average signal of these input signals A third subtraction circuit that calculates a difference between an output signal of the 263H delay circuit and an output signal of the first averaging circuit to output a second inter-field difference signal; A noise-reduced current video signal output from the subtraction circuit, a 263H delay signal output from the 263H delay circuit,
The 1H delay signal output from the 1H delay circuit is input, and according to the comparison result of the levels of these three input signals, the noise-reduction current video signal and the 1H delay signal are mixed to form an adaptive interpolation signal. An interpolation filter circuit that creates and outputs a predetermined non-linear processing for vertical contour compensation on the second inter-field difference signal output from the third subtraction circuit according to the level of the inter-field difference signal A second non-linear processing circuit that performs the above-described processing, and a first addition that adds an output signal of the second non-linear processing circuit to the adaptive interpolation signal and outputs an interpolation signal that has been subjected to noise reduction and vertical contour compensation. A progressive scan conversion device comprising a circuit. 2. The progressive scan conversion device according to claim 1, wherein said 263H delay circuit comprises said 263H delay circuit and a second 1H delay circuit connected in cascade to said 263H delay circuit. 3. The interpolation filter circuit according to claim 1, wherein the level difference between the current video signal and the 263H delay circuit and the
A comparison processing circuit for detecting the level difference between the delay signal and the 1H delay signal, a decoding circuit for converting an output signal of the comparison processing circuit into a mixing control signal, and a mixing control signal provided from the decoding circuit; 2. A progressive scan converter according to claim 1, further comprising a mixing circuit for generating and outputting an adaptive interpolation signal by mixing the current video signal and the 1H delay signal with a ratio corresponding to the level difference. apparatus. 4. A second averaging circuit for receiving an output signal of the 263H delay circuit and an output signal of the 263H delay circuit and outputting an average signal of these output signals, and an output from the second subtraction circuit. The difference between the noise reduced video signal to be output and the output signal of the second averaging circuit is calculated,
A fourth subtraction circuit for outputting the inter-field difference signal, and a third non-linear processing for performing predetermined non-linear processing for vertical contour compensation on the third inter-field difference signal output from the fourth subtraction circuit Processing circuit, and adding the output signal of the third nonlinear processing circuit to the low-noise video signal output from the second subtraction circuit to generate a developed video signal that has been subjected to low-noise and vertical contour compensation. 2. The progressive scan conversion device according to claim 1, further comprising: a second adder circuit for outputting. 5. A first non-linear processing circuit for noise reduction, comprising: a first circuit for generating a first signal having a level proportional to a level of the first inter-field difference signal; A second circuit for generating a second signal of a constant level irrespective of the level of the first inter-field difference signal; comparing the level of the first inter-field difference signal with a predetermined reference level; A comparison circuit for outputting a signal representing the first signal when the level of the first inter-field difference signal is equal to or lower than the reference level, and when the level of the first inter-field difference signal is equal to or lower than the reference level, The switching device according to claim 1, further comprising a switching circuit for selecting and outputting the second signal. 6. A first non-linear processing circuit for noise reduction, comprising: a first circuit for generating a first signal having a level proportional to a level of the first inter-field difference signal; A second circuit for generating a second signal having a constant level irrespective of the level of the first inter-field difference signal; and a third circuit for reducing the level as the level of the first inter-field difference signal increases. A third circuit for generating a signal, and a level of the first inter-field difference signal,
A comparison circuit for comparing the second and third reference levels to output a signal representing a comparison result; and a level of the first inter-field difference signal corresponding to the first reference level in response to an output signal of the comparison circuit. When the signal is below the level, the first signal is output. When the signal is between the first reference level and the second reference level, the second signal is output between the second reference level and the third reference level. And a switching circuit for selecting and outputting a signal of a third level when the signal is at a level of zero and a signal at a level of zero when the signal is equal to or higher than the reference level of the third level. . 7. A first non-linear processing circuit for noise reduction, comprising: a first circuit for generating a first signal having a level proportional to a level of the first inter-field difference signal; A second circuit for generating a second signal whose level decreases with an increase in one inter-field difference signal, and a first and a second reference level different in level of the first inter-field difference signal A comparison circuit that outputs a signal representing a comparison result; and, when the level of the first inter-field difference signal is equal to or lower than a first reference level, the first signal is output according to the output signal of the comparison circuit. A switching circuit for selecting and outputting the second signal when the signal is between the first reference level and the second reference level, and outputting a signal having a zero level when the signal is equal to or higher than the second reference level; A contract consisting of Progressive scanning conversion apparatus according to claim (1). 8. A second or third for vertical contour compensation.
A first circuit for generating a first signal having a level proportional to the level of the second or third inter-field difference signal; and a non-linear processing circuit for generating the first or second inter-field difference signal. A second circuit for generating a second signal having a constant level regardless of the level; and a second circuit for generating a third signal whose level decreases as the level of the second or third inter-field difference signal increases. And the level of the second or third inter-field difference signal
A comparison circuit for comparing the first, second, third, and fourth reference levels with each other and outputting a signal representing a comparison result; and a second or third signal corresponding to an output signal of the comparison circuit.
When the level of the inter-field difference signal is less than or equal to the first reference level, the zero-level signal is output. When the level difference signal is between the first reference level and the second reference level, the first signal is output. When the second signal is between the third reference level and the third reference level, the second signal is output.
When the third signal is between the reference levels of
The switching device according to claim 1, further comprising a switching circuit for selecting and outputting a signal of a zero level when the signal is equal to or higher than the fourth reference level.