JPH036182A - Vertical outline compensating circuit for interpolating signal - Google Patents

Abstract

PURPOSE:To execute an appropriate outline compensation corresponding to a motion of an image by inputting the present video signal, a 1H delay signal of the same field as this signal, and a 263H delay signal of the previous field, changing a mixture ratio of the video signal and the 1H delay signal in accordance with a level difference of these signals and generating an adaptive type interpolating signal. CONSTITUTION:An input signal (the present video signal being a luminance signal after Y/C separation) of an input terminal is applied to a 262H delaying circuit (field memory) 1, a subtracting circuit 5 and an adding circuit 8, an output signal of the circuit 1 is applied to a 1H delaying circuit (line memory) 2, and in the end, an output of the circuit 2 is delayed by 263H from the present video signal. Thereafter, outputs from the circuit 1 and 2 are added by an adding circuit 3 and brought to 1/2 fold by a 1/2 coefficient multiplier 4, this signal and the previous field average video signal are applied to the subtracting circuit 5 and it becomes an inter-field difference signal of the present video signal. Thereafter, it is inputted to a non-linear processing circuit 7 through a low-pass filter 6, an output of the circuit 7 is added to the present video signal generated from the adding circuit 8, and it becomes a signal whose vertical outline is compensated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a vertical contour compensation circuit for creating an interpolation signal necessary for progressive scan conversion and for applying vertical contour enhancement to this interpolation signal.

Conventional technologyIn response to demands for higher image quality in television receivers, IDTV
, HDTV, and other systems have been developed or realized. These methods perform sequential scanning (non-interlaced scanning), which requires the creation of interpolation signals. This interpolation signal is created by interpolation between lines or interfields, but depending on the presence or absence of movement in the three images and its degree, interpolation between lines and interfields can be switched as appropriate, or the video signal between lines or fields can be mixed. It is said that it is preferable to change the ratio. In addition, to create an interpolated signal,
It is desirable to take measures to prevent flickering (line flicker) as much as possible.

On the other hand, in order to improve the sharpness of the two images, not only horizontal edge enhancement but also vertical edge enhancement is necessary.

Since the interpolation signal is a type of average value signal, it works in the direction of blurring one contour, so vertical contour compensation is an essential technique.

Vertical edge enhancement is generally performed by adding an inter-field difference signal or an inter-frame difference signal to the original signal, but it is necessary to take into account the degree of movement of the six images. This is because the level of the difference signal mentioned above is related to the vertical contour when there is little or no movement, but as the movement increases, more difference components due to movement are included.

Problems to be Solved by the Invention The present invention creates an interpolation signal that takes into account the movement of one image and prevents the occurrence of flickering, and provides a circuit that performs appropriate contour compensation on this interpolation signal according to the movement of the image. This is what we provide.

Means for Solving the Problems The vertical contour compensation circuit for interpolation signals according to the present invention includes a first delay circuit that delays the input current video signal by 1H, and a second delay circuit that delays the input current video signal by 283H. The 1H delayed signal outputted from the first delay circuit in section 9 and the 263H delayed signal outputted from the second delay circuit in section 1 are manually input, and the levels of these three input signals are manually input. Comparison of 'C1 above current video signal and 1
An interpolation filter circuit that creates and outputs an adaptive interpolation signal by mixing with H delay (A), an interfield difference signal creation circuit that creates and outputs an interfield difference signal of the interpolation signal, For the inter-field difference signal output from the inter-field difference signal generation circuit (.

and a nonlinear processing circuit that performs predetermined nonlinear processing for C vertical contour compensation according to the level of the difference signal between 71 and 71, and adds the output signal of the nonlinear processing circuit to the adaptive interpolation signal, Interpolation with vertical contour compensation 45
It is equipped with an adder circuit that outputs the signal.

The interpolation filter circuit includes a comparison processing circuit that detects the level difference between the current video signal and the 263H delayed signal, and a level difference between the 263H delayed signal and the 1H delayed signal, and mixes and controls the output signals of the comparison processing circuit. It is controlled by a decoding circuit that converts into a signal and a mixing control signal given from the decoding circuit, and the current video No. 45 and No. 1 are
It is composed of a mixed C circuit that outputs an adaptive inter-interpolation signal by mixing the H delay signal and the H delay signal at a predetermined ratio according to the level difference of "-2".

The current video signal, the 1H delayed signal of the field between it, and the 263H delayed signal of the previous field are input, and the current video signal is calculated according to the level difference between these signals (that is, taking into account the movement of the image). An adaptive interpolation signal is created by changing the mixing ratio of the video signal and the Hi1 extended signal (without using the 283H delayed signal). Vertical contour enhancement processing is applied to this adaptive somote signal. That is, the level of the interfield difference signal of the interpolation signal is detected, and the interfield difference signal is subjected to nonlinear processing in accordance with the detected level. By adding the non-linearly processed inter-field difference signal to the adaptive interpolation signal, an adaptive interpolation signal with vertical contour compensation is finally obtained.

Embodiment FIG. 1 shows a vertical contour compensation circuit according to an embodiment of the present invention. This vertical contour compensation circuit performs vertical contour compensation on both the current video signal and the interpolation signal created therefrom, and has the feature that a part of the eight circuits can be shared.

First, the vertical contour compensation operation for the current video signal will be explained.

The video signal (luminance signal after Y/C separation) (this is called the current video signal) input to the input terminal is processed by a 262H delay circuit (field memory)1. The signal is applied to a subtraction circuit 5 and an addition circuit 8. The output signal of the 282H delay circuit 1 is given to the 1H delay circuit (line memory) 2. After all, the output of 1H delay circuit 2 is.

It is delayed by 283H from the input current video signal.

The 2G2H delay signal output from the 262H delay circuit 1 and the 263H delay signal output from the 1H delay circuit 2 are added in the adder circuit 3, and then 1/2 in the 1/2 coefficient unit 4.
By multiplying, the arithmetic average is obtained. As shown in Fig. 2, the 263H delayed signal and the 262H delayed signal are the signals of the previous field in interlaced scanning, and the 263H delayed signal and the 262H delayed signal are the signals of the previous field in interlaced scanning. . Therefore, the output signal of the 1/2 coefficient unit 4 will be referred to as the previous field average video signal.

The previous field average video signal output from the 1/2 coefficient unit 4 is applied to a subtraction circuit 5. By subtracting the previous field average video signal from the current video signal in the subtraction circuit 5, an inter-field difference signal of one current video signal is obtained.

The inter-field difference signal output from the subtraction circuit 5 passes through a low-pass filter 6 and is input to a nonlinear processing circuit 7. This inter-field difference signal includes a high frequency component in the vertical direction of the image (specifically, a 15.7 KHz signal and its high frequency). The low pass filter 6 is 0.5MHz or I
It allows signals of about M II z or less to pass through, thereby removing high frequency components in the horizontal direction (
This is generally high frequency noise) is removed. In this way, only the vertical signal component is input to the first nonlinear processing circuit 7. An example of a specific configuration of the nonlinear processing circuit 7 will be described later, but for example, it has characteristics as shown in FIG. Accordingly, a signal component (contour compensation component of the current video signal) representing the vertical contour to be emphasized is output.

The output signal of the nonlinear processing circuit 7 is then given to an adder circuit 8. This adding circuit 8 is supplied with a current video signal, and by adding the output signal of the nonlinear processing circuit 7 to this current video signal, a current video signal with vertical contour compensation is output from the adding circuit 8. It turns out.

Next, a vertical contour compensation circuit for interpolation signals for progressive scan conversion will be described.

The input current video signal is sent to the 1H delay circuit 10. Addition circuit 11
and the interpolation filter circuit 13.

The output signal of the 1HH extension circuit 10 is given to an addition circuit 11 and an interpolation filter circuit 3, respectively. therefore,
In the adder circuit 11, the current video signal and the 1HH extended signal (see Figure 3) output from the 1HH extended circuit are added, and further multiplied by 1/2 in the 1/2 coefficient unit 12 to generate a line interpolation signal. be done. These 1HH extension circuits 10.
The adder circuit 11 and the 1/2 coefficient unit 12 constitute a line interpolation circuit that creates a line interpolation signal.

The line interpolation signal output from the 1/2 coefficient unit 12 is given to a subtraction circuit 15. The 283H delayed signal (previous field signal) output from the 1HH extension circuit 2 (a 1-field delay circuit is configured by the 282H delay circuit 1 and the 1HH extension circuit 2) is input to this subtraction circuit 15, and the 283H By subtracting the line interpolation signal from the delayed signal, an interfield difference signal of the interpolation signal is obtained.

As shown in Figure 3, the line interpolation signal is identical to the current video signal.
Since it is an arithmetic mean with the HH extended signal, it is on the scanning line exactly corresponding to the 21i3H delayed signal. The above-mentioned line interpolation circuit and 21 field delay circuit.

The subtraction circuit 15 constitutes an inter-field difference signal generation circuit.

As mentioned above, the interpolation filter circuit 13 receives the current video signal (
This is represented by the symbol A) and the 1HH extended signal (this is represented by the symbol C.
) in addition to 2 output from the 1HH extension circuit 2
An 83H delayed signal (represented by symbol B) is input. The interpolation filter circuit, path I3, is as described in detail later.
Adaptation is achieved by detecting the level difference between signals A and B and the level difference between signals B and C, and according to the detection results, mixing signals A and C at a predetermined ratio (signal B is not mixed). Create and output a shape interpolation signal. This adaptive interpolation signal is applied to adder circuit 18.

The interfield difference signal of the interpolation signal output from the subtraction circuit 15 is passed through a low-pass filter 16 to the nonlinear processing circuit 1.
7 is given. The vertical contour compensation component signal of the interpolation signal outputted from the nonlinear processing circuit 17 is input to the addition circuit 18 and added to the adaptive interpolation signal provided from the interpolation filter circuit 13. In this way, the adder circuit I8
An adaptive interpolation signal subjected to vertical contour compensation is output from the .

The specific configuration of the interpolation filter circuit 13 will be described with reference to FIGS. 4 to 11.

FIG. 4 shows a schematic configuration of the inter-capturing filter circuit 13. The interpolation filter circuit 13 includes a comparison processing and decoding circuit 31 and a mixing circuit 32. Current video signal A,
The 283H delayed signal B and the 1H delayed signal are applied to the color comparison processing and decoding circuit 31. The mixing circuit 32 is supplied with the current video signal A and the 1H delayed signal color. The comparison processing and decoding circuit 31 receives these input signals A and B.
, C, control signals Sl and S2 for controlling changeover switches in the mixing circuit 32, which will be described in detail later, are created and given to the mixing circuit 32.

The comparison processing and decoding circuit 31 is composed of a comparison processing circuit and a decoding circuit. Details of the comparison processing circuit are shown in FIG. 5, and details of the decoding circuit are shown in FIG. 7.

In FIG. 5, the comparison processing circuit includes two subtraction circuits 33, 3.
Contains 4. One subtraction circuit 33 inputs 263
Subtract the current video signal A from the H-delayed signal B (7°) and give the result to the absolute value circuit 35. Therefore, the absolute value circuit 35 outputs a signal with a level expressed as 1B=AI.The other subtraction circuit 34 Then, from 263H delay signal B to 1H
The delay signal is subtracted, and the result is given to the absolute value circuit 3B to be converted into an absolute value, so from this circuit 3G, IB
- A signal representing the level of CI is output.

The comparison processing circuit further includes seven comparators 37L.

Includes 37M, 37S, 38L, 38M, 388 and 39. Comparators 37L, 37M and 3
The positive input terminals of 75 have reference levels R, RM, and R, respectively.
8 is given. The relationship is R>RM>R8. The output signal IB-A1 of the absolute value circuit 35 is applied to the negative input terminals of these comparators 37L, 37M and 37S. Therefore, the output B-A of the absolute value circuit 35
If I is smaller than the reference level R8, the outputs of all comparators 37S, 37M, and 37L DAs'DAM''
AL becomes H level. This state is called "equivalence." When the level of the signal IB-AI is between the reference 1/bell R and R, the output DAs between S becomes the L level, and the other output DAM'AL maintains the H level. It's called "starting." Signal l B-A
When one novel of l is between the reference level R and R)7, the output DAS and DAM become L level, and the output DA
l maintains the H level. This state is called "in the cavity." When the level of the signal IB-AI exceeds the reference level Rt, all the comparators 37L, 37M, 37
The output DAL "AM" As of S becomes L level. This state is called "insertion." The above comparative operations are summarized in a table in FIG. In this table, the output signal H
The level is represented by 0, and the L level is represented by ].

Similarly, reference levels R, RM, and R8 of 1° are applied to the positive input terminals of comparators 38L, 38M, and 38S, respectively. These comparators 38L, 38M.

The output signal 11 of the absolute value circuit 36 is connected to the negative input terminal of 38S.
3-CI is inputting. These comparators 38L, 3
8M and 38S compare the level of the input signal IB-CI with the reference level R, R, , R8, respectively, and output the output signal DCL "CM" C9 representing the comparison result.
Output. This output signal DCL "CM" C8 is also summarized in FIG.

The comparator 39 outputs the absolute value signal I B-A I and B-Cl
It is used to compare the size of.

When 1B-AI<IB-CI, a signal Tl of H level (represented by code 0) is output, and on the contrary, a signal T1 of L level (represented by code 1) is output. This signal T
1 is not particularly used in the decoding circuit of this embodiment (FIG. 7).

The AND circuit 40 connects the output DA8 of the comparator 37S and the comparator 3.
When both the outputs Dcs of 8S are II novel, that is, when the signals IB-AI and lB-CI are both small (when there is almost no difference between the signals A, B, and C), the H level (sign 0 A signal T2 (expressed as ) is output.

The comparison processing circuit (FIG. 5) outputs signals D 1 , D 2 , D 2 , T2 . D
cL.

AL AM As DCM"C3 is given as an input signal to the decoding circuit shown in FIG. S2 (MSB and LS
(consisting of 2 bits of B), as shown in FIG.

It is configured by a combination of EX-OR circuits 41a, 41b, 41e and OR circuits 42a, 42b.

The operation of this decoding circuit, ie, the relationship between its input signals and output signals, is shown in the form of a table in FIG. FIG. 8 also shows the output mixed signal of the mixing circuit 32 (interpolation filter circuit 1
3) is also shown. Here, the mixed signal expressed in the form of a fraction represents the mixed state of input signals A and C in the mixing circuit 32. For example (AI
C)/2 represents the arithmetic mean of input signals A and C.

In FIG. 8, the mixing ratio of the 8 input signals A and C is:

It is determined according to the difference between signals A, C and signal B.

That is, of the one input signals A and C, the one with a smaller difference from the signal B is used at a larger mixing ratio.

For example, the column s of D-0 and Dcs-〇 in the top row represents the case where the difference signals IB-A and IB-CI are both extremely small (and are equivalent), and in this case, the current video signal A and the 1H delay Arithmetic average signal of delayed signal reactor (A0C
)/2 is output as an adaptive interpolation signal (line interpolation). In addition, in the case of DAs"" and Dcs-1, there is almost no difference between signals A and B (equivalent) and there is a slight difference between signals B and C (start), and in this case, The current video signal A, which has almost no difference from the signal B, is output as an interpolation signal. In addition, in the case of D-1 and Dcs-0, the signal S is output as a 1H delayed signal furnace interpolation signal with almost no difference between the signal S and the signal B.

The same idea applies when the difference between signals A and B and the difference between signals B and C become large. For example, D-D
-0 and DCL-DCM-", the signal A is applied to AL AM, and conversely, when DAL "DAM"' is
When L=DoM-0, signal C is employed as the interpolation signal. Also, DAL”=DAM”=”DA
In the case of s"" 1 and D-0, DcM-Dcs-1, the mixing ratio of the signal AL is 3/4. The mixing ratio of signal C is 1/4.

In this way, the current video signal A of the current field and the 1H delayed delay signal filter, whichever has the smallest difference from the 2838 delayed signal B of the previous field, are mixed at a larger ratio (including 1), so the movement of one image is The occurrence of flickering is reduced as much as possible (a large difference from signal B means that there is large movement). This interpolation filter is suitable for creating interpolation signals for moving images.

A specific example of the mixing circuit 32 that achieves the above-mentioned mixing process is shown in the ninth example.
As shown in the figure.

This mixing circuit includes a coefficient switching circuit 51 that mixes input signals A and C under the control of a control signal S2 (the mixed output is α1), and an arithmetic average α2− (A+
C) with an adder circuit 52 which takes /2.

These circuits 51. , 52 outputs α 1 and 52 according to the control signal S1 (the selected output is α). The output signal of the changeover switch 53 becomes an adaptive interpolation signal. The changeover switch 53 is controlled by the control signal S1 (0 or 1).
As shown as 0.1 adjacent to switch 53,
Switching is controlled. Although the switch 53 is shown as a contact point, it goes without saying that it is constituted by a semiconductor element or the like. These matters also apply to other changeover switches described later.

A specific example of the configuration of the coefficient switching circuit 51 is shown in FIG. The output signal α1°α2.α) is shown in FIG.

The configuration and operation of the coefficient switching circuit 51 are clear from FIG. 10 and FIG. TI, but will be briefly explained. This circuit is A/4, 3A/4. It includes a circuit that creates C/4°3C/4, a changeover switch that changes these signals including inputs A and C, and an addition circuit that adds the switching results.

A signal representing 3A/4 is created by the 1/2 coefficient multiplier f31a, the 1/4 coefficient multiplier 82a, and the adder circuit 63a.

Either A or 3A/4 is selected by the changeover switch 64a. 1/4 by the changeover switch 65a
Either the signal representing A/4 or the signal representing 0, which is the output of the coefficient multiplier 82a, is selected. These changeover switches 84a and 85a are controlled by the LSB of the control signal S2. Either one of the outputs of the changeover switches 84a and 135a is selected by the changeover switch 88a. This changeover switch 66a is controlled by the MSB of the control signal S2.

1/2 coefficient unit 61b and 1. A signal representing 3C/4 is created by the /4 coefficient unit 1j2b and the adder circuit 63b. Either C or 3C/4 is selected by the changeover switch 64b. By the changeover switch 85b, 1/
Either the signal representing C/4, which is the output of the 4-coefficient multiplier 62b, or the signal representing 0 is selected. These changeover switches 64b and 65b are connected to the NOT circuit 8 of the control signal S2.
fi is controlled by the LSB inverted by 8b. Either one of the outputs of the changeover switches 64b and 65b is selected by the changeover switch 6Bb. This changeover switch 86b is controlled by the MSB of the control signal S2 which is inverted by the NOT circuit 68a.

The output signals of the changeover switches 66a and 61 are added by an adder circuit 67 to form an output signal a1.

Nonlinear processing circuits 7 and 17 can have the same configuration, and specific configuration examples thereof are shown in FIGS. 12 and 1.
This will be explained with reference to Figure 3. FIG. 12 is a circuit diagram showing an example of the nonlinear processing circuits 7, 17. FIG. 13 is a graph showing the relationship between the human force difference signal 1F and the output signal of the nonlinear processing circuit 7.17.

As is clear from FIG. 13, the nonlinear processing circuit shown in FIG. 12 maintains the value of the human input X until the input Regardless of the output Z (hereinafter nonlinear processing circuit 7 or 17
Let Z be the signal output from ) is kept at zero. Human power
From a predetermined value to 2D, the level of 1 novel of input X and the level of output 2 are in a proportional relationship. Furthermore, input X is 2D
If this is the case, the output Z will be kept at a constant value DS up to 3D.

When the input X exceeds 3D, the output Z decreases linearly with a constant slope [7. When the input X is 4D or more, the output Z is kept at zero. In this way, this nonlinear processing circuit.

It is configured to generate an output 2 whose level changes in a trapezoidal manner as the level of the input X increases.

In addition to the component representing the vertical contour, the input difference signal X includes a noise component and a component representing image motion. It is considered that there are many noise components in the portion where the level of the input difference signal X is low. It is also considered that the level of the input difference signal X increases as the component representing motion increases. In the nonlinear processing circuit shown in Fig. 12, the output signal 2 is kept at zero when the level of the input Since it is intense, one edge is not emphasized by keeping the output signal Z at zero. This is an ideal nonlinear processing circuit for contour compensation that emphasizes the contour according to the level of the input signal when the level of the input X is in the range of D to 4D.

Referring to FIG. 12, the difference signal X input manually to the nonlinear processing circuit 7 or 17 is input to the absolute value circuit 71. Sign discrimination circuit 72
and is applied to the coefficient multiplier 73a in the first coefficient multiplier group 73. The absolute value circuit 71 converts the input difference signal X into an absolute value, and its output signal is applied to one input end f- of four comparators 78a to 78d in a comparator group 78, which will be described later. The sign discrimination circuit 72 discriminates whether the input difference signal is positive or negative, and the discrimination signal is given as a switching control signal to a switching circuit 77, which will be described later.

There are two coefficient units 73a and 7 in the first coefficient unit 1v'A.
3b is included. These coefficient units 73a, 73b
are both multiplied by input signal 1::coefficient S and output. One coefficient "573a" multiplies the input difference signal by a factor of 8 and provides signals representing Z and -SX to subtracters 80 and 81.

In this practical example, it is possible to switch the degree of edge enhancement into two levels, and for this purpose a threshold generation circuit 74 is provided that generates two types of threshold values, D1 and D2. These thresholds DI.

D2 is applied to two input terminals of the switching circuit 75, respectively. The switching circuit 75 is supplied with an external threshold selection signal specifying the degree of edge enhancement, and the threshold D1 or D2 is selected in accordance with this selection signal. The signal representing the selected threshold value D (the two types of threshold values D1 and D2 are collectively expressed as D) output from the switching circuit 75 is as follows.

Five coefficient units 76a, 78b in the second coefficient unit group 76
.

7[fe, 76d, 7Be and comparator 78a
is applied to the other input terminal of The coefficient multiplier 7Ba in the second coefficient multiplier group 76 multiplies the input threshold by 1, and the coefficient multiplier 713b multiplies the input threshold by -1 and outputs a signal representing them. be. Coefficient unit 7Ba,
The output signal of 76b is applied to two input terminals of switching circuit 77, respectively.

The switching circuit 77 performs switching based on the discrimination signal from the code discrimination circuit 72. That is, the switching circuit 77 selects the threshold value input from the coefficient unit 78a if the human force difference signal X determined by the sign discrimination circuit 72 is positive, and selects the threshold value input from the coefficient unit 78b if it is negative. do.

The threshold value or 10 selected by the switching circuit 77 is applied to the coefficient multiplier 73b in the first coefficient multiplier group 73, and
It is multiplied and given to the switching circuit 79 as z2-DS (D includes negative values) and also given to the coefficient multiplier 7Bf.

Coefficient units 78c, 78d, and 78e are switching circuits 75
Each signal representing the threshold value given by is doubled.

Multiply by 3, multiply by 4, comparators 78b, 78c, 78
d to the other input terminal. Furthermore, coefficient unit 7
8f multiplies the signal representing Z2-DS output from the coefficient multiplier 73b by four and supplies the resultant signal to the subtracter 81 as a signal representing 4DS.

In the subtracter 81, 4DS-SX is calculated.

A signal Z3 representing the result of this calculation is input to the switching circuit 79. Furthermore, a signal representing Z2-DS outputted from the coefficient unit 73b is input to the subtracter 80. 1 This subtracter 80 calculates 2l-SX-DS, and a signal z1 representing the result of this calculation is sent to the switching circuit. 79 will be manned.

On the other hand, in the comparators 78a to 78d in the comparator group 7B.

The absolute value input difference signal X and these comparators 78a~
The reference value (threshold value) given to 78d.

2D, 3D, and 4D), and a signal representing the results of these comparisons is input to the switching circuit 79 as a switching control signal. In response to this switching control signal, the switching circuit 79 changes the level of the input difference signal X.

If it is below the threshold, the O of the grounded Z4 terminal
output a level signal, and if D<X≦2D, Z, -
Outputs 8X-DS, and outputs signal Z when 2D<X≦3D.
2-DS is output, and if 3Dx≦4D, the signal Z3 is output.
-4DS-8X is output, and when X exceeds 4D, switching is made to output a 0 level signal of the grounded z4 terminal. Further, a signal for turning on and off the contour compensation circuit is given to the switching circuit 79, and when the on signal is given, the comparator circuit 79 performs the above operation according to the output of the comparator group 78, but when the off signal is given,
It is switched to the grounded z4 terminal, and the output Z becomes 0.

Effects of the Invention According to the present invention, as described above, the current video signal, the 1H delayed signal of the same field, and the 2H delay signal of the previous field.
An adaptive interpolation signal is created by inputting the 63H delayed signal and changing the mixing ratio of the current video signal and the 1H delayed signal according to the level difference between these signals. In particular, the degree of image movement is detected based on the level difference between the 283H delayed signal of the previous field and the current video signal and 1H delayed signal of the current field, and based on the detection result, the current video signal of the current field and the 1H delayed signal are detected. Since the signal is mixed with the signal, it is possible to prevent the occurrence of flickering that tends to occur when there is movement. The adaptive interpolation signal according to the present invention is particularly effective in improving the quality of moving images.

Further, according to the present invention, vertical contour enhancement processing is performed on the above-mentioned adaptive interpolation signal. That is, the level of the interfield difference signal of the interpolated signal is detected.

Nonlinear processing is performed on this inter-field difference signal according to the detected level. By adding the non-linearly processed inter-field difference signal to the adaptive interpolation signal, an adaptive interpolation signal with vertical contour compensation is finally obtained. In this manner, according to the present invention, an adaptive interpolation signal with proper vertical contour compensation for progressive scanning can be generated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the invention. FIG. 2 is a diagram showing the relationship between the current video signal, the 262H delay signal, and the 263H delay signal, and FIG. 3 is a diagram showing the relationship between the current video signal, the 1H delay signal, and the 263H delay signal. FIG. 4 is a block diagram showing the schematic configuration of the interpolation filter circuit, FIG. 5 is a circuit diagram showing the configuration of the comparison processing circuit, FIG. 6 is a diagram showing the comparison operation collectively, and FIG. 7 is the configuration of the decoding circuit. A circuit diagram showing. FIG. 8 is a diagram showing the decoding operation and mixing output together, FIG. 9 is a block diagram showing the configuration of the mixing circuit, and FIG.
The figure is a circuit diagram showing the configuration of the coefficient switching circuit, and FIG. 11 is a diagram collectively showing the operation of the mixing circuit. FIG. 12 is a circuit diagram showing an example of a nonlinear processing circuit. FIG. 13 is a graph showing the relationship between the interfield difference signal and the output signal of the nonlinear processing circuit. 1...262H delay circuit. 2.10...1H delay circuit. 3, 8.11. Ill...addition circuit. 4.12...1/2 coefficient unit. 5.15...Subtraction circuit. 7.17...Nonlinear processing circuit. 13...Interpolation filter circuit. 31... Comparison processing and decoding circuit. 32...Mixing circuit. that's all

Claims (4)

[Claims] (1) A first delay circuit that delays the input current video signal by 1H, a second delay circuit that delays the input current video signal by 263H, the input current video signal, and the 1H output from the first delay circuit. Adaptation is achieved by inputting the delayed signal and the 263H delayed signal output from the second delay circuit, and mixing the current video signal and the 1H delayed signal according to the comparison result of the levels of these three input signals. an interpolation filter circuit that creates and outputs an interpolated signal, an interfield difference signal creation circuit that creates and outputs an interfield difference signal of the interpolation signal, and an interfield difference signal output from the above interfield difference signal creation circuit. Then, a nonlinear processing circuit performs predetermined nonlinear processing for vertical contour compensation according to the level of the interfield difference signal, and an output signal of the nonlinear processing circuit is added to the adaptive interpolation signal to perform vertical contour compensation. A vertical contour compensation circuit for an interpolated signal, comprising: an adder circuit that outputs an interpolated signal subjected to . (2) The interpolation filter circuit detects the level difference between the current video signal and the 263H delayed signal and the level difference between the 263H delayed signal and the 1H delayed signal, and the output signal of the comparison processing circuit. The adaptive video signal is controlled by a decoding circuit that converts the signal into a mixing control signal, and a mixing control signal given from the decoding circuit, and mixes the current video signal and the 1H delayed signal at a predetermined ratio according to the above level difference. The interpolation signal vertical contour compensation circuit according to claim 1, comprising: a mixing circuit that creates and outputs an interpolation signal. (3) A line interpolation circuit in which the inter-field difference signal creation circuit creates and outputs a line interpolation signal that is an average signal of the current video signal and the video signal 1H before the current video signal, which corresponds to the line interpolation signal. A 1-field delay circuit that outputs the previous field video signal to the horizontal scanning line, and an inter-field difference signal representing the difference between the line interpolation signal and the previous field video signal output from the 1-field delay circuit is calculated and output. The vertical contour compensation circuit for an interpolated signal according to claim 1, further comprising a subtraction circuit that performs the following steps. (4) The nonlinear processing circuit for vertical contour compensation includes a first circuit that creates a first signal having a level proportional to the level of the interfield difference signal, and a first circuit that generates a first signal having a level proportional to the level of the interfield difference signal; a second circuit that creates a second signal with a constant level; a third circuit that creates a third signal whose level decreases as the level of the inter-field difference signal increases; The first and second signal levels are different.
, a comparison circuit that compares the signal with a third and fourth reference level and outputs a signal representing a comparison result; and a level of the inter-field difference signal is lower than or equal to a first reference level according to the output signal of the comparison circuit. When the signal is at zero level, when the signal is between the first reference level and the second reference level, the first signal is used, and when the signal is between the second reference level and the third reference level, the signal is at zero level. 2nd above
When the signal is between the third reference level and the fourth reference level, the third signal is selected, and when the signal is above the fourth reference level, the zero level signal is selected and output. The vertical contour compensation circuit for interpolation signals according to claim 1, comprising: a switching circuit;