JPH0310584A - Sequential scanning converter - Google Patents

Abstract

PURPOSE:To eliminate the phase deviation in the vertical direction and to improve an S/N by generating an arithmetic mean signal of two adjacent lines in one field of interlaced scanning and taking a difference between a video signal of a line of the other field and the same arithmetic mean. CONSTITUTION:Changeover circuits 4, 10 are connected respectively to a terminal TA in a 1st field of the interlaced scanning. Thus, an adder circuit 2 and a 1/2 coefficient device 3 generate a 1st arithmetic mean signal of two adjacent lines in the 1st field. The changeover circuits 4, 10 are switched respectively to a terminal TB from the terminal TA in a 2nd field. Then a subtraction circuit 11 outputs a 1st inter-field difference signal generated by using a video signal subjected to 1H delay from the input video signal and a 2nd arithmetic mean signal between a 262H delay signal and a 263H delay signal. Then the signal is used for noise reduction processing at a subtraction circuit 5 via a 1st nonlinear processing circuit 12.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to interpolation signals required for progressive scan conversion, in particular noise reduction and vertical contour compensation.
The present invention relates to a progressive scan conversion device that outputs an adaptive interpolation signal.

Conventional technologyIn response to demands for higher image quality in television receivers, IDTV
, EDTV, and other systems have been developed or realized. These systems perform sequential scanning (non-interlace scanning) in which the current video signal and the interpolation signal are alternately scanned at double the scanning speed, and therefore it is necessary to create an interpolation signal. This interpolation signal is created by interpolation between lines or interfields, but depending on the presence or absence of movement between the two images and its degree, interpolation between lines or interfields can be switched as appropriate, or the video signal between lines or fields can be mixed. It is said that it is preferable to change the ratio.

In addition, when creating an interpolation signal, flicker (line flicker)
It is desirable to devise ways to prevent this from occurring as much as possible.

On the other hand, in order to improve the sharpness of the two images, not only horizontal edge enhancement but also vertical edge enhancement is necessary.

Since the interpolation signal is a type of average value signal, it works in the direction of blurring one contour, so vertical contour compensation is an essential technique.

Vertical edge enhancement is generally performed by adding an inter-field difference signal or an inter-frame difference signal to the original signal, but it is necessary to take into account the degree of movement of one image. This is because the level of the difference signal mentioned above is related to the vertical contour when there is little or no movement, but as the movement increases, more difference components due to movement are included.

On the other hand, in video signal reproduction processing, noise reduction processing of the video signal is also essential. The basic idea of a noise reduction circuit is to take advantage of the fact that video signals have a strong correlation in the vertical direction with respect to adjacent horizontal scanning lines, extract the noise component by taking the line-to-line difference signal, and then remove this noise component. The purpose is to subtract the difference signal from the original video signal. Conventional field cyclic noise reducers are two-line noise reducers.
It uses field correlation.

In other words, the conventional noise reduction circuit converts the input video signal into 262
Delay 262H delay circuit and 1-man video signal to 2
63H delay 263H delay circuit and these 26
a switching circuit that switches the output signals of the 2H and 263H delay circuits for each field; a first subtraction circuit that outputs an inter-field difference signal by calculating the difference between the output signal of the switching circuit and the input video signal; a nonlinear processing circuit that detects the degree of movement in the vertical direction of the image according to the magnitude of the level of the difference signal, and extracts a noise component included in the inter-field difference signal according to the detected degree of movement; , and a second subtraction circuit that subtracts the noise component signal output from the nonlinear processing circuit from the input video signal.

Since conventional noise reduction circuits utilize two-line field correlation, they remove intermediate noise components between two adjacent fields.

A vertical phase shift occurred.

On the other hand, since noise reduction processing is a type of averaging processing, the shading of one image is averaged in the vertical direction, and clear boundaries may become blurred. Therefore, a vertical contour compensation circuit that emphasizes vertical contours is required.

Problems to be Solved by the Invention In the manner described above, there is provided a noise reduction circuit without phase shift in the vertical direction, a circuit that can create an interpolation signal that can prevent the occurrence of flickering, and a vertical contour compensation that is complementary to these circuits. Although circuits are required, providing these circuits separately would complicate the circuit configuration.

This invention achieves noise reduction without vertical phase shift, creates an interpolation signal from this noise-reduced video signal that takes into account the movement of one image and can prevent flickering, and It is an object of the present invention to provide a progressive scan conversion device which can perform appropriate vertical contour compensation according to the movement of the object and which can simplify the circuit configuration as much as possible.

Means for Solving the Problems A progressive scan conversion device according to the present invention converts an input video signal into one
a first 1H delay circuit that delays the input video signal by 1H; a first averaging circuit that receives the input video signal and the signal delayed by 1H by the first 1H delay circuit; and outputs an average signal of these input signals; Switching is performed between the delayed signal delayed by 1H by the 1H delay circuit and the output signal of the first averaging circuit, and when scanning one field, the output signal of the first averaging circuit is selected, and the output signal of the first averaging circuit is selected when scanning the other field. A first switching circuit that selects and outputs the 1H delay signal during scanning, a 262H delay circuit that delays the noise-reduced 1H delay signal by 262H, and a 263H delay circuit that delays the noise-reduced 1H delay signal by 263H. , above 2
62) Input the output signal of the I delay circuit and the output signal of the upper fB 2B3H delay circuit.

A second averaging circuit 1 that outputs an average signal of these output signals switches between the output signal of the 262H delay circuit and the output signal of the second averaging circuit, and when scanning one field, the 2B2H delay is applied. a second switching circuit that selects the output signal of the circuit and selects and outputs the output signal of the second averaging circuit during the other field scanning;
a first subtraction circuit that calculates the difference between the output signal of the first switching circuit and the output signal of the second switching circuit and outputs a first inter-field difference signal; output from the first subtraction circuit; a first nonlinear processing circuit that performs predetermined nonlinear processing for noise reduction on the first inter-field difference output signal; a second subtraction circuit that calculates and outputs the noise-reduced video signal as a noise-reduced video signal; a second 1H delay circuit that delays the noise-reduced video signal output from the second subtraction circuit by 1H;
a third averaging circuit that inputs the noise-reduced video signal output from the second subtraction circuit and the signal delayed by 1H by the second 1H delay circuit, and outputs an average signal of these input signals; , calculates the difference between the output signal of the 283H delay circuit and the output signal of the third averaging circuit, and calculates the second
a third subtraction circuit that outputs an inter-field difference signal; and a noise-reduced current video signal output from the second subtraction circuit.

The 263H delay signal outputted from the 263H delay circuit and the 1H delay signal outputted from the second 1H delay circuit are input, and the noise reduction effect is determined according to the comparison result of the levels of these three input signals. An interpolation filter circuit that creates and outputs an adaptive interpolation signal by mixing a video signal and a 1H delayed signal, and a second interfield difference signal output from the third subtraction circuit. a second nonlinear processing circuit that performs predetermined nonlinear processing for vertical contour compensation according to the level of the difference signal; and noise reduction by adding the output signal of the second nonlinear processing circuit to the adaptive interpolation signal. The present invention is characterized in that it includes a first adder circuit that outputs an interpolated signal subjected to vertical contour compensation.

The interpolation filter circuit is a comparison processing circuit that detects the level difference between the noise-reduced current video signal and the noise-reduced 263H delayed signal and the level difference between the noise-reduced 263H delayed signal and the noise-reduced 1H delayed signal, respectively; A decoding circuit converts the output signal of the comparison processing circuit into a mixing control signal, and is controlled by a mixing control signal given from the decoding circuit, and a noise-reduced current video signal and a noise-reduced 1
It is composed of a mixing circuit that outputs an adaptive interpolation signal by mixing the H-delayed signal at a predetermined ratio according to the above level difference.

According to the present invention, an input video signal is delayed by 1H by the 1H delay circuit, and a signal (first average value signal) representing the average value of this delayed signal and the input video signal is created. In one field scanning period in interlaced scanning, a signal delayed by 2B2H from a video signal delayed by 1H is subtracted from the first average value signal.

A first inter-field difference signal is obtained. This first interfield difference signal is subjected to nonlinear processing for noise reduction in a first nonlinear processing circuit.

Since it is subtracted from the video signal delayed by 1H, the noise component of the input video signal is removed. In the other field scanning period, a signal (second average value signal) is created. and 1
A first inter-field difference signal is obtained by subtracting the second average value signal from the H-delayed video signal, and this first inter-field difference signal is similarly subjected to nonlinear processing. , is subtracted from the input video signal, so
Noise components of the input video signal will be removed.

The current video signal with noise reduced in this way.

The noise-reduced 1H delayed signal of the same field and the noise-reduced 263H delayed signal of the previous field are input, and depending on the level difference between these signals (that is, taking into account the movement of the image), the current video signal and 1H By changing the mixing ratio with the delayed signal (without using the 263H delayed signal), a noise-reduced adaptive interpolation signal is created. This adaptive interpolation signal is subjected to vertical contour enhancement processing. That is, a signal (third average value signal) representing the average value of the noise-reduced current video signal and the noise-reduced 1H delayed signal is created, and this third average value signal and the above-mentioned noise-reduced 263H delayed signal are combined. A second inter-field difference signal is obtained by taking the difference between the two fields. This second inter-field difference signal is applied to the second non-linear processing circuit, and non-linear processing for vertical contour enhancement is applied thereto in accordance with the level of the second inter-field difference signal. By adding the output signal of this second nonlinear processing circuit to the adaptive interpolation signal, a vertical contour-compensated adaptive interpolation signal is finally obtained.

Embodiment FIG. 1 shows a progressive scan converter including a noise reduction circuit (field recursive noise reducer) and a vertical contour compensation circuit. This progressive scan conversion device performs vertical contour compensation on both the current video signal and the interpolation signal created therefrom, and is characterized in that a portion of one circuit can be shared. Also, Figures 2 and 3 show the relationship between the input video signal and the delayed video signal, and the solid line in Figure 2 indicates the horizontal scanning line of the first field. Each horizontal scanning line of the second field is shown. The broken lines in FIG. 2 indicate the horizontal scanning lines of the second field, and the broken lines in FIG. 3 indicate the horizontal scanning lines of the first field. In addition, in these figures, the video signal delayed by 1H from the single-handed video signal is indicated by a double circle a.
t.

By a, b, b2, the video signal (i.e., the input video signal) which is the same field as the manual video signal and which is 1H advanced from the above-mentioned delayed video signal is the delayed signal in a different field by the black circle indicated by -1H. are respectively represented by white circles indicated by 262H and 283H.

First, the noise reduction circuit will be explained.

In Figure 1, a video signal (Y/C
The luminance signal after separation) is given to a first 1H delay circuit 1 and an adder circuit 2, respectively.

The signal delayed by the 1H delay circuit 1 is sent to the adder circuit 2.
The signal is applied to the TB terminal of the switching circuit 4 and the second subtraction circuit 5, respectively. In addition circuit 2, input video signal and 1H
The delayed video signal is added and applied to the 1/2 coefficient unit 3. An arithmetic average signal of the input video signal and the video signal delayed by 1H is created by the adder circuit 2 and the 1/2 coefficient unit 3 (first averaging circuit), and this signal is sent to the TA terminal of the first switching circuit 4. Given.

On the other hand, the output signal of the subtraction circuit 5 is applied as a noise-reduced video signal to an interpolation filter circuit 28 and a vertical contour emphasizing circuit, as will be described later, and also to a 2B2H delay circuit 6. The output signal of the 262H delay circuit 6 is sent to the 1H delay circuit 7. Addition circuit 8 and second switching circuit 1
0 to the TA terminals, respectively. Signal further delayed by 1H by 1H delay circuit 7 (283H delayed signal)
is applied to the adder circuit 8. 1 in the next stage of the adder circuit 8
/2 coefficient unit 9 is connected. Adder circuit 8 and 1/2
A second averaging circuit is configured by the coefficient unit 9, whereby a signal representing the arithmetic average value of the video signal delayed by 262H and the video signal delayed by 263H is applied to the TB terminal of the second switching circuit 10. It will be done. Switching circuit 1
0 is switched between the TA terminal side and the TB terminal side for each field by a switching control signal as described later, and the signal selected by this switching is applied to the first subtraction circuit 11.

The first switching circuit 4 is also switched field by field by a switching control signal. The subtraction circuit 11 is also supplied with a signal selected by the switching circuit 4. In this subtraction circuit 11, the output signal of the second switching circuit 10 is subtracted from the output signal of the first switching circuit 4, and a first inter-field difference signal is output. This first inter-field difference signal is given to the first nonlinear processing circuit 12, where noise components are extracted. A specific example of the nonlinear processing circuit 12 will be described later, but it has characteristics as shown in FIGS. 14, 17, and 20, for example.

The noise component signal output from the nonlinear processing circuit 12 is
is applied to the subtraction circuit 5. By removing noise components from the input video signal in the subtraction circuit 5, a noise-reduced video signal is obtained.

In the first field of interlaced scanning, the switching circuit 4
．． 10 are respectively connected to the TA terminal.

Therefore, as shown in the left side of FIG.
A first arithmetic mean signal of the line (double circle at and -1H black circle) is created and applied to the positive input terminal of the subtraction circuit 11 via the switching circuit 4. Also, the video signal delayed by 2B2H (signal of the second field, double circle al and -
The white circle of 262H sandwiched between the black circle of 1H) is switching circuit 1.
0 and is applied to the negative input terminal of the subtraction circuit 11. In the subtraction circuit 11, a difference signal between these two input signals is obtained, which is passed through a first nonlinear processing circuit 12 and used for noise reduction.

In the second field, switching circuit 4 and switching circuit l
0 is switched from the TA terminal side to the TB terminal side. Double circle b on the left side of Figure 3, and the corresponding 2
Referring to the white circles 62H and 263H, the positive input terminal of the subtraction circuit 11 receives a video signal delayed by 1H from the input video signal via the switching circuit 4 (double circle b 2 shown in FIG. 3).
), but the negative side input terminal of the subtraction circuit 11 receives the 262H delayed signal and the 263H delayed signal (262H, 263H shown in FIG.
A second arithmetic mean signal of 3H (white circle) is applied via the switching circuit 10, respectively. A first inter-field difference signal created using these input signals is output from the subtraction circuit 11, passes through the first nonlinear processing circuit 12, and is used in the subtraction circuit 5 for noise reduction processing.

In the above description, in the first field, the switching circuit 4.
lO selects the signal given to the TA terminal side,
In the second field, the switching circuit 410 respectively
The signal given to the B terminal side is selected. However, in the present invention, the switching circuits 4.10 can also be controlled to switch in the opposite manner. That is, as shown on the right side of FIG. 2, in the first field, the switching circuit 4
, 10 are connected to the TB terminal, and in the second field, the switching circuit 4.10 is connected to the TA terminal as shown on the right side of Fig. 3.
Switch to terminal.

Next, the vertical contour compensation circuit for the current video signal will be explained.

A third inter-field difference signal for contour compensation of the current video signal is created by the fourth subtraction circuit 14. This subtraction circuit 14 receives a second arithmetic average of the noise-reduced video signal outputted from the second subtraction circuit 5 and the 262H delayed signal and the 263H delayed signal outputted from the second averaging circuit. A third inter-field difference signal is created by subtracting the second arithmetic mean signal from the noise-reduced video signal.

The third inter-field difference signal output from the fourth subtraction circuit 14 is input to the third nonlinear processing circuit 1B via a low-pass filter 15. The third interfield difference signal is a high frequency component in the vertical direction of the image (specifically, 15.7K
Hz signal and its high frequency). The low-pass filter 15 allows signals of about 0.5 MHz or IMHz or less to pass, thereby removing horizontal high frequency components (which are generally high frequency noise) from the third interfield difference signal. In this way, only the vertical signal component is input to the third nonlinear processing circuit 16.

An example of a specific configuration of the nonlinear processing circuit 16 will be described later, but it has characteristics as shown in FIG. A vertical contour compensation signal component to be emphasized is output accordingly.

The output signal of the third nonlinear processing circuit 16 is then given to the second addition circuit 17. This addition circuit 17 is also supplied with the above-described noise-reduced output video signal of the second subtraction circuit 5, and by adding the vertical contour compensation signal component to this video signal, a vertical contour compensated video signal is generated. (This is called the current video signal with respect to the interpolated signal) is the adder circuit 17
will be output from. This means that the rounding of the waveform caused in the vertical direction by the noise reduction processing is compensated for by the vertical contour enhancement.

Next, a circuit for generating an adaptive interpolation signal for progressive scan conversion and its vertical contour compensation circuit will be described.

The video signal whose noise has been reduced by the second subtraction circuit 5 is given to a second 1HH extension circuit 21 and an addition circuit 22, respectively. The output signal of the 1HH extension circuit 21 is sent to the adder circuit 22.
given to. Therefore, the noise-reduced video signal and its 1HH extended signal are added in the adder circuit 22, and further multiplied by 1/2 in the 1/2 coefficient unit 23 to generate a line interpolation signal. Adder circuit 22 and 1/2 coefficient unit 23 constitute a third averaging circuit.

The line interpolation signal output from the 1/2 coefficient unit 23 is the third
is applied to the subtraction circuit 24. This subtraction circuit 24 has 1
The 263H delayed signal (pre-field signal) output from the HH delay circuit 7 is input.

A second interfield difference signal of the interpolated signal is obtained by subtracting the line interpolated signal from the H.263H delayed signal. Since the line interpolation signal is the arithmetic mean of the current video signal and the 1HH extended signal, it is on the scanning line exactly corresponding to the 263H delayed signal.

The interpolation filter circuit 28 receives the noise-reduced current video signal outputted from the second subtraction circuit 5 (represented by the symbol A) and the 1HH extended signal outputted from the second 1HH extended circuit 21 (represented by the symbol A). (represented by code C) and the 263H delayed signal output from the 1HH delay circuit 7 (represented by code B)
is inputting. As will be described in detail later, the interpolation filter circuit 28 detects the level difference between signals A and B and the level difference between signals B and C, and divides the signals A and C into a predetermined ratio according to the detection results. (signal B is not mixed) to create and output an adaptive interpolation signal. This adaptive interpolation signal is applied to the first adder circuit 27.

The interfield difference signal of the interpolation signal output from the subtraction circuit 24 is applied to a second nonlinear processing circuit 26 via a low-pass filter 25. The vertical contour compensation component signal of the interpolation signal output from this nonlinear processing circuit 2B is output to the adder circuit 2B.
7 and is added to the adaptive interpolation signal provided from the interpolation filter circuit 28. In this way, the adder circuit 27 outputs a noise-reduced and vertical contour-compensated adaptive interpolation signal.

The specific configuration of the interpolation filter circuit 13 will be described with reference to FIGS. 4 to 11.

FIG. 4 shows a schematic configuration of the interpolation filter circuit 28. Interpolation filter circuit 28 includes a comparison processing and decoding circuit 31 and a mixing circuit 32. Current video signal A,
The 283H delayed signal B and the 1H delayed signal are applied to the color comparison processing and decoding circuit 31.

The mixing circuit 32 is supplied with the current video signal A and the 1H delayed signal color. The comparison processing and decoding circuit 31 generates a control signal S for controlling a changeover switch in the mixing circuit 32, which will be described in detail later, based on the comparison processing of these input signals A, B, and C.
1 and S2 are created and given to the mixing circuit 32.

The comparison processing and decoding circuit 31 is composed of a comparison processing circuit and a decoding circuit. Details of the comparison processing circuit are shown in FIG. 5, and details of the decoding circuit are shown in FIG. 7.

In FIG. 5, the comparison processing circuit includes two subtraction circuits 33, 3.
Contains 4. One subtraction circuit 33 is manually operated 263
Subtract the current video signal A from the H delayed signal B.

The result is given to the absolute value circuit 35. Therefore, the absolute value circuit 35 outputs a signal having a level represented by lB-AI. The other subtraction circuit 34 subtracts the 1H delayed signal color from the 263H delayed signal B, and the result is given to the absolute value circuit 3B to be converted into an absolute value, so that from this circuit 36, the level of lB-CI is expressed. A signal is output.

The comparison processing circuit further includes seven comparators 37L.

Includes 37M, 37S, 38L, 38M, 38S and 39. Comparators 37L, 37M and 37
Reference levels R, R, and R are applied to the positive input terminal of S, respectively. The relationship is R>R>R8. The output signal IB-AI of the absolute value circuit 35 is applied to the negative input terminals of these 3M comparators 37L, 37M and 37S. Therefore, the output B-A I of the absolute value circuit 35
is smaller than the reference level R8, all comparators 37
The outputs DAs'DAM"AL of S, 37M, and 3γL become H level. This state is called "equivalent." Signal I
When the level of B-AI is between the reference levels R and R, only 3M of the outputs DAs are at the L level, and the other outputs DAM'AL are kept at the H level. This state is called "start". When the level of signal B-AI is between reference levels RM and Rt,
Outputs DAs and DAM go to L level, and output DAL goes to H level.
keep level. This state is called "Toyonaka". Signal IB-
When the AI level exceeds the reference level RL,
Output DA of all comparators 37L, 37M, 37S
L "AM" AS becomes L level. This state is called "insertion j." The above comparison operations are summarized in a table in FIG. 6. In this table, the H level of the output signal is represented by 0, and the L level of the output signal is represented by 1.

Similarly, reference levels R, R, and R are applied to the positive input terminals of comparators 38L, 38M, and 38S, respectively. These comparators 38L, 38M.

The negative input terminal of 38S receives the output signal B- of the absolute value circuit 3B.
CI is inputting. These comparators 38L, 38M
, 38S compares the level of the input signal IB-CI with reference levels R, R, and R, respectively, and outputs signals representing the comparison results. L "CM" C3
Output. This output signal. L "CM" C9 is also shown together in FIG.

The comparator 39 outputs the absolute value signal I B-A I and B-CI
It is used to compare the size of.

When IB-AI<IB-CI, an H level signal T1 (represented by 0) is output, and when the opposite is true, an L level signal T1 (represented by 1) is output. This signal T
1 is not particularly used in the decoding circuit of this embodiment (FIG. 7).

The AND circuit 40 connects the output DA8 of the comparator 37S and the comparator 3.
When the outputs Dcs of 8S are both at H level, that is, when the signals I B-A I and I B-CI are both small (when there is almost no difference between signals A, B, and C), the H level ( A signal T2 (represented by code 0) is output.

Output signals D , D , D , T 2 , D representing the above-mentioned comparison results of the comparison processing circuit (FIG. 5)
ct.

AL AM AS DCM"C3 is given as an input signal to the decoding circuit shown in FIG. (MSB and LSB
(consisting of 2 bits), as shown in FIG.

It is configured by a combination of EX-OR circuits 41g, 41b, 41c and OR circuits 42a, 42b.

The operation of this decoding circuit, ie, the relationship between its input signals and output signals, is shown in the form of a table in FIG. Also in Figure 8. The output mixed signal of the mixing circuit 32 whose mixing ratio is controlled by the signals Sl and S2 (interpolation filter circuit 2
8 output adaptive interpolation signal) is also shown. Here, the mixed signal expressed in the form of a fraction represents the mixed state of the input signals A, :C in the mixing circuit 32. For example, (A
+C)/2 represents the arithmetic mean of input signals A and C.

In FIG. 8, the mixing ratio of input signals A and C is:

It is determined according to the difference between signals A, C and signal B.

That is, of the input signals A and C, the one with a smaller difference from the signal B is used at a larger mixing ratio.

For example, the columns D As -0 and Dcs-0 in the top row represent the case where the difference signals I B-A I and I B-CI are both extremely small (and are equivalent), and in this case, the current video signal A and the 1H delay Arithmetic mean signal of delayed signal color (A+C)
/2 is output as an adaptive interpolation signal (line interpolation). Also, in the case of DAs-〇Big Do8-1, signals A and B
There is almost no difference between signals B and C (equivalent) and there is a slight difference between signals B and C (starting), and in this case, signal B
The current video signal A, which has almost no difference between the current video signal A and the current video signal A, is output as an interpolation signal. Further, in the case of D=1, Dcs-0, the 1H delayed delayed signal is output as a 1H delayed signal furnace interpolation signal with almost no difference between the signal s and the signal B.

The same idea applies when the difference between signals A and B and the difference between signals B and C become large. For example, D-D
-0 and DCL-DCM=1, the signal A is applied to ^LAN, and conversely, when DAL=DAM”=1 and D
In the case of CL-DoM-0, signal C is employed as an interpolation signal. Also “AL”DAM””DAS”1
And in the case of D-0, DcM-Dcs-1, the mixing ratio of the signal AL is 3/4. The mixing ratio of signal C is 1/4.

In this way, the current video signal A of the current field and the 1H delayed signal filter, whichever has a smaller difference from the 263H delayed signal B of the previous field, are mixed at a larger ratio (including 1), so the movement of one image is The occurrence of flickering is reduced as much as possible (a large difference from signal B means that there is large movement). This interpolation filter is suitable for creating interpolation signals for moving images.

A specific example of the mixing circuit 32 that achieves the above-mentioned mixing process is shown in the ninth example.
As shown in the figure.

This mixing circuit includes a coefficient switching circuit 51 that mixes input signals A and C under the control of a control signal S2 (the mixed output is α1), and an arithmetic average α2− (A+
C) with an adder circuit 52 which takes /2.

It is composed of a changeover switch 53 that selects one of the outputs α 1 α of these circuits 51 and 52 according to the control signal S1 (the selected output is set to α). The output signal of the changeover switch 53 becomes an adaptive interpolation signal. The changeover switch 53 is controlled by the control signal Sl (◯ or 1) as indicated by 0 and 1 adjacent to the switch 53. Although the switch 53 is shown as a contact point, it goes without saying that it is constituted by a semiconductor element or the like. These matters also apply to other changeover switches described later.

A specific example of the configuration of the coefficient switching circuit 51 is shown in FIG. The output signal α1°α2.α) is shown in FIG.

Although the configuration and operation of the coefficient switching circuit 51 are clear from FIGS. 10 and 11, they will be briefly explained. This circuit is A/4.3A/4. It includes circuits that create C/4° and 3C/4 respectively, changeover switches that change over these signals including inputs A and C, and an addition circuit that adds up the 1-switch results.

A signal representing 3A/4 is created by the 1/2 coefficient multiplier f+La, the 1/4 coefficient multiplier 62a, and the adder circuit 83a.

Either A or 3A/4 is selected by the changeover switch 84a. 1/4 by the changeover switch 85a
Either the signal representing A/4 or the signal representing O, which is the output of the coefficient multiplier 62a, is selected. These changeover switches 84a and 65a are controlled by the LSB of the control signal S2. Either one of the outputs of the changeover switches 64a and 65a is selected by the changeover switch 66a. This changeover switch 66a is controlled by the MSB of the control signal S2.

A signal representing 3C/4 is created by the 1/2 coefficient unit aib, the 1/4 coefficient unit 62b, and the adder circuit 63b. Either C or 3C/4 is selected by the changeover switch 84b. The selector switch 65b selects either the signal representing C/4 or the signal representing 0, which is the output of the 1/4 coefficient multiplier 82b. These changeover switches 64b and 65b are controlled by the LSB of the control signal S2 which is inverted by the NOT circuit 68b. Either one of the outputs of the changeover switches B4b and 65b is selected by the changeover switch 86b. This changeover switch 66b
is controlled by the MSB of control signal S2, which is inverted by NOT circuit 88a.

The output signals of the changeover switches 68a and 66b are sent to the adder circuit B7.
are added to form the output signal α1.

Next, each nonlinear processing circuit 12, 16 and 26 will be explained.

First, a first specific example of the configuration of the first nonlinear processing circuit 12 will be described. FIG. 12 shows the first nonlinear processing circuit 1.
2 is a circuit diagram showing an example of No. 2. FIG. FIG. 13 is a graph showing the relationship between the level of the inter-field difference signal (hereinafter simply referred to as the difference signal, indicated by the symbol X) X input to the first nonlinear processing circuit 12 and the nonlinear coefficient of the nonlinear processing circuit 12. FIG. 14 is a graph showing the relationship between the input difference signal X and the output signal Y (hereinafter referred to as Y) of the nonlinear processing circuit 12.

As is clear from FIG. 14, in the nonlinear processing circuit shown in FIG. 12, the level of input X and the level of output Y are in a proportional relationship until input X reaches a predetermined value Δ; Then, the output Y is kept at a constant value ΔK. The input difference signal X includes a component representing image movement in addition to a noise component. When the component representing motion increases, the input difference signal
It is thought that the level of On the other hand, the level of the noise component can be considered to be approximately constant. Therefore, in this nonlinear processing circuit, when the level of the input X exceeds a predetermined value Δ, the level of the output Y representing the noise component is kept constant. This nonlinear processing circuit is characterized by a simple configuration.

Referring to FIG. 12, the difference signal X input to the nonlinear processing circuit 12 is the absolute value circuit 71. It is applied to the sign discrimination circuit 72 and the coefficient unit 73a in the first coefficient unit group 73.

The absolute value circuit 71 converts the input difference signal X into an absolute value,
The output signal is applied to one input terminal of a comparator 78, which will be described later. The sign discrimination circuit 72 discriminates whether the input difference signal X is positive or negative, and the discrimination signal is given as a switching control signal to a switching circuit 77, which will be described later.

The first coefficient unit group 73 includes two coefficient units 73a.

73b is included. These coefficient units 73a, 73
In both cases, the input signal is multiplied by a coefficient K and outputted. One coefficient unit 73a multiplies the input difference signal X by a coefficient,
Signals representing Y and -KX are applied to the next stage switching circuit 79.

In this embodiment, it is possible to switch the degree of noise reduction into two stages, and for this purpose, a threshold generation circuit 74 is provided that generates two types of thresholds: Δ, Δ, and 2.
is provided. These threshold values Δl.

Δ2 is applied to two input terminals of the switching circuit 75, respectively. The switching circuit 75 is supplied with an external threshold selection signal specifying the degree of noise reduction, and the threshold value Δ1 or Δ2 is selected in accordance with this selection signal. The signal representing the selected threshold value Δ (the two types of threshold values Δ1 and Δ2 are collectively expressed as Δ) is output from the switching circuit 75.

Two coefficient units 76a and 7[1 in the second coefficient unit group 76
b and the other input terminal of comparator 78. One coefficient multiplier 76a in the second coefficient multiplier group 76 multiplies the input threshold value Δ by 1, and the other coefficient multiplier 76b multiplies the input threshold value Δ by −1, and outputs a signal representing them. This is what is output. The output signals of the coefficient multipliers 76a and 76b are applied to two input terminals of a switching circuit 77, respectively.

The switching circuit 77 performs switching based on the discrimination signal from the code discrimination circuit 72. That is, the switching circuit 77 selects the threshold value Δ input from the coefficient unit 78a if the input difference signal X determined by the sign determination circuit 72 is positive, and selects the threshold value −Δ input from the coefficient unit 78b if it is negative. do.

Threshold value Δ or −Δ selected by switching circuit 77
is applied to the coefficient multiplier 73b in the first coefficient multiplier group) 3, multiplied by , and applied to the switching circuit 79 as Y2-ΔK (Δ includes negative values).

On the other hand, the comparator 78 compares the input difference signal X converted into an absolute value with a threshold value Δ1 or Δ2 given to the comparator 78. The comparator 78 switches the switching circuit 7 according to these magnitudes.
A switching control signal is given to 9. That is, if the input difference signal
KX, and if the input difference signal X is greater than the selected threshold, the switching circuit 79 outputs a signal Y2-ΔK. In addition, the signal that turns the noise reduction circuit on and off is the switching circuit 7.
9, and when the ON signal is applied, the switching circuit 79 performs the above operation according to the output of the comparator 78, but when the OFF signal is applied, the switching circuit 79 switches to the grounded Y3 terminal. , the output Y becomes 0.

Another specific example of the configuration of the first nonlinear processing circuit 12 for noise reduction will be described. FIG. 15 is a circuit diagram showing a second example of the first nonlinear processing circuit 12. Also the 16th
The figure shows the level of the interfield difference signal X and the nonlinear processing circuit 1.
2 is a graph showing the relationship between the 17th nonlinear coefficient and
The figure is a graph showing the relationship between the input difference signal X and the output signal Y of the nonlinear processing circuit 12.

As is clear from FIG. 17, in the nonlinear processing circuit shown in FIG. 15, the level of input X and the level of output Y are in a proportional relationship until input X reaches a predetermined value Δ, but when input Then, the output Y is kept at a constant value ΔK up to 2Δ. When the input X exceeds 2Δ, the output Y decreases linearly at a constant slope, and when the input X exceeds 3Δ, the output Y is kept at zero. In this way, this nonlinear processing circuit is configured to generate an output Y whose level changes in a trapezoidal manner as the level of the input X increases.

The input difference signal X includes a component representing image movement in addition to a noise component. It is considered that as the component representing motion increases, the level of the input difference signal X increases. 1st
In the nonlinear processing circuit shown in Figure 5, when the level of input It is set to zero so that no noise reduction processing is performed. Therefore, ideal noise reduction processing can be expected by using this nonlinear processing circuit.

Referring to FIG. 15, the difference signal X input to the first nonlinear processing circuit 12 is the absolute value circuit 71. It is applied to the sign discrimination circuit 72 and the coefficient unit 73a in the first coefficient unit group 73. The absolute value circuit 71 converts the input difference signal
It is applied to one input terminal of 8a to 78c. The sign discrimination circuit 72 detects that the input difference signal X is positive.

It discriminates the negative sign, and the discrimination signal is given as a switching control signal to a switching circuit 77, which will be described later.

The first coefficient unit group 73 includes two coefficient units 73a.

73b is included. These coefficient units 73a, 73
In both cases, the input signal is multiplied by a coefficient K and outputted. One coefficient unit 73a multiplies the input difference signal X by a coefficient,
Signals representing Y and -KX are applied to the next stage switching circuit 79 and also to the subtracter 80.

In this embodiment as well, it is possible to switch the degree of noise reduction into two stages, and for this purpose the threshold generation circuit 7 generates 2FJ type thresholds Δ, Δ and 2.
4 is provided. These threshold values Δ1° and Δ2 are applied to two input terminals of the switching circuit 75, respectively. The switching circuit 75 is supplied with an external threshold selection signal specifying the degree of noise reduction, and the threshold value Δ1 or Δ2 is selected in accordance with this selection signal. Switching circuit 75
The signals representing the selected threshold value Δ (the two types of threshold values Δ1 and Δ2 are collectively expressed as Δ) output from the four coefficient multipliers 76a in the second coefficient multiplier group 76, 78
b.

78c, 76d and the other input terminal of comparator 78a. The coefficient multiplier 76a in the second coefficient multiplier group 7B multiplies the input threshold value Δ by 1, and the coefficient multiplier 7[ib multiplies the input threshold value Δ by −1, and outputs a signal representing them. It is something. The output signals of coefficient multipliers 78a and 76b are applied to two input terminals of switching circuit 77, respectively.

The switching circuit 77 performs switching based on the discrimination signal from the code discrimination circuit 72. That is, the switching circuit 77 selects the threshold value Δ inputted from the coefficient unit 78a if the input difference signal X determined by the sign determination circuit 72 is positive, and selects the threshold value −Δ inputted from the coefficient unit 76b if it is negative. do.

Threshold value Δ or −Δ selected by switching circuit 77
is applied to the coefficient multiplier Tab in the first coefficient multiplier group 73, multiplied by , and applied to the switching circuit 79 as Y2-ΔK (Δ includes a negative value), as well as to the coefficient multiplier 78e.

Coefficient multipliers 76c and 76d double and triple the signals representing the threshold value Δ given from switching circuit 75, respectively, and apply the results to the other input terminals of comparators 78b and 78c, respectively. Furthermore, the coefficient multiplier 78e triples the signal representing Y2-ΔK outputted from the coefficient multiplier 73b and supplies it to the subtracter 80 as a signal representing 3ΔK.

In the subtracter 80, -KX is calculated on 3Δ.

A signal Y3 representing the result of this calculation is input to the switching circuit 79.

On the other hand, in the comparators 78a to 78c in the comparator group 78.

The absolute value input difference signal X and these comparators 78a~
The reference value (threshold value Δ) given to 78c.

2Δ, 3Δ) are compared, and a signal representing the results of these comparisons is input to the switching circuit 79 as a switching control signal. In response to this switching control signal, the switching circuit 79 changes the level of the input difference signal X.

If the threshold value Δ is below, the signal y1-KX is output, and Δ
If X≦2∆, it outputs the signal Y2-∆K, and if 2∆≦X≦3∆, it outputs -Y1 as the signal Y3-3∆.
When X exceeds 3Δ, switching is made to output a 0 level signal from the grounded Y4 terminal. In addition, a signal to turn on and off the noise reduction circuit is given to the switching circuit 79, and when the on signal is given, the switching circuit 79
9 performs the above-described operation in response to the output of the comparator group 78, but when an off signal is applied, it is switched to the grounded Y4 terminal, and the output Y becomes O.

FIG. 18 is a circuit diagram showing a third example of the first nonlinear processing circuit 12. Further, FIG. 19 is a graph showing the relationship between the level of the input difference signal X and the nonlinear coefficient of this nonlinear processing circuit, and FIG. 20 is a graph showing the relationship between the input difference signal X and the output signal Y of the nonlinear processing circuit. It is a graph.

As is clear from FIG. 20, in the nonlinear processing circuit shown in FIG. 18, the level of input X and the level of output Y are in a proportional relationship until input X reaches a predetermined value Δ; Then, the output Y decreases linearly with a constant slope, and when the input X is 2Δ or more, the output Y is kept at zero. in this way,
This non-linear processing circuit is configured to generate an output Y whose level changes triangularly in response to an increase in the level of one person's power X. According to this nonlinear processing circuit, close to ideal noise reduction processing can be expected, and the configuration is simpler than that of the circuit shown in FIG. 15.

In FIG. 18, the same parts as those shown in FIG. 15 are given the same reference numerals, and only the different points will be described.

The output Y2 of the coefficient multiplier 73b is not input to the switching circuit 79. In the comparator group 78, the comparator 78c is not provided. A signal representing 2Δ output from the coefficient unit 76f is applied to a subtracter 80. Therefore, the subtracter 80 outputs a signal representing -KX at Y3-2Δ.

The switching circuit 79 operates as follows based on the switching control signal inputted from the comparator group 78. That is, the switching circuit 79
selects and outputs the signal Y1 until the input difference signal X reaches Δ,
When Δx≦2Δ, a signal Y3 is output, and when X exceeds 2Δ, a zero level signal Y4 is output. In this way, the characteristics shown in FIGS. 19 and 20 are obtained.

Next, specific configuration examples of the second nonlinear processing circuit 26 and the third nonlinear circuit 16 will be described. The same circuit configuration can be used for the second nonlinear processing circuit 26 and the third nonlinear processing circuit 1B. A circuit diagram showing an example of the second nonlinear processing circuit 26 or the third nonlinear processing circuit 1B is shown in FIG. FIG. 22 is a graph showing the relationship between the difference signal input to the circuit 2B or 1B and the output signal. Hereinafter, the signal input to the second nonlinear processing circuit 26 or the third nonlinear processing circuit 16 will be indicated by the symbol Xo, and the signal output from the circuit 2B or 16 will be indicated by the symbol 2.

As is clear from FIG. 22, in the nonlinear processing circuit shown in FIG. 21, the output Z is kept at zero regardless of the value of the input Xo until the input Xo reaches a predetermined value. When the input X is from a predetermined value to 2D, the level of the input Xo and the level of the output 2 are in a proportional relationship. Furthermore, input X. When becomes 2D or more, the output Z is kept at a constant value DS up to 3D. Input X. is 3
When Xo exceeds D, the output Z decreases linearly with a constant slope, and when the input Xo exceeds 4D, the output Z is kept at zero. Thus, this nonlinear processing circuit has an input X. The output Zo is configured to generate an output Zo whose level changes in a trapezoidal manner as the level increases.

Input difference signal X. includes a component representing a vertical contour, a noise component, and a component representing image movement.

It is considered that there are many noise components in the portion where the level of the input difference signal Xo is low. Also, when the component representing movement increases, the input difference signal X. It is thought that the level of Second
In the nonlinear processing circuit shown in FIG. When the level of Z is below a predetermined value, there are many noise components, so the output signal
By keeping the output signal Z at zero, and since there is rapid movement when the level of human power Xo exceeds 4D, by keeping the output signal Z at zero,
Does not emphasize contours. And input X.

This is an ideal non-linear processing circuit for contour compensation that enhances contours according to the level of the input signal within the range of D to 4D.

Referring to FIG. 21, a difference signal X is input to the second nonlinear processing circuit 2B or the third nonlinear processing circuit 16.

is the absolute value circuit 81. It is applied to the sign discrimination circuit 82 and the coefficient unit 83a in the first coefficient unit group 83. Absolute value circuit 8
1 is the input difference signal X. is converted into an absolute value, and its output signal is sent to four comparators 88a to 88 in the comparator group 88, which will be described later.
11d. Sign discrimination circuit 8
2 is the input difference signal X. It determines the positive and negative sign of
The determination signal is given as a switching control signal to a switching circuit 87, which will be described later.

The first coefficient unit group 83 includes two coefficient units 83a.

83b is included. These coefficient units 83a, 83
In both cases, the input signal is multiplied by a coefficient S and output. One coefficient multiplier 83a receives the input difference signal X. is multiplied by a factor of 8 and a signal representing Z-SXo is applied to the next stage switching circuit 89 and also to the subtracter 90.91.

In this embodiment, it is possible to switch the degree of edge enhancement into two stages, and for this purpose, a threshold generation circuit 8 is provided which generates 2Fi threshold values D, D, and 2.
4 are provided. These threshold values D1 and D2 are applied to two input terminals of the switching circuit 85, respectively. The switching circuit 85 is supplied with an external threshold selection signal specifying the degree of edge enhancement, and the threshold D1 or D2 is selected in accordance with this selection signal. Switching circuit 85
The signal representing the selected threshold value D (the two types of threshold values D1 and D2 are collectively expressed as D) output from is.

Five coefficient units 86a, 88b in the second coefficient unit group 8B
1!8c, 86d, 8[ie and comparator 88
is applied to the other input terminal of a. Second coefficient unit group 86
The coefficient multiplier 86a multiplies the input threshold value by 1, and the coefficient multiplier 88b multiplies the input threshold value by -1 and outputs a signal representing them. coefficient unit 88a,
The output signal of 88b is applied to two input terminals of switching circuit 87, respectively.

The switching circuit 87 performs switching based on the discrimination signal from the code discrimination circuit 82. That is, the switching circuit 87 receives the input difference signal X determined by the sign determining circuit 82. If is positive, the threshold value inputted from the coefficient multiplier 86a is selected, and if negative, the threshold value -D given from the coefficient multiplier 88b is selected. The threshold value selected by the switching circuit 87 or -
D is given to the coefficient multiplier 83b in the first coefficient multiplier group 83,
The signal is multiplied by 8 and given to the switching circuit 89 as Z2-DS (D includes negative values) and also given to the coefficient multiplier 88f.

Coefficient units 88c, 88d, and 88e are switching circuits 85
Each signal representing the threshold value given by is doubled.

Multiply by 3, multiply by 4, comparators 88b, Hc, 88d
respectively to the other input terminal of . Furthermore, coefficient unit 8B
f is the signal representing Z2-DS outputted from the coefficient multiplier 83b, multiplied by 4 and applied to the subtracter 91 as a signal representing 4DS.

In the subtracter 91, 4DS-3Xo is calculated, and a signal Z3 representing the result of this calculation is input to the switching circuit 89.

Furthermore, Z output from the coefficient unit 83b is sent to the subtracter 9o.
2-A signal representing DS is input and the subtractor 90
Zl-3Xo-DS is calculated, and a signal Z1 representing the result of this calculation is input to the switching circuit 89.

On the other hand, in the comparators 88a to 88d in the comparator group 88.

Input difference signal X converted into absolute value. and these comparators 88a
The reference value (threshold value) given to ~811d.

2D, 3D, and 4D) are compared, and a signal representing the results of these comparisons is input to the switching circuit 89 as a switching control signal. In response to this switching control signal, switching circuit 89 outputs an input difference signal X. The level of.

If it is below the threshold, the grounded Z4 terminal becomes 0.
Output a level signal, D<X. If ≦2D, +, : outputs z -5xo-DS and returns 2D! If X≦3D, output signal Z2-DS.

0 If 3D<X≦4D, signal Z3-4DS-SX
is output, and when Xo exceeds 4D, switching is made to output a 0 level signal from the grounded Z4 terminal. In addition, the signal that turns on and off the contour compensation circuit is supplied to the switching circuit 8.
9, and when the ON signal is applied, the switching circuit 89 performs the above-described operation in accordance with the output of the comparator group 88.

When an off signal is applied, the Z4 terminal is switched to the ground, and the output Z becomes O.

Effects of the Invention According to this invention, an arithmetic mean signal of two adjacent lines in one field of interlaced scanning is created,
A first inter-field difference signal is obtained by taking the difference between the video signal of the line in the other field located between these two lines and the arithmetic mean signal. Since the noise component is removed from the input video signal using so-called 3-line field correlation, the 1-phase characteristics are improved and vertical phase shift is eliminated.

Moreover, a video signal with a high S/N ratio can be obtained.

Further, according to the present invention, the current video signal whose noise has been reduced as described above and the noise reduction 1H of the same field
The delayed signal and the noise-reduced 2θ3H delayed signal of the previous field are input, and a noise-reduced adaptive interpolation signal is generated by changing the signal mixing ratio of the current video signal and the 1H delayed signal according to the level difference between these signals. is created. In particular, the degree of image movement is detected based on the level difference between the 263H delayed signal of the previous field and the current video signal and 1H delayed signal of the current field, and the current video signal and 1H delayed signal of the current field are detected based on the detection result. By mixing these, it is possible to prevent the flickering that tends to occur when there is movement. The adaptive interpolation signal according to the present invention is particularly effective in improving the quality of moving images.

Further, according to the present invention, vertical contour enhancement processing is performed on the noise reduction adaptive interpolation signal. That is, the level of the second interfield difference signal for the interpolation signal is detected, and nonlinear processing is performed on this interfield difference signal according to the detected level. By adding the non-linearly processed inter-field difference signal to the adaptive interpolation signal, an adaptive interpolation signal with vertical contour compensation is finally obtained. In this way, according to the present invention, it is possible to generate an adaptive interpolation signal for progressive scanning that is appropriately vertical contour compensated and also subjected to noise reduction processing.

Furthermore, the 263H (or 262H) delay circuit (field memory) necessary for noise reduction processing, the same delay circuit necessary for interpolation signal generation, and the same delay circuit for vertical contour compensation are shared. Therefore, the circuit configuration becomes simpler. In addition, since the first nonlinear processing circuit for noise reduction and the second nonlinear processing circuit for contour enhancement are provided separately, each field difference signal is subjected to nonlinear processing according to its purpose. This makes it possible to always perform appropriate noise reduction and contour enhancement according to the movement of the two images.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an m-sequential scan converter according to the present invention. FIGS. 2 and 3 show the relationship between the input video signal and the delayed video signal. In FIG. 2, the horizontal scanning line in the first field is shown as a solid line. In FIG. 3, the horizontal scanning lines in the second field are shown by solid lines. FIG. 4 is a block diagram showing a schematic configuration of an interpolation filter circuit, FIG. 5 is a circuit diagram showing a configuration of a comparison processing circuit, and FIG. 6 is a diagram collectively showing the comparison operation. Figure 7 is a circuit diagram showing the configuration of the decoding circuit, Figure 8 is a diagram showing the decoding operation and mixing output together, Figure 9 is a block diagram showing the configuration of the mixing circuit, and Figure 10 is the coefficient switching circuit. FIG. 3 is a circuit diagram showing the configuration of. FIG. 11 is a diagram summarizing the operation of the mixing circuit. FIG. 12 is a circuit diagram showing a first example of the first nonlinear processing circuit for noise reduction, FIG. 13 is a graph showing the relationship between the level of the interfield difference signal and the nonlinear processing coefficient, and FIG.
The figure is a graph showing the relationship between the interfield difference signal and the output signal of the nonlinear processing circuit. FIG. 15 is a circuit diagram showing a second example of the first nonlinear processing circuit for noise reduction, FIG. 16 is a graph showing the relationship between the level of the interfield difference signal and the nonlinear processing coefficient, and FIG.
The figure is a graph showing the relationship between the interfield difference signal and the output signal of the nonlinear processing circuit. FIG. 18 is a circuit diagram showing a third example of the first nonlinear processing circuit for noise reduction, FIG. 19 is a graph showing the relationship between the level of the interfield difference signal and the nonlinear processing coefficient, and FIG.
The figure is a graph showing the relationship between the interfield difference signal and the output signal of the nonlinear processing circuit. FIG. 21 is a circuit diagram showing an example of the second nonlinear processing circuit or the third nonlinear processing circuit for vertical contour compensation;
FIG. 2 is a graph showing the relationship between the interfield difference signal and the output signal of the nonlinear processing circuit. 1, 7.21...1H delay circuit. 2, 8.17.22.27...addition circuit. 3. 9.23...1/2 coefficient unit. 4...first switching circuit. 5...Second subtraction circuit. 6...262H delay circuit. 10...Second switching circuit. 11...First subtraction circuit. 12...First nonlinear processing circuit. Step 4: Fourth subtraction circuit. 16...Third nonlinear processing circuit. 24...Third subtraction circuit 26...Second nonlinear processing circuit 28...Interpolation filter circuit. 31... Comparison processing and decoding circuit. 32...Mixing circuit. Below

Claims (1)

[Scope of Claims] (1) A first 1H delay circuit that delays an input video signal by 1H, which inputs the input video signal and the signal delayed by 1H by the first 1H delay circuit, and A first averaging circuit outputs an average signal, and switches between the delayed signal delayed by 1H by the 1H delay circuit and the output signal of the first averaging circuit. a first switching circuit that selects the output signal of the averaging circuit and selects and outputs the 1H delayed signal during the other field scanning; and a 262H delay circuit that delays the noise-reduced 1H delayed signal by 262H. a 263H delay circuit that delays the noise-reduced 1H delay signal by 263H; a second average that inputs the output signal of the 262H delay circuit and the output signal of the 263H delay circuit and outputs an average signal of these output signals; switching circuit between the output signal of the 262H delay circuit and the output signal of the second averaging circuit, selecting the output signal of the 262H delay circuit when scanning one field, and selecting the output signal of the 262H delay circuit when scanning the other field; a second switching circuit that selects and outputs the output signal of the second averaging circuit; a second switching circuit that calculates the difference between the output signal of the first switching circuit and the output signal of the second switching circuit; a first subtraction circuit that outputs an interfield difference signal; a first nonlinear circuit that performs predetermined nonlinear processing for noise reduction on the first interfield difference output signal output from the first subtraction circuit; a processing circuit; a second subtraction circuit that calculates the difference between the 1H delayed signal and the output signal of the first nonlinear processing circuit and outputs the result as a noise-reduced video signal; noise reduction output from the second subtraction circuit; a second 1H delay circuit that delays the video signal by 1H, a noise-reduced video signal output from the second subtraction circuit, and the second 1H delay circuit;
a third averaging circuit inputting a signal delayed by 1H by the delay circuit and outputting an average signal of these input signals; a third subtraction circuit that calculates a difference and outputs a second inter-field difference signal; a noise-reduced current video signal output from the second subtraction circuit; and a 263H delayed signal output from the 263H delay circuit. , the above second 1H
The 1H delayed signal output from the delay circuit is input, and an adaptive interpolation signal is created by mixing the noise-reduced current video signal and the 1H delayed signal according to the comparison result of the levels of these three input signals. and an interpolation filter circuit that outputs the subtraction circuit, and performs predetermined nonlinear processing for vertical contour compensation on the second interfield difference signal output from the third subtraction circuit according to the level of the interfield difference signal. The second thing to do
a nonlinear processing circuit; and a first addition circuit that adds the output signal of the second nonlinear processing circuit to the adaptive interpolation signal and outputs an interpolation signal subjected to noise reduction and vertical contour compensation. progressive scan converter. (2) The progressive scan conversion device according to claim (1), wherein the 263H delay circuit is composed of the 262H delay circuit and a third 1H delay circuit cascade-connected thereto. (3) The interpolation filter circuit detects the level difference between the current video signal and the 263H delayed signal and the level difference between the 263H delayed signal and the 1H delayed signal, and the output signal of the comparison processing circuit. The adaptive video signal is controlled by a decoding circuit that converts the signal into a mixing control signal, and a mixing control signal given from the decoding circuit, and mixes the current video signal and the 1H delayed signal at a predetermined ratio according to the above level difference. The progressive scan conversion device according to claim 1, further comprising a mixing circuit that creates and outputs an interpolation signal. (4) A fourth subtraction circuit that calculates the difference between the noise-reduced video signal output from the second subtraction circuit and the output signal of the second averaging circuit and outputs a third inter-field difference signal. , a third nonlinear processing circuit that performs predetermined nonlinear processing for vertical contour compensation on the third interfield difference signal output from the fourth subtraction circuit; Claim 1 further comprising: a second addition circuit that adds the output signal of the third nonlinear processing circuit to the noise-reduced video signal and outputs it as a video signal subjected to noise reduction and vertical contour compensation. ). (5) the first nonlinear processing circuit for noise reduction, a first circuit that creates a first signal having a level proportional to the level of the first inter-field difference signal; a second circuit that creates a second signal at a constant level regardless of the level of the inter-field difference signal; and a signal that compares the level of the first inter-field difference signal with a predetermined reference level and represents the comparison result. a comparison circuit that outputs a signal, and a comparison circuit that outputs the first signal when the level of the first inter-field difference signal is below the reference level, and outputs the second signal when the level of the first inter-field difference signal is equal to or higher than the reference level, according to the output signal of the comparison circuit. The progressive scan conversion device according to claim 1, comprising: a switching circuit that selects and outputs the respective signals; (8) the first nonlinear processing circuit for noise reduction, a first circuit that creates a first signal having a level proportional to the level of the first inter-field difference signal; a second circuit that creates a second signal at a constant level regardless of the level of the inter-field difference signal; and a third circuit that creates a third signal whose level decreases as the level of the first inter-field difference signal increases. a third circuit that controls the level of the first inter-field difference signal;
, a comparison circuit that compares the first inter-field difference signal with a second and third reference level and outputs a signal representing a comparison result; When the signal is below the reference level, the first signal is used, when the signal is between the first reference level and the second reference level, the second signal is used, and when the signal is between the second reference level and the third reference level. The sequential scanning according to claim 1, comprising: a switching circuit that selects and outputs the third signal when the level is between the third reference level and a zero level signal when the level is equal to or higher than the third reference level; conversion device. (7) the first nonlinear processing circuit for noise reduction, a first circuit that creates a first signal having a level proportional to the level of the first inter-field difference signal; a second circuit for creating a second signal whose level decreases as the inter-field difference signal increases; and comparing the level of the first inter-field difference signal with different first and second reference levels. , a comparator circuit that outputs a signal representing a comparison result; and a comparator circuit that outputs a signal representing a comparison result; a switching circuit that selects and outputs the second signal when the signal is between the first reference level and the second reference level, and a zero level signal when the signal is equal to or higher than the second reference level; The progressive scan conversion device according to claim 1. (8) The second or third nonlinear processing circuit for vertical contour compensation creates a first signal having a level proportional to the level of the second or third interfield difference signal. a second circuit for creating a second signal at a constant level regardless of the level of the second or third interfield difference signal; and increasing the level of the second or third interfield difference signal. a third circuit for creating a third signal whose level decreases as the level of the second or third inter-field difference signal increases;
a comparison circuit that compares with different first, second, third, and fourth reference levels and outputs a signal representing a comparison result;
When the level of the inter-field difference signal is below the first reference level, the zero level signal is
when the first signal is between the reference level of
When the signal is between the second reference level and the third reference level, the second signal is sent, and when the signal is between the third reference level and the fourth reference level, the third signal is sent. The progressive scan conversion device according to claim 1, comprising: a switching circuit that selects and outputs a signal having a zero level when the level is equal to or higher than the fourth reference level;