JPH02288552A - Noise reduction and vertical contour compensation circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit constitution by sharing a one field delay circuit for a noise reduction circuit and a vertical contour compensation circuit. CONSTITUTION:An adder circuit 2 and a 1/2 coefficient device 3 generate an arithmetic mean signal for an input video signal and a 1H delay signal and an adder circuit 8 and a 1/2 coefficient device 9 generate an arithmetic mean signal for a video signal retarded by 262H and a video signal retarded by 263H. A subtraction circuit 11 subtracts the output signal of a switching device 10 from an output signal of a switching device 4, the noise component is extracted by a nonlinear processing circuit 12 and it is eliminated from the input video signal at a subtraction circuit 5. An inter-field difference signal for contour compensation is generated by a subtraction circuit 14, a nonlinear processing circuit 16 outputs a vertical contour compensation signal to be emphasized in response to the level of the input signal and the video signal subjected to vertical contour compensation is outputted from an adder circuit 17 to compensate unsharpened waveform caused in the vertical direction by the noise reduction processing. Thus, the circuit constitution is simplified.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention provides a circuit that combines a noise reduction circuit (so-called noise reducer) for reducing noise components of a video signal and a circuit for vertical contour compensation (emphasis). The basic idea of conventional technology noise reduction circuits is to take advantage of the fact that video signals have a strong correlation in the vertical direction with respect to adjacent horizontal scanning lines, extract noise components by taking line-to-line difference signals, and eliminate this noise. The purpose is to subtract a difference signal containing the components from the original video signal. Conventional field recursive noise reducers utilize two-line field correlation.

A block diagram of a conventional noise reduction circuit using two-line field correlation is shown in FIG. Referring to this figure, an input video signal (luminance signal Y after Y/C separation) is applied to a first subtraction circuit 20 and a second subtraction circuit 5.

The output signal of the second subtraction circuit 5 is outputted to the output terminal as a video signal after noise reduction processing. Also, the output signal of this subtraction circuit 5 is 262H in order to be delayed by one field period.
The signal is applied to a delay circuit (field memory) 6 (H is one horizontal scanning period).

The signal delayed by 262H by the 262H delay circuit 6 is applied to the B terminal of the switching circuit 10 and the 1H delay circuit 7. 1
The signal applied to the H delay circuit 7 is further delayed by 1H, output, and applied to the A terminal of the switching circuit IO.

The switching circuit IO selects one part of the scanning screen based on the switching control signal.
The A terminal and B terminal are switched for each field, and the signal selected according to the switch.

It is fed back and given to the first subtraction circuit 20.

In the subtraction circuit 20, the input video signal is converted to the switching circuit 10.
The output signals of are subtracted and an inter-field difference signal is output. This interfield difference signal is given to the nonlinear processing circuit 12. The nonlinear processing circuit 12 detects the degree of movement in the vertical direction of the image according to the magnitude of the input field difference signal, and detects noise components included in the field difference signal according to the detected degree of movement. Output.

The noise component signal output from the nonlinear processing circuit 12 is
Since the noise component is subtracted from the input video signal, a video signal with reduced noise components is output from the output terminal.

FIG. 16 shows the horizontal scanning lines of the first field in interlaced scanning, and FIG. 17 shows the horizontal scanning lines of the second field with solid lines. In FIG. 16, the horizontal scanning line of the second field is indicated by a broken line,
Similarly, in FIG. 17, the horizontal scanning line of the first field is indicated by a broken line.

The switching circuit 10 is switched field by field by a switching control signal. There are two types of switching control methods.

In one of them, the A terminal is connected to the first field, and the B terminal is connected to the second field. The situation in this case is shown by the white circles and black circles shown on the left side in FIG. 1B and FIG. 17, respectively. That is, in these figures, the black circles a 1 + b 2 are human input video signals given to the input terminals of the noise reduction circuit;
, b2■ The white circles indicated by arrows 283H and 282H correspond to the input video signals of black circles a and b2, respectively.
B3H, 2B2H are delayed signals. That is, these white circles are signals appearing at the A terminal and the B terminal of the switching circuit IO, respectively.

In the subtraction circuit 20, the first field has a black circle at
By subtracting the corresponding 263H delayed video signal from the video signal of black circle b2, the corresponding 282H delayed video signal is subtracted from the video signal of black circle b2 in the second field. An inter-field difference signal is obtained.

In another switching control method, the B terminal is connected to the first field, and the A terminal is connected to the second field. The video signal at this time is on the right side of Figure 1B (black circle b
1 and the corresponding white circle 282H) and the right side of FIG. 17 (black circle a2 and the corresponding white circle 263H).

Problems to be Solved by the Invention As mentioned above, conventional noise reduction circuits utilize two-line field correlation, which means that they remove the intermediate noise component between two adjacent fields. A phase shift occurred.

On the other hand, since noise reduction processing is a type of averaging processing, the shading of one image is averaged in the vertical direction, and clear boundaries may become blurred. The vertical contour compensation circuit emphasizes the vertical contour, and this circuit also has the function of correcting the vertical blur caused by the noise reduction circuit.

As described above, the noise reduction circuit and the vertical contour compensation circuit have a mutually complementary relationship, but if these circuits were provided separately, the circuit configuration would become complicated. Also.

In both noise reduction processing and vertical contour compensation processing, it is necessary to fully consider image motion.

The present invention provides a noise reduction/vertical contour compensation circuit that achieves noise reduction without phase shift in the vertical direction, has a six-circuit configuration as simple as possible, and is capable of processing in consideration of image motion.

Means for Solving the Problems A noise reduction/vertical contour compensation circuit according to the present invention includes a 1H delay circuit that delays an input video signal by 1H, inputs the input video signal and a signal I Hligmed by the 1H delay circuit, and processes these signals. A first averaging circuit outputs an average signal of the input signals of the first averaging circuit, and switches between the input video signal and the output signal of the first averaging circuit, and selects the input video signal when scanning one field, and selects the input video signal when scanning the other field. a first switching circuit that selects and outputs the output signal of the first averaging circuit during field scanning; a 282H delay circuit that delays the input video signal by 262H; a 263H delay circuit that delays the input video signal by 283H; a second averaging circuit which inputs the output signal of the 262H delay circuit and the output signal of the 268H delay circuit and outputs an average signal of these output signals; an output signal of the 263H delay circuit and the second average; the output signal of the second averaging circuit is selected during one field scanning;
A second switching circuit selects and outputs the output signal of the 283H delay circuit during the other field scanning.

a first subtraction circuit that calculates the difference between the output signal of the first switching circuit and the output signal of the second switching circuit and outputs a first inter-field difference signal; output from the first subtraction circuit; subtracting the output signal of the first non-linear processing circuit from the first non-linear processing circuit which performs predetermined non-linear processing for noise reduction on the first inter-field difference output signal; a second subtraction circuit that outputs a noise-reduced video signal; a difference between the noise-reduced video signal output from the second subtraction circuit and the output signal of the second averaging circuit is computed; a third subtraction circuit that outputs a difference signal; a second nonlinear processing circuit that performs predetermined nonlinear processing for vertical contour compensation on the second interfield difference signal output from the third subtraction circuit; and an addition circuit that adds the output signal of the second nonlinear processing circuit to the noise-reduced video signal output from the second subtraction circuit and outputs the result as a video signal subjected to noise reduction and vertical contour compensation. It is characterized by having

According to the present invention, an input video signal is delayed by 1H by the 1H delay circuit, and a signal (first average value signal) representing the average value of this delayed signal and the input video signal is created. In one field scanning period in interlaced scanning, a first inter-field difference signal is obtained by subtracting a signal delayed by 263H from the single-handed video signal from the first average value signal. This first inter-field difference signal is subjected to nonlinear processing for noise reduction in the first nonlinear processing circuit, and then subtracted from the input video signal, so that noise components of the input video signal are removed. In the other field scanning period, a signal (second average value signal) representing the average value of a signal delayed by 262H and a signal delayed by 283H from the input video signal is created. Then, the second average value signal is subtracted from the input video signal.

A first inter-field difference signal is obtained, and this first inter-field difference signal is similarly subjected to non-linear processing and then subtracted from the input video signal, so that the noise component of the input video signal is removed. Become.

Furthermore, a second inter-field difference signal is obtained by taking the difference between the video signal whose noise has been reduced as described above and the second average value signal. This second inter-field difference signal is applied to the second non-linear processing circuit, and non-linear processing for vertical contour enhancement is applied thereto in accordance with the level of the second inter-field difference signal. Vertical edge enhancement is achieved by adding the output signal of this second nonlinear processing circuit to the above-mentioned noise-reduced video signal.

Embodiment FIG. 1 shows an embodiment of a noise reduction (field recursive noise reducer) and vertical contour compensation circuit according to the first invention. In this figure, the same components as those shown in FIG. 15 are given the same reference numerals.

2 and 3 show the relationship between the input video signal and the delayed video signal. The solid line in FIG. 2 indicates the horizontal scanning line of the first field, and the solid line in FIG. 3 indicates the horizontal scanning line of the second field. Each horizontal scanning line of the field is shown. Second
The broken line in the figure indicates the horizontal scanning line of the second field, and
The broken lines in the figure each indicate the horizontal scanning line of the first field. Furthermore, in these figures, the input video signal is double 9a, a, b, b2, and the 1H delayed signal in the same field as the single manual video signal is indicated by 1H, and the delayed signal in different fields is 282H, Each is represented by a white circle indicated by 283H.

The circuit shown in FIG. 1 includes, in addition to a noise reduction circuit and a vertical contour compensation circuit, a circuit for generating a line interpolation signal for progressive scan conversion. This line interpolation signal is also vertically edge-enhanced.

First, the noise reduction circuit will be explained.

In Figure 1, the video signal (Y/
The luminance signal after C separation) is processed by a 1H delay circuit 1° adder circuit 2.
The signal is applied to the B terminal of the switching circuit 4 and the second subtraction circuit 5, respectively. The signal delayed by the 1H delay circuit 1 is given to the adder circuit 2. In the adder circuit 2, the input video signal and the 1H delayed signal are added and provided to the 1/2 coefficient unit 3. An arithmetic mean signal of the input video signal and the 1H delayed signal is created by the adder circuit 2 and the 1/2 coefficient unit 3 (the first
averaging circuit), which is applied to the A terminal of the switching circuit 4.

On the other hand, the output signal of the subtraction circuit 5 is applied as a noise-reduced video signal to a vertical contour emphasizing circuit and also to a 282 H delay circuit 6, as will be described later. 262
The output signal of H delay circuit 6 is given to 1H delay circuit 7 and adder circuit 8, respectively.

The signal further delayed by 1H by the 1H delay circuit 7 is
One side is applied to the adder circuit 8, and the other side is applied to the A terminal of the switching circuit IO. A 1/2 coefficient unit 9 is connected to the next stage of the adder circuit 8. Adder circuit 8 and 1/2 coefficient unit 9
The second averaging circuit is configured by 26
A signal representing the arithmetic average value of the 2 H delayed video signal and the 283 H delayed video signal is applied to the B terminal of the switching circuit 10. As will be described later, the switching circuit 10 is switched between the A terminal side and the B terminal side for each field by a switching control signal, and the signal selected by this switching is applied to the first subtraction circuit 11.

The switching circuit 4 is also switched field by field by a switching control signal. The subtraction circuit 11 is also supplied with a signal selected by the switching circuit 4.

In the subtraction circuit 11, the output signal of the switching circuit 10 is subtracted from the output signal of the switching circuit 4, and a first inter-field difference signal is output. This first inter-field difference signal is applied to the first nonlinear processing circuit I2, where noise components are extracted. Specific examples of the nonlinear processing circuit 12 will be described later, but for example, FIGS.
It has the characteristics shown in Figure 4.

The noise component signal output from the nonlinear processing circuit 12 is given to the subtraction circuit 5. By removing noise components from the input video signal in the subtraction circuit 5, a noise-reduced video signal is obtained.

In the first field of interlaced scanning, the switching circuit 4
．． IO are each connected to the A terminal. Therefore, as shown on the left side of FIG. a
A first arithmetic mean signal of 1 and 1H (black circles) is created and applied to the positive input terminal of the subtraction circuit 11 via the switching circuit 4. Further, the video signal delayed by 263H (the signal of the second field, the white circle of 263H sandwiched between the double circle at and the black circle of 1H) passes through the switching circuit IO and is connected to the negative side input terminal of the subtraction circuit 11. given to. In the subtraction circuit 11, a difference signal between these two input signals is obtained, which is passed through a first nonlinear processing circuit 12 and used for noise reduction.

In the second field, switching circuit 4 and switching circuit 1
0 is switched from the A terminal side to the B terminal side. Double circle b on the left side of Figure 3 and the corresponding 262
Refer to the white circles of H and 263H.

An input video signal (double circle b2 shown in FIG. 3) is input to the positive input terminal of the subtraction circuit 11 via the switching circuit 4.

The negative input terminal of the subtraction circuit 11 receives a 262H delay signal and a 263H delay signal (262H, 283H shown in FIG.
The second arithmetic mean signals of (white circles) are respectively given via switching circuits IO. A first inter-field difference signal created using these input signals is output from the subtraction circuit 11, passes through the first nonlinear processing circuit 12, and is used by the subtraction circuit 5 for noise reduction processing.

In the above explanation, in the first field, the switching circuit 4,
10 selects the signal given to the A terminal side, and in the second field, the switching circuit 4 and IO select the signal given to the A terminal side, respectively.
Selects the signal given to the terminal side. However, in this invention, the switching circuit 4. It is also possible to control the switching of lO. That is, as shown on the right side of FIG. 2, in the first field, the switching circuit 4.
10 is connected to the B terminal, and in the second build, the switching circuit 4. Switch to to A terminal.

Next, the vertical contour compensation circuit will be explained.

A second inter-field difference signal for contour compensation is generated by a third subtraction circuit 14. This subtraction circuit 14 receives a second arithmetic average of the noise-reduced video signal outputted from the second subtraction circuit 5 and the 262H delayed signal and the 263H delayed signal outputted from the second averaging circuit. A second inter-field difference signal is created by subtracting the second arithmetic mean signal from the noise-reduced video signal.

The second inter-field difference signal output from the third subtraction circuit 14 passes through the first low-pass filter 15 and is input to the second nonlinear processing circuit 1B. The second interfield difference signal is a high frequency component in the vertical direction of the image (specifically, 15.
7KHz signal and its high frequency). The low-pass filter 15 passes signals of approximately 0.5 MHz or I MHz or less, and thereby removes horizontal high frequency components (which are generally high frequency noise) from the second interfield difference signal. Ru. In this way, only the vertical signal component is input to the second nonlinear processing circuit 16. An example of a specific configuration of the nonlinear processing circuit IB will be described later, but for example, it has characteristics as shown in FIG. A vertical contour compensation signal component to be emphasized is output accordingly.

The output signal of the second nonlinear processing circuit 16 is then applied to the adder circuit 1.
7 is given. This addition circuit 17 is also supplied with the above-described noise-reduced output video signal of the second subtraction circuit 5, and by adding the vertical contour compensation signal component to this video signal, a vertical contour compensated video signal is generated. (This is called the current signal with respect to the interpolated signal) is output from the adder circuit 17. This means that the rounding of the waveform caused in the vertical direction by the noise reduction processing is compensated for by the vertical contour enhancement.

Next, a vertical contour compensation circuit for line interpolation signals for progressive scan conversion will be described.

The video signal whose noise has been reduced by the second subtraction circuit 5 is 1
H delay circuit 21. It is applied to adder circuits 22 and 28. 1
The output signals of the H delay circuit 21 are applied to adder circuits 22 and 28, respectively. Therefore, the noise-reduced video signal and its 1H delayed signal are added in the adding circuit 22, and further multiplied by 1/2 in the 1/2 coefficient unit 22 to generate a line interpolation signal.

Similarly, a line interpolation signal is created by an adder circuit 28 and a 1/2 coefficient unit 29. These 1H delay circuits 21. Addition circuits 22, 28 and 1/2 coefficient units 23, 2
9 constitutes a circuit for creating a line interpolation signal.

The interpolation signal output from the 1/2 coefficient unit 23 is given to a fourth subtraction circuit 24. The 263H delay signal output from the 1H delay circuit 7 is also input to the subtraction circuit 24, and the third interfield difference signal is obtained by subtracting the interpolation signal from the 263H delay signal.

The third inter-field difference signal output from the fourth subtraction circuit 24 is similarly applied to the third nonlinear processing circuit 26 via the second low-pass filter 25. The vertical contour compensation component signal of the interpolation signal output from the nonlinear processing circuit 26 is input to the second adder circuit 27, and the l/2 coefficient multiplier 2
It is added to the line interpolation signal given from 9. In this way, the adder circuit 27 outputs a line interpolation signal that has undergone vertical contour compensation.

Next, each nonlinear processing circuit 12, 16 and 26 will be explained.

First, a first specific example of the configuration of the first nonlinear processing circuit 12 will be described. FIG. 4 shows the first nonlinear processing circuit 12.
It is a circuit diagram showing an example. Further, FIG. 5 is a graph showing the relationship between the level of the inter-field difference signal (hereinafter simply referred to as the difference signal and indicated by the symbol X) input to the first nonlinear processing circuit 12 and the nonlinear coefficient of the nonlinear processing circuit 12. and
FIG. 6 is a graph showing the relationship between the input difference signal X and the output signal Y (hereinafter referred to as Y) of the nonlinear processing circuit 12.

As is clear from FIG. 6, the nonlinear processing circuit shown in FIG.
Although the levels of are in a proportional relationship.

When the input X exceeds a predetermined value Δ, the output Y is kept at a constant value ΔK. The input difference signal X includes a component representing image movement in addition to a noise component. It is considered that as the component representing motion increases, the level of the input difference signal X increases. On the other hand, the level of the noise component can be considered to be approximately constant. Therefore, in this nonlinear processing circuit, when the level of the input X exceeds a predetermined value Δ, the level of the output Y representing the noise component is kept constant. This nonlinear processing circuit is characterized by a simple configuration.

Referring to FIG. 4, the difference signal X input to the nonlinear processing circuit 12 is the absolute value circuit 31. It is applied to the sign discrimination circuit 32 and the coefficient multiplier 33a in the first coefficient multiplier group 33.

The absolute value circuit 31 converts the input difference signal X into an absolute value,
The output signal is applied to one input terminal of a comparator 38, which will be described later. The sign discrimination circuit 32 discriminates whether the input difference signal X is positive or negative, and the discrimination signal is given as a switching control signal to a switching circuit 37, which will be described later.

The first coefficient unit group 33 includes two coefficient units 33a.

33b is included. These coefficient units 33a, 33
In both cases, the input signal is multiplied by a coefficient K and outputted. One coefficient unit 33a multiplies the input difference signal X by a coefficient,
Signals representing Y and -KX are applied to the next stage switching circuit 39.

In this embodiment, it is possible to switch the degree of noise reduction into two stages, and for this purpose a threshold generation circuit 34 is provided that generates two types of thresholds, Δ2 and Δ2. These threshold values Δ1° and Δ2 are applied to two input terminals of the switching circuit 35, respectively. The switching circuit 35 is supplied with an external threshold selection signal specifying the degree of noise reduction, and the threshold value Δ1 or Δ2 is selected in accordance with this selection signal. The signal representing the selected threshold value Δ (the two types of threshold values Δ1 and Δ2 are collectively expressed as Δ) is output from the switching circuit 35.

Two coefficient units 36a and 36b in the second coefficient unit group 3B
and the other input terminal of comparator 38.

One coefficient multiplier 36a in the second coefficient multiplier group 36 multiplies the input threshold value Δ by 1, and the other coefficient multiplier 38b multiplies the input threshold value Δ by −1, and outputs a signal representing them. This is what is output. The output signals of the coefficient multipliers 86m and 36b are applied to two input terminals of the switching circuit 37, respectively.

The switching circuit 37 performs switching based on the discrimination signal from the code discrimination circuit 32. That is, the switching circuit 37 selects the threshold value Δ input from the coefficient unit 36a if the input difference signal X determined by the sign determination circuit 32 is positive, and selects the threshold value −Δ input from the coefficient unit 38b if it is negative. do.

Threshold value Δ or -Δ selected by switching circuit 37
is applied to the coefficient multiplier 33b in the first coefficient multiplier group 33, multiplied by , and applied to the switching circuit 39 as Y2-ΔK (Δ includes negative values).

On the other hand, the comparator 38 compares the input difference signal X converted into an absolute value with a threshold value Δ1 or Δ2 given to the comparator 38. The comparator 38 switches between the switching circuits 3 and 3 depending on the magnitude of these.
A switching control signal is given to 9. That is, if the input difference signal
KX, and if the input difference signal X is greater than the selected threshold, the switching circuit 39 outputs a signal Y2-ΔK. In addition, the signal that turns the noise reduction circuit on and off is the switching circuit 3.
9, and when an ON signal is applied, the comparator circuit 39 performs the above operation according to the output of the comparator 38, but when an OFF signal is applied, it is switched to the grounded Y3 terminal. , the output Y becomes 0.

Next, specific configuration examples of the second nonlinear processing circuit 1B and the third nonlinear circuit 2B will be described. The same circuit configuration can be used for the second nonlinear processing circuit 16 and the third nonlinear processing circuit 2B. A circuit diagram showing an example of the second nonlinear processing circuit 1B or the third nonlinear processing circuit 2B is shown in FIG. FIG. 8 is a graph showing the relationship between the difference signal input to the circuit 16 or 26 and the output signal. Hereinafter, the signal input to the second nonlinear processing circuit 16 or the third nonlinear processing circuit 2B is indicated by the symbol Xo, and the signal output from those circuits 16 or 26 is indicated by the symbol Z.

As is clear from FIG. 8, in the nonlinear processing circuit shown in FIG. 7, the output Z is kept at zero regardless of the value of the input Xo until the input Xo reaches a predetermined value. Input X is 2D from the predetermined value
Until then, the level of the input Xo and the level of the output Z are in a proportional relationship. Furthermore, input X. When becomes 2D or more, 3D
The output Z is kept at a constant value DS until. When the input Xo exceeds 3D, the output Z decreases linearly with a constant slope, and the two-man power
When o is 4D or more, the output Z is kept at zero. in this way,
This nonlinear processing circuit has an input X. The output Zo is configured to generate an output Zo whose level changes in a trapezoidal manner as the level increases.

Human force difference signal X. includes a component representing a vertical contour, a noise component, and a component representing image movement.

It is considered that there are many noise components in the portion where the level of the input difference signal Xo is low. Also, when the component representing movement increases, the input difference signal X. It is thought that the level of 7th
In the nonlinear processing circuit shown in the figure, the input X. In the range where the level of input Don't do it. And one person power X.

This is an ideal non-linear processing circuit for contour compensation that enhances contours according to the level of the input signal within the range of D to 4D.

Referring to FIG. 7, the second nonlinear processing circuit 16 or the third
The difference signal X input to the nonlinear processing circuit 26 of.

is the absolute value circuit 41. It is applied to the sign discrimination circuit 42 and the coefficient multiplier 43a in the first coefficient multiplier group 43. Absolute value circuit 4
1 is the input difference signal X. is converted into an absolute value, and its output signal is sent to four comparators 411a to 411a in the comparator group 48, which will be described later.
48d. Sign discrimination circuit 4
2 is the human force difference signal X. It determines the positive and negative sign of
The determination signal is given as a switching control signal to a switching circuit 47, which will be described later.

The first coefficient unit group 43 includes two coefficient units 43a.

43b is included. These coefficient units 43a, 43
In both cases, the input signal is multiplied by a coefficient S and output. One coefficient unit 43a receives the input difference signal X. is multiplied by a factor of 8 and a signal representing Z-SXo is applied to the next stage switching circuit 49 and also to the subtracter 50.51.

In this embodiment, it is possible to switch the degree of edge enhancement into two levels, and for this purpose, a threshold generation circuit 44 is provided which generates two types of threshold values, D2 and ■.
is provided. These thresholds DI.

D2 is applied to two input terminals of the switching circuit 45, respectively. The switching circuit 45 is supplied with an external threshold selection signal specifying the degree of edge enhancement, and the threshold D1 or D2 is selected in accordance with this selection signal. The signal representing the selected threshold value D (the two types of threshold values D1 and D2 are collectively expressed as D) output from the switching circuit 45 is as follows.

Five coefficient units 46a, 48b in the second coefficient unit group 46
.

46c, 46d, 46e and the other input terminal of comparator 48a. The coefficient multiplier 46a in the second coefficient multiplier group 46 multiplies the input threshold by 1, and the coefficient multiplier 46b multiplies the input threshold by -1 and outputs a signal representing them. be. Coefficient unit 46a, 4
The output signals of 6b are applied to two input terminals of a switching circuit 47, respectively.

The switching circuit 47 performs switching based on the discrimination signal from the code discrimination circuit 42. That is, the switching circuit 47 receives the input difference signal X determined by the sign determining circuit 42. If is positive, the threshold value inputted from the coefficient unit 48a is selected, and if it is negative, the threshold value -0 given from the coefficient unit 48b is selected. The threshold value selected by the switching circuit 47 or -
D is given to the coefficient multiplier 43b in the first coefficient multiplier group 43,
The signal is multiplied by 8 and given to the switching circuit 49 as Z2-DS (D includes negative values), and also given to the coefficient multiplier 46f.

Coefficient units 46c, 48d, and 48e are switching circuits 45
Each signal representing the threshold value given by is doubled.

Multiply by 3, multiply by 4, comparators 48b, 48c, 48d
respectively to the other input terminal of . Furthermore, the coefficient unit 48
f is Z 2 "" D S output from the coefficient unit 43b
The signal representing 4DS is multiplied by 4 and is supplied to the subtracter 51 as a signal representing 4DS.

In the subtracter 51, 4DS-SXo is calculated and a signal z3 representing the calculation result is input to the switching circuit 49. Furthermore, a signal representing Z2-Ds outputted from the coefficient unit 43b is input to the subtracter 50, and Z-8Xo-DS is calculated in this subtracter 50, and a signal Z1 representing the result of this calculation is is input to the switching circuit 49.

On the other hand, in the comparators 48a to 48d in the comparator group 48.

Input difference signal X converted into absolute value. and these comparators 48a
The reference value (threshold value) given to ~48d.

2D, 3D, and 4D) are compared, and a signal representing the results of these comparisons is input to the switching circuit 49 as a switching control signal. In response to this switching control signal, switching circuit 49 outputs an input difference signal X. The level of.

If it is below the threshold, the grounded Z4 terminal becomes 0.
Outputs a level signal, and when D<Xo≦2D, Z
-3Xo-DS is output, and when 2D x ≦3D, a signal Z2-DS is output.

If 3D x ≦4D, Niha signal Z3-4DS-SX
is output, and when Xo exceeds 4D, switching is made to output a 0 level signal from the grounded Z4 terminal. Also turn on the contour compensation circuit.

An OFF signal is given to the switching circuit 49, and when an ON signal is given, the comparator circuit 49 switches to the comparator group 4.
The above-mentioned operation is performed according to the output of 8.

When an off signal is applied, the switch is switched to the grounded z4 terminal, and the output Z becomes 0.

Finally, another specific example of the configuration of the first nonlinear processing circuit 12 for noise reduction will be explained. FIG. 9 is a circuit diagram showing a second example of the first nonlinear processing circuit 12. In addition, Fig. 10 shows an inter-field difference signal (hereinafter simply referred to as a difference signal).
11 is a graph showing the relationship between the level of X and the nonlinear coefficient of the nonlinear processing circuit 12, and FIG. 11 is a graph showing the relationship between the input difference signal X and the output signal Y of the nonlinear processing circuit 3.

As is clear from FIG. 11, in the nonlinear processing circuit shown in FIG. 9, the level of input X and the level of output Y are in a proportional relationship until input X reaches a predetermined value Δ; Then, the output Y is kept at a constant value ΔK up to 2Δ. When the input X exceeds 2Δ, the output Y decreases linearly at a constant slope, and when the input X exceeds 3Δ, the output Y is kept at zero. In this way, this nonlinear processing circuit is configured to generate an output Y whose level changes in a trapezoidal manner as the level of the input X increases.

The input difference signal X includes a component representing image movement in addition to a noise component. It is considered that as the component representing motion increases, the level of the input difference signal X increases. 7th
In the nonlinear processing circuit shown in the figure, when the level of input to prevent noise reduction processing from being performed. Therefore, ideal noise reduction processing can be expected by using this nonlinear processing circuit.

Referring to FIG. 9, the difference signal X input to the first nonlinear processing circuit 12 is the absolute value circuit 31. It is applied to the sign discrimination circuit 32 and the coefficient multiplier 33a in the first coefficient multiplier group 33. The absolute value circuit 31 converts the input difference signal
It is given to one input terminal of a to 38c. The sign discrimination circuit 32 detects that the input difference signal X is positive.

It discriminates the negative sign, and the discrimination signal is given as a switching control signal to a switching circuit 37, which will be described later.

The first coefficient unit group 33 includes two coefficient units 33a.

33b is included. These coefficient units 33g, 33
Both signals b are for multiplying the human input signal by a coefficient K and outputting the result. One coefficient unit 33a multiplies the input difference signal X by a coefficient,
A signal representing Yl-KX is applied to the next stage switching circuit 39 and also to the subtracter 40.

In this embodiment as well, it is possible to switch the degree of noise reduction into two stages, and for this purpose a threshold generation circuit 34 is provided which generates two types of thresholds, Δ and Δ . These threshold values Δ1° and Δ2 are applied to two input terminals of the switching circuit 35, respectively. The switching circuit 35 is supplied with an external threshold selection signal specifying the degree of noise reduction, and the threshold value Δ1 or Δ2 is selected in accordance with this selection signal. The signal representing the selected threshold value Δ (the two types of threshold values ΔI and Δ2 are collectively expressed as Δ) is output from the switching circuit 35.

Four coefficient units 36a, 36b in the second coefficient unit group 36
.

38c, 36d and the other input terminal of comparator 38a. The coefficient multiplier 38a in the second coefficient multiplier group 36 multiplies the manually input threshold value Δ by 1, and the coefficient multiplier 38b multiplies the input threshold value Δ by −1 and outputs a signal representing them. be. The output signals of the coefficient multipliers 36a and 36b are applied to two input terminals of a switching circuit 37, respectively.

The switching circuit 37 performs switching based on the discrimination signal from the code discrimination circuit 32. That is, the switching circuit 37 selects the threshold value Δ input from the coefficient unit 36a if the input difference signal X determined by the sign determination circuit 32 is positive, and selects the threshold value −Δ input from the coefficient unit 3Bb if it is negative. do.

Threshold value Δ or −Δ selected by switching circuit 37
is applied to the coefficient multiplier 33b in the first coefficient multiplier group 33, multiplied by , and applied to the switching circuit 39 as Y2''ΔK (Δ includes negative values), as well as to the coefficient multiplier 3[ie.

The coefficient multipliers 3[ic and 36d multiply the signals representing the threshold value Δ given from the switching circuit 35 by 2 and 3, respectively.
It is applied to the other input terminals of comparators 38b and 38C, respectively. Further, the coefficient multiplier 3Be triples the signal representing Y2-ΔK output from the coefficient multiplier 33b and supplies it to the subtracter 40 as a signal representing 3ΔK.

In the subtracter 40, -KX is calculated on 3Δ.

A signal Y3 representing the result of this calculation is input to the switching circuit 39.

On the other hand, in the comparators 38a to 38c in the comparator group 88.

The absolute value input difference signal X and these comparators 38a~
The reference value (threshold Δ) given to 38c.

2Δ, 3Δ) are compared, and a signal representing the results of these comparisons is input to the switching circuit 39 as a switching control signal. In response to this switching control signal, the switching circuit 39 outputs a signal Y1-KX when the level of the input difference signal
-Output ΔK.

When 2Δ×X≦3Δ, -Yl is output as the signal Y3-3Δ, and when X exceeds 3Δ, switching is made to output a 0 level signal from the grounded Y4 terminal. Further, a signal for turning on and off the noise reduction circuit is given to the switching circuit 39. When the on signal is given, the comparator circuit 39 performs the above operation according to the output of the comparator group 38, but when the off signal is given, the grounded Y
It is switched to 4 terminals, and the output Y becomes 0.

FIG. 12 is a circuit diagram showing a third example of the first nonlinear processing circuit 12. Further, FIG. 13 is a graph showing the relationship between the level of the input difference signal X and the nonlinear coefficient of this nonlinear processing circuit, and FIG. 14 is a graph showing the relationship between the input difference signal X and the output signal Y of the nonlinear processing circuit. It is a graph.

As is clear from FIG. 14, in the nonlinear processing circuit shown in FIG. 12, the level of input X and the level of output Y are in a proportional relationship until input X reaches a predetermined value Δ; Then, the output Y decreases linearly with a constant slope, and when the input X is 2Δ or more, the output Y is kept at zero. in this way,
This non-linear processing circuit is configured to generate an output Y whose level changes triangularly in response to an increase in the level of human power X. According to this nonlinear processing circuit, close to ideal noise reduction processing can be expected, and the configuration is simpler than that of the circuit shown in FIG. 7.

In FIG. 12, the same parts as those shown in FIG. 9 are given the same reference numerals, and only the different points will be described.

The output Y2 of the coefficient multiplier 33b is not input to the switching circuit 39. In the comparator group 38, no comparator 38c is provided. A signal representing 2Δ output from the coefficient unit 36f is applied to the subtracter 40. Therefore, the subtracter 4a outputs a signal representing -KX at Y3-2Δ.

The switching circuit 89 operates as follows based on the switching control signal inputted from the comparator group 38. That is, the switching circuit 39
selects and outputs the signal Y1 until the input difference signal X reaches Δ,
When Δx≦2Δ, a signal Y3 is output, and when X exceeds 2Δ, a zero level signal Y4 is output. In this way, the characteristics shown in FIGS. 13 and 14 are obtained.

Effects of the Invention According to the present invention, an arithmetic mean signal of two adjacent lines in one field of interlaced scanning is created, and a video signal of a line in the other field located between these two lines is calculated. By taking the difference from the arithmetic mean above.

An inter-field difference signal is obtained. Since the noise component is removed from the input video signal using so-called 3-line field correlation, the 1-phase characteristics are improved, vertical phase shift is eliminated, and a video signal with a high S/N ratio can be obtained. can. Further, since it is sufficient to add a 1H delay circuit, a switching circuit, and an averaging circuit to the conventional circuit, the circuit does not become so complicated. Furthermore, integration is relatively easy.

Furthermore, a 1-field delay circuit for creating an inter-field difference signal for noise reduction and a 1-field delay circuit for creating an inter-field difference signal for vertical contour compensation are combined into a noise reduction circuit and a vertical contour compensation circuit. Since it is shared by both, the circuit configuration becomes simpler. In addition, since the first nonlinear processing circuit for noise reduction and the second nonlinear processing circuit for edge enhancement are provided separately, each interfield difference signal has a nonlinear processing circuit according to its purpose. This makes it possible to perform appropriate noise reduction and contour enhancement at all times according to the movement of one image.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a noise reduction and vertical contour compensation circuit according to an embodiment of the present invention. FIGS. 2 and 3 show the relationship between the input video signal and the delayed video signal. In FIG. 2, the horizontal scanning line in the first field is shown as a solid line. In FIG. 3, the horizontal scanning lines in the second field are shown by solid lines. Figure 4 shows the first nonlinear processing circuit for noise reduction.
5 is a graph showing the relationship between the level of the inter-field difference signal and the nonlinear processing coefficient, and FIG. 6 is a graph showing the relationship between the field difference signal and the output signal of the nonlinear processing circuit. This is a graph showing. FIG. 7 is a circuit diagram showing an example of the second nonlinear processing circuit or the third nonlinear processing circuit for vertical contour compensation, and FIG. 8 shows the relationship between the interfield difference signal and the output signal of the nonlinear processing circuit. It is a graph. Figure 9 shows the second nonlinear processing circuit for noise reduction.
Figure 1O is a graph showing the relationship between the level of the field difference signal and the nonlinear processing coefficient, and Figure 11 is a graph showing the relationship between the field difference signal and the output signal of the nonlinear processing circuit. be. FIG. 12 is a circuit diagram showing a third example of the first nonlinear processing circuit for noise reduction, FIG. 13 is a graph showing the relationship between the level of the interfield difference signal and the nonlinear processing coefficient, and FIG.
The figure is a graph showing the relationship between the interfield difference signal and the output signal of the nonlinear processing circuit. Figure 15 is a block diagram of a conventional noise reduction circuit using two-line field correlation, Figure 16 is the horizontal scanning line of the first field in interlaced scanning, and Figure 17 is the horizontal scanning line of the second field. Each is shown by a solid line. 1.7.21...1H delay circuit. 2, 8.17.22.27.28...addition circuit. 3, 9.23.29... l/2 coefficient unit. 4...first switching circuit. 5...Second subtraction circuit. 6...262H delay circuit. lO...Second switching circuit. 11...First subtraction circuit. 12...First nonlinear processing circuit. 14...Third subtraction circuit. 16...Second nonlinear processing circuit. 24... Fourth subtraction circuit. 2B...Third nonlinear processing circuit. Patent applicant: NEC Home Electronics Co., Ltd. Agent: Patent attorney: Hisashi Ushi
Ken Tsukasa j I 2 Sword I Filt Army 3 Figure Kashi 2 Field Figure 15 Figure 16 M1 field Figure 17 M2 field

Claims (7)

[Claims] (1) a 1H delay circuit that delays the input video signal by 1H; a first averaging circuit that receives the input video signal and the signal delayed by 1H by the 1H delay circuit and outputs an average signal of these input signals; The input video signal and the output signal of the first averaging circuit are switched, and the input video signal is selected when scanning one field, and the output signal of the first averaging circuit is selected when scanning the other field. a first switching circuit that selects and outputs; a 262H delay circuit that delays the input video signal by 262H; a 263H delay circuit that delays the input video signal by 263H; an output signal of the 262H delay circuit and an output signal of the 263H delay circuit; and a second averaging circuit that outputs an average signal of these output signals, and switches between the output signal of the 263H delay circuit and the output signal of the second averaging circuit. a second switching circuit that selects the output signal of the second averaging circuit and selects and outputs the output signal of the 263H delay circuit during the other field scanning; a first subtraction circuit that calculates the difference between the output signal of the second switching circuit and outputs a first inter-field difference signal; a first nonlinear processing circuit that performs predetermined nonlinear processing for noise reduction; a second subtraction circuit that subtracts the output signal of the first nonlinear processing circuit from the input video signal and outputs the result as a noise-reduced video signal; The difference between the noise-reduced video signal output from the second subtraction circuit and the output signal of the second averaging circuit is calculated, and
a third subtraction circuit that outputs an inter-field difference signal; a second nonlinear circuit that performs predetermined nonlinear processing for vertical contour compensation on the second inter-field difference signal output from the third subtraction circuit; The output signal of the second nonlinear processing circuit is added to the noise-reduced video signal output from the processing circuit and the second subtraction circuit, and the resultant signal is output as a video signal subjected to noise reduction and vertical contour compensation. Noise reduction and vertical contour compensation circuit with adder circuit, . (2) The first nonlinear processing circuit for noise reduction creates a first signal having a level proportional to the level of the first inter-field difference signal; a second circuit that creates a second signal at a constant level regardless of the level of the inter-field difference signal; and a signal that compares the level of the first inter-field difference signal with a predetermined reference level and represents the comparison result. a comparison circuit that outputs a signal, and a comparison circuit that outputs the first signal when the level of the first inter-field difference signal is below the reference level, and outputs the second signal when the level of the first inter-field difference signal is equal to or higher than the reference level, according to the output signal of the comparison circuit. The noise reduction and vertical contour compensation circuit according to claim 1, comprising: a switching circuit that selects and outputs the respective signals; (3) the first nonlinear processing circuit for noise reduction, a first circuit that creates a first signal having a level proportional to the level of the first inter-field difference signal; a second circuit that creates a second signal at a constant level regardless of the level of the inter-field difference signal; and a third circuit that creates a third signal whose level decreases as the level of the first inter-field difference signal increases. a third circuit that controls the level of the first inter-field difference signal;
, a comparison circuit that compares the first inter-field difference signal with a second and third reference level and outputs a signal representing a comparison result; When the signal is below the reference level, the first signal is used, when the signal is between the first reference level and the second reference level, the second signal is used, and when the signal is between the second reference level and the third reference level. The noise reduction according to claim (1), comprising: a switching circuit that selects and outputs the third signal when the level is between the third reference level and a zero level signal when the level is equal to or higher than the third reference level; Double vertical contour compensation circuit. (4) the first nonlinear processing circuit for noise reduction, a first circuit that creates a first signal having a level proportional to the level of the first inter-field difference signal; a second circuit for creating a second signal whose level decreases as the inter-field difference signal increases; and comparing the level of the first inter-field difference signal with different first and second reference levels. , a comparator circuit that outputs a signal representing a comparison result; and a comparator circuit that outputs a signal representing a comparison result; a switching circuit that selects and outputs the second signal when the signal is between the first reference level and the second reference level, and a zero level signal when the signal is equal to or higher than the second reference level; The noise reduction and vertical contour compensation circuit according to claim (1). (5) the second nonlinear processing circuit for vertical contour compensation; a first circuit that creates a first signal having a level proportional to the level of the second inter-field difference signal; a second circuit that generates a second signal at a constant level regardless of the level of the second inter-field difference signal; and a third signal whose level decreases as the level of the second inter-field difference signal increases. A third circuit to be created and a first circuit with different levels of the second inter-field difference signal.
, a comparison circuit that compares the signals with second, third, and fourth reference levels and outputs a signal representing a comparison result; When the signal is below the first reference level, the signal is at zero level; when it is between the first reference level and the second reference level, the first signal is set; when the signal is at the second reference level and the third reference level. When the level is between the third reference level and the fourth reference level, the third signal is set, and the fourth signal is set between the third reference level and the fourth reference level.
2. The noise reduction and vertical contour compensation circuit according to claim 1, comprising: a switching circuit that selects and outputs a signal having a zero level when the signal is equal to or higher than a reference level; (6) The noise reduction and vertical contour compensation circuit according to claim 1, wherein the 263H delay circuit is comprised of the 262H delay circuit and the 1H delay circuit. (7) An interpolation signal creation circuit that creates and outputs a line interpolation signal that is an average signal of the noise-reduced video signal output from the second subtraction circuit and the noise-reduced video signal 1H before the noise-reduced video signal; a fourth subtraction circuit that calculates the difference between the output signal of the 263H delay circuit and the line interpolation signal and outputs a third interfield difference signal; a third interfield difference output from the fourth subtraction circuit; A third non-linear processing circuit performs predetermined non-linear processing on the signal for vertical contour compensation, and vertical contour compensation is performed by adding the output signal of the third non-linear processing circuit to the line interpolation signal. The noise reduction and vertical contour compensation circuit according to claim 1, further comprising: a second addition circuit that outputs the interpolated signal.