JPH02288550A - Noise reduction and vertical contour compensation circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit constitution by sharing a circuit including a subtraction circuit to generate an inter-field difference signal with a noise reduction circuit and a vertical contour compensation circuit. CONSTITUTION:An inter-field difference signal outputted from a 1st subtraction circuit 1 is given to a 1st nonlinear processing circuit 3 and nonlinear processing for noise reduction in response to the level of the inter-field difference signal is applied. Then a video signal subjected to noise reduction processing is obtained at a 2nd subtraction circuit 2 by subtracting the resulting signal from an input video signal. On the other hand, the inter-field difference signal is subjected to nonlinear processing for the vertical contour compensation in response to the level of the inter-field difference signal at a 2nd nonlinear processing circuit 8 and its output signal is added to an adder circuit 9 to the video signal subjected to noise reduction processing to attain the emphasis of vertical contour. Thus, the circuit constitution is simplified.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention provides a circuit that combines a noise reduction circuit (so-called noise reducer) for reducing noise components of a video signal and a circuit for vertical contour compensation (emphasis). Regarding.

The basic idea of conventional technology noise reduction circuits is to take advantage of the fact that video signals have a strong correlation in the vertical direction with respect to adjacent horizontal scanning lines, extract noise components by taking line-to-line difference signals, and eliminate this noise. The purpose is to subtract a difference signal containing the components from the original video signal. Since the noise reduction process is a type of averaging process, the shading of one image is averaged in the vertical direction, and clear boundaries may become blurred. The vertical contour compensation circuit emphasizes the vertical contour, and this circuit has the function of correcting the vertical blur caused by the noise reduction circuit.

Problems to be Solved by the Invention As described above, the noise reduction circuit and the vertical contour compensation circuit have a mutually complementary relationship, but if these circuits were provided separately, the circuit configuration would become complicated. Also.

In both noise reduction processing and vertical contour compensation processing, it is necessary to fully consider image motion.

The present invention provides a noise reduction/vertical contour compensation circuit which has a circuit configuration as simple as possible and is capable of processing in consideration of image motion.

Means for Solving the Problems The noise reduction and vertical contour compensation circuit according to the present invention includes a first subtraction circuit that subtracts a video signal delayed by 262H or 263H from an input video signal and outputs an inter-field difference signal. , a first nonlinear processing circuit that performs predetermined nonlinear processing for noise reduction on the interfield difference signal output from the first subtraction circuit; and an output signal of the first nonlinear processing circuit from the input video signal. a second subtraction circuit that subtracts the signal and outputs it as a noise-reduced video signal; a second nonlinear circuit that performs predetermined nonlinear processing for vertical contour compensation on the inter-field difference signal output from the first subtraction circuit; The output signal of the second nonlinear processing circuit is added to the noise-reduced video signal output from the processing circuit and the second subtraction circuit, and the resultant signal is output as a video signal subjected to noise reduction and vertical contour compensation. It is characterized by being equipped with an adder circuit.

Function: The inter-field difference signal output from the first subtraction circuit is given to the first non-linear processing circuit, where it is subjected to non-linear processing for noise reduction according to the level of the inter-field difference signal. By subtracting the input video signal from the input video signal in the subtraction circuit No. 2, the video signal becomes a video signal to which a noise reduction circuit has been applied.

On the other hand, the inter-field difference signal outputted from the first subtraction circuit is applied to the second non-linear processing circuit, and is subjected to non-linear processing for vertical contour compensation according to the level of the inter-field difference signal. Vertical edge enhancement is achieved by adding the output signal of this second nonlinear processing circuit to the above-mentioned noise-reduced video signal.

Embodiment FIG. 1 shows an embodiment of a noise reduction and vertical contour compensation circuit. This is a circuit that uses two-line field correlation.

A human video signal (luminance signal Y after Y/C separation) is given to a first subtraction circuit 1 and a second subtraction circuit 2.

The output signal of the second subtraction circuit 2 is a video signal after noise reduction processing, and this video signal is further applied to an addition circuit 9, subjected to vertical contour compensation processing, and then outputted to an output terminal.

Further, the output signal of the second subtraction circuit 2 is applied to a 262H delay circuit (field memory) 4 to delay it by one field period (H is one horizontal scanning period). The signal delayed by 262H by the 262H delay circuit 4 is applied to the B terminal of the switching circuit 6 and the IH delay circuit (line memory) 5. The signal applied to the IH delay circuit 5 is further delayed by IH, output, and applied to the A terminal of the switching circuit 6.

The switching circuit 6 switches the A terminal and B terminal for each field of the scanning screen based on the switching control signal, and the signal selected according to the switching (video signal delayed by 263H or 262H) is fed back. It is applied to the first subtraction circuit 1.

In the subtraction circuit 1, the output video signal of the switching circuit 6 is subtracted from the input video signal, and an inter-field difference signal X is output. This interfield difference signal X is given to the first nonlinear processing circuit 3. The first nonlinear processing circuit 3 detects the degree of movement in the vertical direction of the image according to the magnitude of the input inter-field difference signal (Noise) component Y
Output. The specific configuration of the first nonlinear processing circuit 3 will be detailed later, and this circuit 3 is shown in FIG.

It has characteristics as shown in FIG. 9 or FIG. 12.

Noise component signal gY output from the first nonlinear processing circuit 3
is applied to the second subtraction circuit 2, and the noise component is subtracted from the input video signal, so that a video signal with reduced noise components is obtained.

On the other hand, the inter-field difference signal X output from the first subtraction circuit 1 is input to the second nonlinear processing circuit 8 via a low-pass filter 7. The interfield difference signal X includes a high frequency component in the vertical direction of the image (specifically, a 15.7 KHz signal and its high frequency). Low pass filter is 0.5
It allows signals of about MHz or I MHz or less to pass through, thereby removing high frequency components in the horizontal direction (which is generally high frequency noise) from the interfield difference signal. In this way, only the vertical signal component is
input to the nonlinear processing circuit 8 of. An example of a specific configuration of the nonlinear processing circuit 8 will be described later, but it has characteristics as shown in FIG. , outputs a signal component Z representing the vertical contour to be emphasized depending on the degree of the detected movement.

The output signal Z of the second nonlinear processing circuit 8 is then sent to the adder circuit 9
given to. The above-mentioned noise-reduced output video signal of the second subtraction circuit 2 is also given to this adder circuit 9, and by adding the signal Z to this video signal, the vertical contour-compensated video signal is sent to the adder circuit. It will be output from 9. This means that the rounding of the waveform caused in the vertical direction by the noise reduction processing is compensated for by the vertical contour enhancement.

A first specific example of the configuration of the first nonlinear processing circuit 3 will be described. FIG. 2 is a circuit diagram showing an example of the first nonlinear processing circuit 3. In FIG. 3 is a graph showing the relationship between the level of the inter-field difference signal (hereinafter simply referred to as difference signal) X and the nonlinear coefficient of the nonlinear processing circuit 3, and FIG. 4 is a graph showing the relationship between the input difference signal X and the nonlinear processing circuit. 3 is a graph showing the relationship with the output signal Y of No. 3.

As is clear from FIG. 4, the nonlinear processing circuit shown in FIG.
are in a proportional relationship, but when the input X exceeds a predetermined value Δ, the output Y is kept at a constant value ΔK. The input difference signal X includes a component representing image movement in addition to a noise component. It is considered that as the component representing motion increases, the level of the input difference signal X increases. On the other hand, the level of the noise component can be considered to be approximately constant. Therefore, in this nonlinear processing circuit, when the level of the input X exceeds a predetermined value Δ, the level of the output Y representing the noise component is kept constant. This nonlinear processing circuit is characterized by a simple configuration.

Difference signal X input to nonlinear processing circuit 3 with reference to FIG.
is the absolute value circuit 31. It is applied to the sign discrimination circuit 32 and the coefficient multiplier 33a in the first coefficient multiplier group 33.

The absolute value port □ circuit 31 converts the input difference signal , a negative sign, and the determination signal is given as a switching control signal to a switching circuit 37, which will be described later.

The first coefficient unit group 33 includes two coefficient units 33a.

33b is included. These coefficient units 33a, 33
In both cases, the input signal is multiplied by a coefficient K and outputted. One coefficient unit 33a multiplies the input difference signal X by a coefficient,
Signals representing Y and -KX are applied to the next stage switching circuit 39.

In this embodiment, it is possible to switch the degree of noise reduction into two stages, and for this purpose, a threshold generation circuit 84 is provided that generates two types of thresholds, Δ 1 and Δ 2 . These threshold values Δ1゜Δ2 are determined by the switching circuit 35-2.
each input terminal. The switching circuit 35 is supplied with an external threshold selection signal that specifies the degree of noise reduction, and the threshold value Δ1 is set according to this selection signal.
Or Δ2 is selected. The signal representing the selected threshold value Δ (the two types of threshold values Δl and Δ2 are collectively expressed as Δ) is output from the switching circuit 35.

It is applied to the other input terminal of two coefficient multipliers Ha and 36b in the second coefficient multiplier group 36 and a comparator 38.

One coefficient multiplier 36a in the second coefficient multiplier group 36 multiplies the input threshold value Δ by 1, and the other coefficient multiplier 38b multiplies the input threshold value Δ by −1, and outputs a signal representing them. This is what is output. The output signals of the coefficient multipliers 36a and 38b are applied to two input terminals of a switching circuit 37, respectively.

The switching circuit 37 performs switching based on the discrimination signal from the code discrimination circuit 32. That is, the switching circuit 37 selects the threshold value Δ input from the coefficient unit 36a if the input difference signal X determined by the sign determination circuit 32 is positive, and selects the threshold value −Δ input from the coefficient unit 38b if it is negative. do.

Threshold value Δ or −Δ selected by switching circuit 37
is applied to the coefficient multiplier 33b in the first coefficient multiplier group 33, multiplied by , and applied to the switching circuit 39 as Y2-ΔK (Δ includes negative values).

On the other hand, the comparator 38 compares the input difference signal X converted into an absolute value with a threshold value Δ1 or Δ2 given to the comparator 38. The comparator 38 switches between the switching circuits 3 and 3 depending on the magnitude of these.
A switching control signal is given to 9. That is, if the input difference signal
KX, and if the input difference signal X is greater than the selected threshold, the switching circuit 39 outputs a signal Y2-ΔK. In addition, the signal that turns the noise reduction circuit on and off is the switching circuit 3.
9, and when an ON signal is applied, the comparator circuit 39 performs the above operation according to the output of the comparator 38, but when an OFF signal is applied, it is switched to the grounded Y3 terminal. , the output Y becomes 0.

Next, a specific configuration example of the second nonlinear processing circuit 8 will be explained. FIG. 5 is a circuit diagram showing an example of the second nonlinear processing circuit 8. In FIG. FIG. 6 is a graph showing the relationship between the input difference signal X and the output signal Z of the nonlinear processing circuit 8.

As is clear from FIG. 6, in the nonlinear processing circuit shown in FIG. 5, the output Z is kept at zero regardless of the value of the input X until the input X reaches a predetermined value. Input X or specified 1ii! 2 from D
Up to D, the level of input X and the level of output Z are in a proportional relationship. Further, when the input X becomes 2D or more, the output 2 is kept at a constant value DS up to 3D. When the input X exceeds 3D, the output Z decreases linearly with a constant slope, and when the input X exceeds 4
Above D, the output Z is kept at zero. In this way, this nonlinear processing circuit is configured to generate an output Z whose level changes in a trapezoidal manner as the level of the input X increases.

In addition to the component representing the vertical contour, the input difference signal X includes a noise component and a component representing image motion. It is considered that there are many noise components in the portion where the level of the input difference signal X is low. It is also considered that the level of the input difference signal X increases as the component representing motion increases. In the nonlinear processing circuit shown in Fig. 5, the output signal Z is kept at zero when the level of input By keeping the output signal 2 at zero, 9 contour enhancement is not performed. This is an ideal nonlinear processing circuit for contour compensation that emphasizes contours according to the level of the input signal when the level of the input X is in the range of D to 4D.

Referring to FIG. 5, the difference signal X input to the second nonlinear processing circuit 8 is the absolute value circuit 41. The code discrimination circuit 42 and the first
is applied to the coefficient multiplier 43a in the coefficient multiplier group 43. The absolute value circuit 41 converts the input difference signal
~48d is applied to one input terminal. The sign discrimination circuit 42 detects that the input difference signal X is positive.

It discriminates the negative sign, and the discrimination signal is given as a switching control signal to a switching circuit 47, which will be described later.

The first coefficient unit group 43 includes two coefficient units 43a.

43b is included. These coefficient units 43a, 43
In both cases, the input signal is multiplied by a coefficient S and output. One coefficient unit 43m multiplies the input difference signal X by a coefficient of 8,
Signals representing Z and -SX are applied to the next stage switching circuit 49 and also to the subtractor 650.51.

In this embodiment, it is possible to switch the degree of edge enhancement into two levels, and for this purpose, a threshold generation circuit 44 is provided which generates two types of threshold values D2. These threshold values Dl.

D2 is applied to two input terminals of the switching circuit 45, respectively. The switching circuit 45 is supplied with an external threshold selection signal specifying the degree of edge enhancement, and the threshold D1 or D2 is selected in accordance with this selection signal. The signal representing the selected threshold value D (the two types of threshold values D1 and D2 are collectively expressed as D) output from the switching circuit 45 is as follows.

Five coefficient units 46 a r 4 in the second coefficient unit group 4B
6bT4Bc, 46d, 46e and the other input terminal of the comparator 48a. The coefficient multiplier 46a in the second coefficient multiplier group 46 multiplies the input threshold value by 1, and the coefficient multiplier 461b□ multiplies the input threshold value by -1, and outputs a signal representing these t''. The output signals of the coefficient multipliers 46a and 46b are applied to two input terminals of a switching circuit 47, respectively.

The switching circuit 47 performs switching based on the discrimination signal from the code discrimination circuit 42. That is, the switching circuit 47 selects the threshold value inputted from the coefficient multiplier 46a if the input difference signal X determined by the sign discrimination circuit 42 is positive, and selects the threshold value -D given from the coefficient multiplier 48b if it is negative. do.

The threshold value selected by the switching circuit 47 or -D
is given to the coefficient multiplier 43b in the first coefficient multiplier group 43, and 8
It is multiplied and given to the switching circuit 49 as 22-DS (D includes negative values) and also given to the coefficient multiplier 48f.

Coefficient units 46c, 48d, and 46e are switching circuits 45
Each signal representing the threshold value given by is doubled.

Multiply by 3, multiply by 4, comparators 48b, 48c, 48
d to the other input terminal. Furthermore, coefficient unit 4
8f multiplies the signal representing Z2-DS outputted from the coefficient multiplier 43b by four and supplies it to the subtracter 51 as a signal representing 4DS.

In the subtracter 51, 4DS-8X is calculated.

A signal z3 representing the result of this calculation is input to the switching circuit 49. Furthermore, a signal representing Z2-DS outputted from the coefficient unit 43b is input to the subtracter 50, Z, -5X-DS is calculated in this subtracter 50, and the signal z1 representing the result of this calculation is switched. input to circuit 49;

On the other hand, in the comparators 48a to 48d in the comparator group 48.

Absolute input difference signal X and these comparators 48'a
The reference value (threshold value) given to ~48d.

2D, 3D, and 4D) are compared, and a signal representing the results of these comparisons is input to the switching circuit 49 as a switching control signal. The switching circuit 49 changes the level of the input difference signal X in response to this switching control signal.

If it is below the threshold, the 0 of the grounded z4 terminal
output a level signal, and when D<X≦2D, EiZ,
-5X-DS, and when 2D<X≦3D, it outputs the signal Z2-DS, and when 3Dx≦4D, it outputs the signal Z2-DS.
3-4DS-SX is output, and when X exceeds 4D, switching is made to output a 0 level signal from the grounded Z4 terminal. Further, a signal for turning on and off the contour compensation circuit is given to the switching circuit 49, and when the on signal is given, the comparator circuit 49 performs the above operation according to the output of the comparator group 48, but when the off signal is applied, it switches to the grounded Z4 terminal and output 2 becomes 0.
becomes.

Finally, another specific example of the configuration of the first nonlinear processing circuit 3 will be explained. FIG. 7 shows the second nonlinear processing circuit 3 of the first nonlinear processing circuit 3.
FIG. 2 is a circuit diagram showing an example. 8 is a graph showing the relationship between the level of the inter-field difference signal (hereinafter simply referred to as difference signal) X and the nonlinear coefficient of the nonlinear processing circuit 3, and FIG. 9 is a graph showing the relationship between the input difference signal X and the nonlinear coefficient of the nonlinear processing circuit 3 3 is a graph showing the relationship between the output signal Y and the output signal Y.

As is clear from FIG. 9, the nonlinear processing circuit shown in FIG.
The levels of are proportional to each other, but when the input X exceeds a predetermined value Δ, the output Y is kept at a constant value ΔK up to 2Δ. input
When X exceeds 2Δ, the output Y decreases linearly at a constant slope, and when the input X exceeds 3Δ, the output Y is kept at zero. In this way, this nonlinear processing circuit is configured to generate an output Y whose level changes in a trapezoidal manner as the level of the input X increases.

The input difference signal X includes a component representing image movement in addition to a noise component. It is considered that as the component representing motion increases, the level of the input difference signal X increases. 7th
In the nonlinear processing circuit shown in the figure, when the level of input to prevent noise reduction processing from being performed. Therefore, ideal noise reduction processing can be expected by using this nonlinear processing circuit.

Difference signal X input to nonlinear processing circuit 3 with reference to FIG.
is the absolute value circuit 31. It is applied to the sign discrimination circuit 32 and the coefficient multiplier 33a in the first coefficient multiplier group 33.

The absolute value circuit 31 converts the input difference signal X into an absolute value,
The output signal is applied to one input terminal of three comparators 38a to 38c in a comparator group 38, which will be described later. The sign discrimination circuit 32 discriminates whether the input difference signal X is positive or negative, and the discrimination signal is given as a switching control signal to a switching circuit 37, which will be described later.

The first coefficient unit group 33 includes two coefficient units 33a.

33b is included. These coefficient units 33a, 33
In both cases, the input signal is multiplied by a coefficient K and outputted. One coefficient unit 33a multiplies the input difference signal X by a coefficient,
Signals representing Y and -KX are applied to the next stage switching circuit 39 and also to the subtracter 40.

In this embodiment as well, it is possible to switch the degree of noise reduction into two stages, and for this purpose a threshold generation circuit 34 is provided which generates two types of thresholds, Δ and Δ . These threshold values Δl.

Δ2 is applied to two input terminals of the switching circuit 35, respectively. The switching circuit 35 is supplied with an external threshold selection signal specifying the degree of noise reduction, and the threshold value Δ1 or Δ2 is selected in accordance with this selection signal. The signal representing the selected threshold value Δ (the two types of threshold values Δ1 and Δ2 are collectively expressed as Δ) is output from the switching circuit 35.

Four coefficient units 3Qa, 36b in the second coefficient unit group 36
.

36c, 36d and the other input terminal of comparator 38a. Second coefficient “coefficient multiplier 38a in lid group 36”
The coefficient multiplier 38b multiplies the input threshold value Δ by 1, and the coefficient multiplier 38b multiplies the input threshold value Δ by −1 and outputs a signal representing them. The output signals of the coefficient multipliers 38a and 36b are applied to two input terminals of a switching circuit 37, respectively.

The switching circuit 37 performs switching based on the discrimination signal from the code discrimination circuit 32. That is, the switching circuit 37 selects the threshold value Δ inputted from the coefficient unit 36a if the input difference signal X determined by the sign determination circuit 32 is positive, and selects the threshold value −Δ inputted from the coefficient unit 36b if it is negative. do.

Threshold value Δ or −Δ selected by switching circuit 37
is applied to the coefficient multiplier 33b in the first coefficient multiplier group 33, multiplied by , and applied to the switching circuit 39 as Y2-ΔK (Δ includes negative values), as well as to the coefficient multiplier 36e.

Coefficient multipliers 36c and 36d double and triple the signals representing the threshold value Δ given from switching circuit 35, respectively, and apply the results to the other input terminals of comparators 38b and 38c, respectively. Furthermore, the coefficient multiplier 36e triples the signal representing Y2-ΔK outputted from the coefficient multiplier 33b and supplies it to the subtracter 40 as a signal representing 3ΔK.

In the subtracter 40, -KX is calculated on 3Δ.

A signal Y3 representing the result of this calculation is input to the switching circuit 39.

On the other hand, in the comparators 38a to 38c in the comparator group 38.

The absolute value input difference signal X and these comparators 38a~
The reference value (threshold Δ) given to 38c.

2Δ, 3Δ) are compared, and a signal representing the results of these comparisons is input to the switching circuit 39 as a switching control signal. In response to this switching control signal, the switching circuit 39 changes the level of the input difference signal X.

If the threshold value Δ is below, the signal Y1-KX is output, and Δ
If X≦2∆, it outputs the signal Y2-∆K, and if 2∆≦X≦3∆, it outputs -Y as the signal Y3-3∆.
When X exceeds 3Δ, switching is made to output a 0 level signal from the grounded Y4 terminal. Further, a signal for turning on and off the noise reduction circuit is given to the switching circuit 39, and when the on signal is given, the comparison circuit 39
9 performs the above operation in response to the output of the comparator group 38, but when an off signal is applied, it is switched to the grounded Y4 terminal, and the output Y becomes 0.

FIG. 1O is a circuit diagram showing a third example of the nonlinear processing circuit 3. Moreover, FIG. 11 is a graph showing the relationship between the level of the inter-field difference signal (hereinafter simply referred to as difference signal) X and the nonlinear coefficient of this nonlinear processing circuit, and FIG. 12 is a graph showing the relationship between the input difference signal 7 is a graph showing a relationship with an output signal Y. FIG.

As is clear from FIG. 12, in the nonlinear processing circuit shown in FIG. 1O, the level of input X and the level of output Y are in a proportional relationship until input X reaches a predetermined value Δ, but Then, the output Y decreases linearly with a constant slope, and when the input X is 2Δ or more, the output Y is kept at zero. in this way,
This nonlinear processing circuit is configured to generate an output Y whose level changes triangularly as the level of the input X increases. According to this nonlinear processing circuit, close to ideal noise reduction processing can be expected, and the configuration is simpler than that of the circuit shown in FIG. 7.

In FIG. 10, the same components as those shown in FIG. 7 are given the same reference numerals, and only the different points will be described.

The output Y2 of the coefficient multiplier 33b is not input to the switching circuit 39. Comparator 38c is not provided in comparator group 3B. A signal representing 2Δ output from the coefficient unit 36f is applied to the subtracter 40. Therefore, the subtracter 40 outputs a signal representing -KX at Y3-2Δ.

The switching circuit 39 operates as follows based on the switching control signal input from the comparator group 38. That is, the switching circuit 39
selects and outputs the signal Y1 until the input difference signal X reaches Δ,
When Δx≦2Δ, a signal Y3 is output, and when X exceeds 2Δ, a zero level signal Y4 is output. In this way, the characteristics shown in FIGS. 11 and 12 are obtained.

Effects of the Invention According to the present invention, as described above, the circuit including the first subtraction circuit for creating the inter-field difference signal is shared by the noise reduction circuit and the vertical contour compensation circuit. The road configuration becomes simpler. In addition, the first
Since the non-linear processing circuit and the second non-linear processing circuit for contour enhancement are provided separately, it is possible to apply non-linear processing to the inter-field difference signal according to the purpose of each, and to reduce the movement of one image. This makes it possible to always perform appropriate noise reduction and edge enhancement depending on the situation.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a noise reduction and vertical contour compensation circuit according to an embodiment of the present invention. Figure 2 shows the first nonlinear processing circuit for noise reduction.
3 is a graph showing the relationship between the level of the inter-field difference signal and the nonlinear processing coefficient, and FIG. 4 is a graph showing the relationship between the inter-field difference signal and the output signal of the nonlinear processing circuit. be. FIG. 5 is a circuit diagram showing an example of the second nonlinear processing circuit for vertical contour compensation, and FIG. 6 is a graph showing the relationship between the interfield difference signal and the output signal of the nonlinear processing circuit. Figure 7 shows the second nonlinear processing circuit for noise reduction.
8 is a graph showing the relationship between the level of the inter-field difference signal and the nonlinear processing coefficient, and FIG. 9 is a graph showing the relationship between the inter-field difference signal and the output signal of the nonlinear processing circuit. be. FIG. 10 is a circuit diagram showing a third example of the first nonlinear processing circuit, FIG. 11 is a graph showing the relationship between the field difference signal level and the nonlinear processing coefficient, and FIG. 12 is a graph showing the relationship between the field difference signal level and the nonlinear processing coefficient. It is a graph showing the relationship between a nonlinear processing time path and an output signal. 1...First subtraction circuit. 2...Second subtraction circuit. 3...first nonlinear processing circuit. 8... Second nonlinear processing circuit. 9...Addition circuit. Patent applicant: NEC Home Electronics Co., Ltd.

Claims (5)

[Claims] (1) 262H or 26H from the input video signal
a first subtraction circuit that subtracts the 3H-delayed video signal and outputs an inter-field difference signal; a predetermined nonlinear process for noise reduction is performed on the inter-field difference signal output from the first subtraction circuit; First thing to do
a nonlinear processing circuit; a second subtraction circuit that subtracts the output signal of the first nonlinear processing circuit from the input video signal and outputs the result as a noise-reduced video signal; an interfield difference signal output from the first subtraction circuit; a second nonlinear processing circuit that performs predetermined nonlinear processing for vertical contour compensation on the noise reduction circuit, and a noise-reduced video signal output from the second subtraction circuit; A noise reduction/vertical contour compensation circuit comprising: an addition circuit which outputs a video signal subjected to noise reduction and vertical contour compensation. (2) The first nonlinear processing circuit for noise reduction includes a first circuit that creates a first signal having a level proportional to the level of the interfield difference signal, and a level of the interfield difference signal. a second circuit that generates a second signal at a constant level regardless of the difference between the fields; a comparison circuit that compares the level of the inter-field difference signal with a predetermined reference level and outputs a signal representing the comparison result; In accordance with the output signal of the circuit, when the level of the inter-field difference signal is below the reference level, the first
The noise reduction/vertical contour compensation circuit according to claim 1, comprising: a switching circuit that selects and outputs the second signal when the signal is equal to or higher than the reference level; (3) The first nonlinear processing circuit for noise reduction includes a first circuit that creates a first signal having a level proportional to the level of the interfield difference signal, and a level of the interfield difference signal. a second circuit for creating a second signal at a constant level regardless of the second signal; a third circuit that creates a third signal whose level decreases as the level of the inter-field difference signal increases;
and a comparison circuit that compares the signal with a third reference level and outputs a signal representing the comparison result; When the first signal is between the first reference level and the second reference level, the second signal is
When the signal is between the second reference level and the third reference level, the third signal is selected, and when the signal is above the third reference level, the zero level signal is selected and output. Claim (1) consisting of a switching circuit.
Noise reduction and vertical contour compensation circuit described in . (4) The first nonlinear processing circuit for noise reduction includes a first circuit that creates a first signal having a level proportional to the level of the interfield difference signal, and an increase in the interfield difference signal. a second circuit that generates a second signal whose level decreases as the field changes; and a second circuit that compares the level of the inter-field difference signal with different first and second reference levels and outputs a signal representing the comparison result. a comparator circuit; and a comparator circuit that, in accordance with the output signal of the comparator circuit, converts the first signal between the first reference level and the second reference level when the level of the inter-field difference signal is below the first reference level. The noise reduction according to claim (1), comprising: a switching circuit that selects and outputs the second signal when the level is between the two, and a signal with a zero level when the level is equal to or higher than the second reference level; Double vertical contour compensation circuit. (5) The second nonlinear processing circuit for vertical contour compensation includes a first circuit for creating a first signal having a level proportional to the level of the inter-field difference signal, and a first circuit for creating a first signal having a level proportional to the level of the inter-field difference signal; a second circuit that creates a second signal of a constant level regardless of the level; a third circuit that creates a third signal whose level decreases as the level of the inter-field difference signal increases; The level of the inter-field difference signal is set to different first and second levels.
, a comparison circuit that compares the signal with a third and fourth reference level and outputs a signal representing a comparison result; and a level of the inter-field difference signal is lower than or equal to a first reference level according to the output signal of the comparison circuit. When the signal is at zero level, when the signal is between the first reference level and the second reference level, the first signal is used, and when the signal is between the second reference level and the third reference level, the signal is at zero level. 2nd above
When the signal is between the third reference level and the fourth reference level, the third signal is selected, and when the signal is above the fourth reference level, the zero level signal is selected and output. The noise reduction and vertical contour compensation circuit according to claim 1, comprising: a switching circuit;