JP2627508B2 - Interrupt processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] The present invention relates to an interrupt processing device used by connecting to a system bus, and functions as a generator for generating an interrupt request on the system bus and monitors an interrupt request on the system bus. The present invention provides an interrupt processing apparatus having a function as a handler for requesting an interrupt processing from a central processing unit when there is an interrupt request. The interrupt processing apparatus of the present invention provides a bus interrupt request signal according to a local interrupt request signal. A bus interrupt output unit for inputting a bus interrupt request signal, and an interrupt output for outputting an interrupt request signal to the central processing unit when a local interrupt request signal or a bus interrupt request signal is input And a changeover switch circuit.

The present invention relates to an interrupt processing device.

2. Description of the Related Art Conventionally, an interrupt processing device that generates an interrupt request on a system bus, and monitors an interrupt request on the system bus, and when there is an interrupt request, interrupt processing is performed by a central processing unit (hereinafter, referred to as a CPU). A requesting interrupt processing device is known, and the former is called a generator and the latter is called a handler.

FIG. 3 is a block diagram of a basic configuration of a generator according to a conventional example.

In the figure, 1 is a local interrupt input unit for inputting a local interrupt request signal (LIR) output from an I / O device (not shown), 2 is a level conversion unit for encoding this signal, and 3 is a bus for transmitting the encoded signal. This is a bus interrupt output unit that outputs as an interrupt request signal (BIR). Reference numeral 4 denotes an interrupt acknowledgment unit for temporarily storing the output of the local interrupt input unit 1. When an acknowledgment signal (ACK) (not shown) is input, the content of this signal is compared with the stored data, and The vector generation unit 5 sends predetermined vector information to the CPU.

FIG. 4 is a basic block diagram of a handler according to a conventional example, 6 is a local interrupt input unit for inputting an LIR signal, 7 is a level conversion unit for encoding the LIR signal,
Reference numeral 8 denotes a bus interrupt input unit for inputting a bus interrupt request signal (BIR) output from the generator. Reference numeral 9 denotes an interrupt output unit, and when an LIR signal or a BIR signal is input,
Outputs an interrupt request signal IRL to the CPU. Reference numeral 10 denotes an interrupt acknowledgment unit for temporarily storing an LIR signal or a BIR signal when the signal is input. When an acknowledgment signal (ACK) (not shown) is input, the content of the signal is compared with the stored data to match. At this time, predetermined vector information is sent from the vector generator 11 to the CPU.

When an interrupt processing system is configured using such a conventional generator and handler, the configuration shown in FIG. 5 is obtained, for example. 12 is a CPU, 13 is a handler, 14 to 16 are generators, and 17 is a system bus. In addition,
Signals having the same reference numerals as those in FIGS. 3 and 4 indicate signals having the same contents.

[Problems to be Solved by the Invention] According to the conventional example, the handler and the generator have separate circuit configurations as shown in FIGS. 3 and 4, and are manufactured as separate chips. .

However, the handler and the generator also include the same circuit components, and if they can be created with the same chip, the development and manufacturing costs can be reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide an interrupt processing apparatus which has both a handler function and a generator function and can select one of the functions when used.

[Means for Solving the Problems] An interrupt processing apparatus according to the present invention includes a bus interrupt output unit that outputs a bus interrupt request signal according to a local interrupt request signal, a bus interrupt input unit that inputs a bus interrupt request signal, When an interrupt request signal or a bus interrupt request signal is input, at least an interrupt output unit for outputting an interrupt request signal to the central processing unit and a switch circuit are provided.

[Operation] When operated as a handler, the switch circuit is switched to activate the bus interrupt input section and the interrupt output section and deactivate the bus interrupt output section.

When operating as a generator, the switch circuit is switched to deactivate the bus interrupt input section and the interrupt output section, and activate the bus interrupt output section.

Example Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an interrupt processing apparatus according to an embodiment of the present invention, which has both a handler function and a generator function.

In the figure, reference numeral 18 denotes a local interrupt input unit for inputting a local interrupt request signal (LIR) output from an I / O device (not shown), 19 a level conversion unit for encoding this signal, and 20 a bus for encoding the encoded signal. Is a bus interrupt output unit that outputs the interrupt request signal (BIR).

Reference numeral 21 denotes a bus interrupt input unit for inputting a bus interrupt request signal (BIR), 22 denotes a level conversion unit 19 or a bus interrupt input unit 21.
Of the interrupt request signal (IR
L). 23 is LIR signal or BI
An interrupt acknowledgment section for temporarily storing the R signal when it is input.
When K) is input, the contents of this signal are compared with the stored data, and when they match, predetermined vector information is sent from the vector generation unit 24 to the CPU.

25 is a switch circuit which receives a / G control signal as an input,
When the / G control signal is "0", a signal is output to activate the bus interrupt input unit 21 and the interrupt output unit 22 and deactivate the bus interrupt output unit 20. When the / G control signal is "1", a G signal is output to make the bus interrupt output unit 20 active and the bus interrupt input unit 21 and the interrupt output unit 22 to be inactive.

Next, the operation of the interrupt processing apparatus of FIG. 1 will be described. When used as a handler, switch circuit 25
Set the / G pin to “0”. As a result, the bus interrupt input unit 21 and the interrupt output unit 22 become active, and the bus interrupt output unit 20 becomes inactive. That is, the interrupt processing apparatus of FIG. 1 has the same configuration as the handler shown in FIG. 4, and can operate as a handler.

When used as a generator, the / G terminal of the switch circuit 25 is set to “1”. As a result, the bus interrupt output unit 20 becomes active, and the bus interrupt input unit 21
And the bus interrupt output unit 22 becomes inactive. That is, the interrupt processing apparatus of FIG. 1 has the same configuration as the generator shown in FIG. 3, and can operate as a generator.

FIG. 2 is a diagram showing the configuration of an interrupt processing system using the interrupt processing apparatus shown in FIG. 1, wherein 26 is a CPU, 27 to 30 are interrupt processing apparatuses according to the embodiment of the present invention shown in FIG.
31 is a system bus.

In the figure, 27 is to operate as a handler
The / G terminal is set to “0”, and the 28/30 terminals are set to “1” to operate as a generator.

As described above, according to the embodiment of the present invention, since the interrupt processing device can be manufactured without distinguishing it as a handler or a generator, it is possible to reduce development and manufacturing costs.

[Effects of the Invention] As described above, according to the present invention, an interrupt processing device can be manufactured without being distinguished as a handler or a generator, so that development and manufacturing costs can be reduced.

In addition, since the user does not need to be aware of a handler or a generator, there is an advantage that the purchase and management of chips can be simplified.

[Brief description of the drawings]

1 is a block diagram showing the configuration of an interrupt processing apparatus according to an embodiment of the present invention, FIG. 2 is a diagram showing an interrupt processing system using the interrupt processing apparatus shown in FIG. 1, and FIG. 3 is a generator according to a conventional example. FIG. 4 is a configuration block diagram of an interrupt processing device as a handler according to a conventional example, and FIG. 5 is a diagram illustrating an interrupt processing system using the interrupt processing device according to a conventional example. It is. (Explanation of symbols) 1,6,18 ... local interrupt input unit, 2,7,19 ... level conversion unit, 3,20 ... bus interrupt output unit, 9,22 ... interrupt output unit, 8,21 … Bus interrupt input unit, 4, 10, 23… Interrupt acknowledge unit, 5, 11, 24… Vector generation unit, 25… Switch circuit, 12, 26… CPU, 13… Handler, 14 to 16 ... Generator, 27 to 30... Interrupt processing device according to the embodiment of the present invention, 17, 31.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Koichi Kuroiwa 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Co., Ltd. (72) Inventor Shinji Koyamada 1015 Ueodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu Microcomputer Systems Co., Ltd. (56) References JP-A-53-107252 (JP, A)

Claims (1)

(57) [Claims] A bus interrupt output unit for outputting a bus interrupt request signal in accordance with a local interrupt request signal; a bus interrupt input unit for inputting a bus interrupt request signal; An interrupt output unit that outputs an interrupt request signal to the central processing unit; and a switch circuit. When operating as a handler, the switch circuit is switched to activate the bus interrupt input unit and the interrupt output unit. When the bus interrupt output section is deactivated to operate as a generator, the switch circuit is switched to deactivate the bus interrupt input section and the interrupt output section to activate the bus interrupt output section. Characteristic interrupt processing device.