JP2626001B2 - Fluxless joining method - Google Patents
Fluxless joining methodInfo
- Publication number
- JP2626001B2 JP2626001B2 JP63314150A JP31415088A JP2626001B2 JP 2626001 B2 JP2626001 B2 JP 2626001B2 JP 63314150 A JP63314150 A JP 63314150A JP 31415088 A JP31415088 A JP 31415088A JP 2626001 B2 JP2626001 B2 JP 2626001B2
- Authority
- JP
- Japan
- Prior art keywords
- metal
- joint
- flux
- soldering
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
【発明の詳細な説明】 〔概要〕 本発明は大型電算機等に使用される半導体部品やその
周辺部品のはんだ付けに関し， 室温状態で部品搭載時にフラックスを全く用いずに接
合できることを目的とし， 室温以下で動作させる半導体等の部品のはんだ付けに
おいて，接合しようとする２つの部品のそれぞれの接合
部に，合金化させたときの融点が室温以下となる２種類
の金属Ａと金属Ｂを，一方の部品の接合部には金属Ａ
を，他方の部品の接合部には金属Ｂを付与し，該金属Ａ
と金属Ｂを該接合部にて，室温状態で直接相対して突き
合わせて溶融合金化させ，該部品の動作温度に冷却する
過程で接合部を凝固させるように構成する。DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to the soldering of semiconductor components and their peripheral components used in large computers and the like, with the object of being able to join at room temperature without using any flux when mounting the components. In the soldering of components such as semiconductors operated at room temperature or lower, two types of metal A and metal B whose melting point when alloyed is lower than room temperature are applied to each joint of the two components to be bonded. Metal A at the joint of one part
And a metal B is applied to the joint of the other part.
And the metal B are directly butted against each other at room temperature at the joint to form a molten alloy, and the joint is solidified in the process of cooling to the operating temperature of the component.
本発明は大型電算機などに使われる半導体部品やその
周辺部品のはんだ付けに関する。The present invention relates to soldering of a semiconductor component used for a large computer and the like and peripheral components thereof.
はんだ付けは通常フラックスを用いて加熱することで
行うが，フラックス残渣の洗浄が非常に難しいため，フ
ラックス残渣によるはんだ接合部あるいは部品そのもの
に悪影響を及ぼす恐れがある。Soldering is usually carried out by heating with a flux, but it is very difficult to clean the flux residue, so the flux residue may adversely affect the solder joint or the component itself.
このため，フラックスを用いないで接合する方法を開
発する必要がある。Therefore, it is necessary to develop a joining method without using flux.
従来のはんだ付け方法を第４図に示す。 FIG. 4 shows a conventional soldering method.
図中,13は部品,14は基板,15ははんだ付け用メタライ
ズ,16は各種はんだ,17はフラックスである。In the figure, 13 is a component, 14 is a board, 15 is a metallization for soldering, 16 is various solders, and 17 is a flux.
先ず，第４図（ａ）に示すように，部品13及び基板14
の上にはんだ付け用のメタライズ15を形成する。First, as shown in FIG.
A metallization 15 for soldering is formed on the substrate.
続いて，第４図（ｂ）に示すように，部品13及び基板
14のはんだ付け用メタライズの上に蒸着，めっき，ペー
スト印刷などの方法でPb−Sn系はんだ16を供給し，はん
だ表面にフラックス17を塗布する。Subsequently, as shown in FIG.
The Pb-Sn-based solder 16 is supplied onto the soldering metallization 14 by vapor deposition, plating, paste printing, or the like, and a flux 17 is applied to the solder surface.
次に，第４図（ｃ）に示すように，部品13と基板14を
突き合わせて200℃前後に加熱し，溶融接合する。Next, as shown in FIG. 4 (c), the component 13 and the substrate 14 are abutted, heated to about 200 ° C., and fusion-bonded.
最後に，第４図（ｄ）に示すように，トリクレンなど
の溶剤で全体の洗浄を行う。Finally, as shown in FIG. 4 (d), the whole is washed with a solvent such as trichlene.
ところが，小さな隙間などに入り込んだフラックス残
渣を取り除くことは非常に困難であり，この残存したフ
ラックス成分によるはんだ接合部や部品そのものへの悪
影響が懸念される。However, it is very difficult to remove the flux residue that has entered small gaps and the like, and there is a concern that this remaining flux component may adversely affect the solder joints and the components themselves.
フラックスは部品表面の酸化膜を除去し，表面を酸化
性雰囲気から被覆する目的で，電子部品ではロジン系の
ものが広く使われているが，トリクレンなどの有機溶剤
で洗浄した場合に，主要活性成分であるアミノ酸塩など
のイオン性物質が溶け難く，部品や基板上に残ってしま
う。Rosin-based flux is widely used for electronic components in order to remove the oxide film on the component surface and coat the surface from an oxidizing atmosphere. However, when the flux is washed with an organic solvent such as trichlene, the main activity is flux. Ionic substances such as amino acid salts, which are components, are difficult to dissolve and remain on components and substrates.
したがって，フラックスは部品や基板上に残渣として
残った場合，水分などの影響により，イオン性物質が解
離して，部品や基板の腐食，或いは電気絶縁破壊を起こ
して，部品の動作不良等の問題を生じていた。Therefore, if the flux remains as a residue on components or boards, ionic substances dissociate due to the effects of moisture, etc., causing corrosion of components or boards or electrical insulation breakdown, resulting in malfunctions of components. Was occurring.
本発明は，このフラックスによる悪影響を除くため
に，室温状態で部品搭載時にフラックスを全く用いずに
接合する方法を提供することを目的とする。An object of the present invention is to provide a method for joining components at room temperature without using any flux at the time of component mounting in order to eliminate the adverse effect of the flux.
第１図は，本発明の原理説明図である。 FIG. 1 is a diagram illustrating the principle of the present invention.
図において,1は部品,2は基板,3ははんだ付け用メタラ
イズ,4及び５は合金化すると融点が室温以下になる２種
の金属である。６は合金である。In the figure, 1 is a component, 2 is a substrate, 3 is a metallization for soldering, and 4 and 5 are two kinds of metals whose melting points become lower than room temperature when alloyed. 6 is an alloy.
第１図（ａ）に示すように，部品１の接合部に形成し
たはんだ付け用メタライズ３の上に金属A4を，又，基板
２の接合部に形成したはんだ付け用メタライズ３の上に
金属B5を付ける。As shown in FIG. 1 (a), a metal A4 is placed on the metallization 3 for soldering formed at the joint of the component 1, and a metal is placed on the metallization 3 for soldering formed at the joint of the substrate 2. Add B5.
次に，第１図（ｂ）に示すように，部品１と基板２の
２種の合金系金属A4と金属B5が相対する位置で突きあわ
せ，軽く圧力を掛ける。Next, as shown in FIG. 1 (b), the two alloy-based metals A4 and B5 of the component 1 and the substrate 2 are butted against each other at opposing positions, and light pressure is applied.
すると，第１図（ｃ）に示すように,2種の合金系金属
A4と金属B5の接触部の境界付近で拡散が始まり，はんだ
溶融する。Then, as shown in Fig. 1 (c), the two alloy-based metals
Diffusion starts near the boundary between the contact part of A4 and metal B5, and the solder melts.
これを低温域中に置いて凝固させれば，合金６とな
り，はんだの接合が完了する。If this is placed in a low-temperature region and solidified, it becomes alloy 6 and the joining of the solder is completed.
本発明では，第１図（ｂ）に示したように，合金の融
点が室温以下になる２種類の金属ＡとＢを突き合わせ，
軽く圧力を加えるようにして，合金を作るようにしてい
る。In the present invention, as shown in FIG. 1 (b), two kinds of metals A and B whose melting point of the alloy is lower than room temperature are butted,
The alloy is made by applying light pressure.
従って，半導体部品の接合部にこの２種類の金属を使
用すれば，部品の動作温度に冷却する過程で接合部を凝
固して接合でき，又，作動中も室温状態に戻すことによ
り，はんだ接合部の金属疲労を取り除き，接合部の劣化
を防止できる。Therefore, if these two types of metals are used in the joints of semiconductor components, the joints can be solidified and joined in the process of cooling to the operating temperature of the components, and by returning to room temperature during operation, solder joining can be achieved. The metal fatigue of the joint can be removed and the deterioration of the joint can be prevented.
更に，フラックスを使用しないため，フラックス残渣
による接合部の損傷がなく，信頼性が向上する。Furthermore, since no flux is used, there is no damage to the joint due to the flux residue, and the reliability is improved.
第２図は本発明の一実施例の工程順説明図である。 FIG. 2 is an explanatory view of a process sequence of one embodiment of the present invention.
図において,7はシリコンチップ,8はアルミナ基板,9は
はんだ付け用にメタライズした金（Au）,10はインジウ
ム（In）,11はガリウム（Ga）,12はインジウム・ガリウ
ム合金である。In the figure, 7 is a silicon chip, 8 is an alumina substrate, 9 is gold (Au) metallized for soldering, 10 is indium (In), 11 is gallium (Ga), and 12 is an indium-gallium alloy.
ここでは，合金化して融点が室温以下になる金属とし
て,InとGaを使用した。Here, In and Ga were used as the alloyed metal whose melting point was lower than room temperature.
先ず，第２図（ａ）で示すように，シリコンチップ７
とアルミナ基板８の双方の端子領域にはんだ付け用メタ
ライズとしてAu9を1,000Åの厚さに蒸着し，その上にIn
10を100μの厚さに蒸着する。First, as shown in FIG.
Au9 is deposited in a thickness of 1,000 mm as a metallization for soldering on both terminal areas of the substrate and the alumina substrate 8, and In is further formed thereon.
10 is deposited to a thickness of 100μ.
次に，アルミナ基板８の端子領域のIn10の上に，蒸着
したInと同一サイズで厚さが1mmのGa片11を載せる。Next, on the In10 in the terminal area of the alumina substrate 8, a Ga piece 11 having the same size as the deposited In and a thickness of 1 mm is placed.
この場合に，シリコンチップ７とアルミナ基板８の双
方の端子領域のAu9の上に蒸着したIn10の総量は,Ga片11
とIn10の合計量の容積比で約17％，重量比で約24％とな
り，第３図に示したインジウム・ガリウム金相図で表さ
れるように，合金化した状態の場合には,20℃において
溶融状態となっている。In this case, the total amount of In10 deposited on Au9 in the terminal areas of both the silicon chip 7 and the alumina substrate 8 is the Ga piece 11
The total volume of In and In10 is about 17% by volume and about 24% by weight. As shown in the indium-gallium-gold phase diagram shown in Fig. 3, in the alloyed state, 20% It is in a molten state at ° C.
従って，第２図（ｂ）に示すように，アルミナ基板８
の端子領域上に載せたGa片11の上に，シリコンチップ７
のIn側を下にして,In10とGa11を突き合わせ，軽く20〜1
00g/cm2の圧力を加えると，第２図（ｃ）に示すように,
In10とGa11が溶融してInGa合金12となり，これを０℃で
５分間放置すると，凝固して溶融接合が完了する。Therefore, as shown in FIG.
Silicon chip 7 on Ga piece 11 placed on the terminal area of
With In side down, butt In10 and Ga11 and lightly
When a pressure of 00 g / cm 2 is applied, as shown in FIG.
In10 and Ga11 are melted to form InGa alloy 12, which is left at 0 ° C. for 5 minutes to solidify and complete the fusion bonding.
以上説明したように，本発明によれば，はんだ付けの
際にフラックスを用いないため，フラックス成分による
腐食や絶縁破壊などの悪影響が生じない。又，温度を掛
けなくて済み，部品の動作中にはんだ接合部が受けた金
属疲労も室温に戻せば完全に回復される等の効果があ
る。As described above, according to the present invention, since no flux is used at the time of soldering, adverse effects such as corrosion and dielectric breakdown due to the flux component do not occur. In addition, there is an effect that the temperature does not need to be applied, and the metal fatigue received by the solder joint during the operation of the component is completely recovered if the temperature is returned to room temperature.
第１図は本発明の原理説明図， 第２図は本発明の１実施例の工程順説明図， 第３図はインジウム・ガリウム金相図， 第４図ははんだ付けの従来例の説明図 である。 図において， １は部品， ２は基板， ３ははんだ付け用メタライズ， ４は金属A, ５は金属B, ６は合金， ７はシリコンチップ， ８はアルミナ基板， ９は金， 10はインジウム， 11はガリウム， 12はインジウム・ガリウム合金 である。 FIG. 1 is an explanatory view of the principle of the present invention, FIG. 2 is an explanatory view of a process sequence of one embodiment of the present invention, FIG. 3 is an indium-gallium gold phase diagram, and FIG. It is. In the figure, 1 is a component, 2 is a substrate, 3 is a metallization for soldering, 4 is a metal A, 5 is a metal B, 6 is an alloy, 7 is a silicon chip, 8 is an alumina substrate, 9 is gold, 10 is indium, 11 is gallium and 12 is indium-gallium alloy.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平１−187997（ＪＰ，Ａ) 特開 昭60−124947（ＪＰ，Ａ) 特開 昭63−306634（ＪＰ，Ａ) ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-187997 (JP, A) JP-A-60-124947 (JP, A) JP-A-63-306634 (JP, A)
Claims (1)
んだ付けにおいて，接合しようとする２つの部品のそれ
ぞれの接合部に，合金化させたときの融点が室温以下と
なる２種類の金属Ａと金属Ｂを，一方の部品の接合部に
は金属Ａを，他方の部品の接合部には金属Ｂを付与し，
該金属Ａと金属Ｂを該接合部にて，室温状態で直接相対
して突き合わせて溶融合金化させ，該部品の動作温度に
冷却する過程で接合部を凝固させることを特徴とするフ
ラックスレス接合方法。When soldering a component such as a semiconductor which is operated at room temperature or lower, two kinds of metal A whose melting point when alloyed is lower than room temperature are added to respective joints of two components to be bonded. And metal B, metal A to the joint of one part and metal B to the joint of the other part,
Fluxless joining, wherein the metal A and the metal B are directly opposed to each other at the joint at room temperature to form a molten alloy, and the joint is solidified in the process of cooling to the operating temperature of the component. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63314150A JP2626001B2 (en) | 1988-12-13 | 1988-12-13 | Fluxless joining method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63314150A JP2626001B2 (en) | 1988-12-13 | 1988-12-13 | Fluxless joining method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02159047A JPH02159047A (en) | 1990-06-19 |
| JP2626001B2 true JP2626001B2 (en) | 1997-07-02 |
Family
ID=18049831
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63314150A Expired - Lifetime JP2626001B2 (en) | 1988-12-13 | 1988-12-13 | Fluxless joining method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2626001B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04240741A (en) * | 1991-01-24 | 1992-08-28 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| US5610371A (en) * | 1994-03-15 | 1997-03-11 | Fujitsu Limited | Electrical connecting device and method for making same |
| JP3356840B2 (en) * | 1993-10-14 | 2002-12-16 | 富士通株式会社 | Electrical connection device and method of forming the same |
| JP2570626B2 (en) * | 1994-08-31 | 1997-01-08 | 日本電気株式会社 | Board connection structure and connection method |
| JP2002289768A (en) | 2000-07-17 | 2002-10-04 | Rohm Co Ltd | Semiconductor device and its manufacturing method |
| JP4036786B2 (en) * | 2003-04-24 | 2008-01-23 | 唯知 須賀 | Electronic component mounting method |
| JP4819608B2 (en) * | 2006-07-31 | 2011-11-24 | 富士フイルム株式会社 | Liquid ejection head, liquid ejection apparatus, and image forming apparatus |
-
1988
- 1988-12-13 JP JP63314150A patent/JP2626001B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02159047A (en) | 1990-06-19 |
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