JP2622527B2 - DMA controller - Google Patents

Description

The present invention relates to a DMA (Direct Memory Access) controller.

[Conventional technology]

Conventionally, DMA transfer is known as a technique for transferring a set of data in block units. When data is DMA-transferred from a memory at a transfer source to a memory at a transfer destination, a DMA transfer is performed.
As shown in the figure, the host gives the DMA controller 1 a transfer start address n and a transfer word number d of the transfer source memory 2 or a transfer end address of the transfer source memory 2. When the DMA controller 1 receives the DMA request signal, it first reads data from the transfer start address n of the memory 2 of the transfer source, writes this data to the head address n 'of the memory 3 of the transfer destination, and then writes After incrementing (or decrementing) the designated addresses of the transfer source memory 2 and the transfer destination memory 3, the address n + 1 of the transfer source memory 2 is obtained.
, And writes the data to the address n '+ 1 of the memory 3 of the transfer destination, and repeats such an operation to DMA-transfer the data of d words from the memory 2 of the transfer source to the memory 3 of the transfer destination. ing.

In addition, an image of an object to be recognized is taken by a camera, and image data from the camera is written in a frame memory in a matrix form. Then, the image data is read out linearly from the frame memory and processed to recognize the object. An image recognition system has been proposed.

[Problems to be solved by the invention]

The DMA controller 1 DMA-transfers data from the transfer source memory 2 to the transfer destination memory 3 while incrementing (or decrementing) the designated addresses of the transfer source memory 2 and the transfer destination memory 3. Data can only be sequentially DMA-transferred from consecutive addresses in the memory 2 to the transfer-destination memory 3,
Data cannot be randomly transferred from the transfer source memory 2 to the transfer destination memory 3 by DMA. Therefore, for example, in the above-described image recognition system, FFT (Fast Fourier Transfer) is performed using specific data in a frame memory.
The DMA controller 1 is useless when performing calculations. In addition, since the data in units of words is DMA-transferred, the data transfer process is performed using both the address and the number of words, so that the processing time becomes longer and the hardware configuration becomes complicated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a DMA controller capable of improving the above-mentioned disadvantages and randomly transferring data from a transfer source memory to a transfer destination memory by DMA, thereby realizing high-speed processing.

[Means for solving the problem]

In order to achieve the above object, the present invention provides a DMA controller which DMA-transfers data from a source memory storing data in a matrix to a destination memory as shown in FIG. A plurality of data addresses for cutting out from the memory into a curve such as a circle are written in advance in the addressing memory 11, and the data addresses written in the addressing memory 11 are used to transfer data from the source memory. Addresses for cutting out in a curved line are sequentially designated one by one in the memory of the transfer source, and data of addresses arranged in a curve are sequentially cut out from the memory of the transfer source, and the memory of the transfer destination is sequentially cut out. Addressing means 12 for performing DMA transfer to the CPU.

[Action]

In the addressing memory 11, a plurality of data addresses composed of curved coordinate data such as a circle to be cut out from the transfer source memory are written in advance, and the addressing means 12
By using the data address written in the addressing memory 11, a data address for cutting out from the transfer source memory in a curved shape is specified and cut out one by one sequentially in the transfer source memory, and cut out. DMA transfer is performed to the transfer destination memory.

〔Example〕

 FIG. 2 shows an embodiment of the present invention.

The DMA controller 21 according to this embodiment includes an addressing memory 22 including a cut-out address memory, a pointer 23,
It has address registers 24, 25, a multiplexer 26, a temporary register 27, and a counter 28, and has a transfer source memory 29 and a transfer destination memory 30, data buses 31, 32, and an address bus 3.
3 connected.

In this embodiment, in the image recognition system, as shown in FIG. 5, a circular address (circular) centered on the address (x, y) among the data stored in a matrix form in the frame memory 29 of the transfer source. Are used for DMA transfer of n pieces of data D ₁ , D ₂ , D _3, ... Of the circular image stored at the addresses arranged in a linear manner. This image recognition system is a system that discriminates coins (for example, coins such as 100 yen coins). The coins are imaged by a camera, converted into image data according to light intensity by a CCD, and this image data is stored in a frame memory. After writing in 29, processing is performed to recognize the coin. Also, when determining whether a coin is a 100 yen coin,
It is checked whether the coin circumference data matches the model value stored in the memory in advance.This is done by extracting only the coin circumference data from the image data in the frame memory 29 and performing an FFT operation to obtain the angle and the angle. This may be performed by obtaining a spectrum of the intensity and comparing the spectrum with the model value. This embodiment is an example in which only data for performing the FFT operation is DMA-transferred from the frame memory 29.

The cut-out address memory 22 stores in advance a plurality of circular linear addresses in which the data of the coordinates of the circle to be cut out (circular data D ₁ , D ₂ , D ₃ ... Dm of the coins in the frame memory 29 are stored). _{data) (x 1, y 1)} , (x 2, y 2), (x 3,
y ₃ ), ..., (xm, ym) are written in order. When a DMA request signal is input from the host and a DMA transfer of data is requested, the DMA controller 21 performs the operations shown in FIGS.
As shown in the figure, first, the pointer 23 and the counter 28 are initialized. Then, the DMA controller 21 reads out the first address data (x ₁ , y ₁ ) from the address specified by the pointer 23 in the cut-out address memory 22 in synchronization with the reference clock, and sets the read address data in the address register 24. 24 address data (x ₁ ,
y ₁ ) is output to the transfer source memory 29 via the multiplexer 26 and the address bus 33. In addition, DMA controller 21
Outputs a read signal to the transfer source memory 29,
To read the image data D ₁ from the address designated by the address data (x _1, y ₁₎ in the. The image data D ₁ is transferred to the temporary register 27 via the data bus 31. Next, the DMA controller 21 sets the data (1) of the start address of the transfer destination memory 30 from the counter 28 to the address register 25 in synchronization with the next reference clock, and the address data (1) of the address register 25 is set. Is output to the transfer destination memory 30 via the multiplexer 26 and the address bus 33. Then, DMA controller 21, the transfer destination memory 30 outputs the write signal, the start address designated by the address data (1) in the transfer destination memory 30, writes the image data D ₁ of the the temporary register 27 Let

Here, in the above image recognition system, the coin is imaged by the camera in the same size, but the positional relationship between the coin and the camera is not constant. Therefore, in this embodiment, it is unclear which position in the memory 29 of the transfer source the image data is located (circular data D ₁ , D ₂ , D ₃ ... Of the coins).
Dm enters an arbitrary position in the transfer source memory 29). Therefore, in this embodiment, at the time of the initial setting, as shown in FIG. 6, the circumference data D ₁ , D ₂ ,
The center position of the circular address 34 in which D ₃ ... Dm enters is previously calculated from the image data in the memory 29 of the transfer source, and the center position of the circular address 34 and the circumferential data D ₁ , D ₂ , D ₃ . The difference (dx, dy) from the center position of the circular address 35, which is the reference for entering, is obtained, and this difference (dx, dy) is added to the address data from the extraction address memory 22 as shown in FIG. Container 36,3
Add 7

Next, the DMA controller 21 increments the pointer 23 and the counter 28 in synchronization with the next reference clock,
The next address data (x ₂ , y ₂ ) is read from the address specified by the pointer 23 in the cut-out address memory 22, and the difference (dx, dy) is added thereto by the adders 36 and 37, and then the addition is performed. Set the result in address register 24,
The address data of this address register 24 (x ₂ + dx, y ₂
+ Dy) is output to the transfer source memory 29 via the multiplexer 26 and the address bus 33. In addition, DMA controller 2
1 outputs a read signal to the transfer source memory 29 and
Address data _{(x 2 + dx, y 2} + dy) in 9 to read the image data D ₂ from the address designated by. The image data D ₂ is transferred to the temporary register 27 via the data bus 31. Next, the DMA controller 21 sets the data (2) at the next address of the transfer destination memory 30 from the counter 28 to the address register 25 and sets the data from the counter 28 to the address register 25 in synchronization with the next reference clock. The address data (2) of the address register 25 is output to the transfer destination memory 30 via the multiplexer 26 and the address bus 33. Then, the DMA controller 21 outputs a write signal to the transfer destination memory 30, and
The address specified by the address data (2) in 30 to write the image data D ₂ from the temporary register 27.

DMA controller 21, the address in subsequent Similarly pointer 23 and the counter 28 is incremented while the transfer source memory 29 _{(x 3 + dx, y 3} + dy), ..., (xm + dx, ym +
sequentially DMA transfers one address at a time the image data D ₃ ... Dm stored in dy).

FIG. 8 shows another embodiment of the present invention, and FIG. 9 shows a timing chart thereof. This embodiment is an example in which the dedicated address buses 33a and 33b are provided in the transfer source memory 29 and the transfer destination memory 30 in the above-described embodiment, respectively.
Each address data of the address registers 24 and 25 is individually output to the source memory 29 and the destination memory 30 via the address buses 33a and 33b. This embodiment operates in the same manner as the above embodiment, and the same parts as those in the above embodiment are denoted by the same reference numerals.

In the above embodiment, the addressing memory 22 is used.
Not as the address pointer of the source memory 29,
Even when used as an address pointer of the transfer memory 30, data is randomly transferred from the transfer source memory 29 to the transfer destination memory 30.
DMA transfer is possible. In addition, not only circular address data in the transfer source memory 29 or the transfer destination memory 30 but also address data of an arbitrary shape such as linear or semicircular are put into the address designating memory 22, and data of the address is stored. Although DMA transfer may be performed, the present invention targets curved address data. Also,
Flexible DM by making each component programmable
A controller may be realized.

〔The invention's effect〕

As described above, according to the present invention, in a DMA controller that DMA-transfers the data from a source memory storing data in a matrix to a destination memory, a circular shape such as a circle is formed from the source memory. An addressing memory 11 in which a plurality of data addresses to be cut out are written in advance, and an address for cutting out a curve from the transfer source memory using the address of the data written in the addressing memory 11 Addressing means for sequentially designating the data of the addresses arranged in a curved line from the memory of the transfer source in order and sequentially transferring the data of the addresses arranged in a curved line from the memory of the transfer source to the memory of the transfer destination. 12 so that data can be randomly DMA-transferred from the memory at the transfer source to the memory at the transfer destination. It is effectively etc.. Furthermore, a plurality of data are sequentially cut out from the memory of the transfer source one by one in a curved manner and DMA-transferred to the memory of the transfer destination, so that the data transfer process can be performed only by the address and the number of words can be processed. The processing of the configuration and the number of words can be eliminated, and the configuration can be simplified and high-speed processing can be realized.

[Brief description of the drawings]

1 is a block diagram showing the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a timing chart of the embodiment, and FIG. 4 is a flowchart showing a processing flow of the embodiment. , FIGS. 5 and 6 are block diagrams for explaining the embodiment, FIG. 7 is a block diagram showing a part of the embodiment, and FIG. 8 is a block diagram showing another embodiment of the present invention. ,
FIG. 9 is a timing chart of the embodiment, and FIG. 10 is a block diagram for explaining a conventional DMA controller. 11 ... Address designation memory, 12 ... Address designation means.

Claims (1)

(57) [Claims] 1. A DMA controller for DMA-transferring data from a memory at a transfer source storing data in a matrix to a memory at a transfer destination. Using the addressing memory 11 in which a data address has been written in advance and the data address written in the addressing memory 11, addresses for cutting out in a curved manner from the memory of the transfer source are sequentially sequentially shifted one by one. Address designating means 12 for designating the transfer source memory to sequentially cut out data of addresses arranged in a curve from the transfer source memory and performing DMA transfer to the transfer destination memory. DMA controller.