JP2615891B2 - Memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is called a contact program type mask ROM, and a memory device in which the presence or absence of a contact to an impurity diffusion region of a transistor corresponds to stored information. It is about.

[Summary of the Invention]

According to the present invention, in a memory device as described above, a wiring layer is provided above an impurity diffusion region of a transistor, and a contact hole is formed to reach the impurity diffusion region and expose a side wall of the wiring layer. By writing the stored information with the embedding of the conductive layer, the TA
T is shortened and high reliability can be obtained.

[Conventional technology]

Conventionally, in a contact program type mask ROM, as shown in FIG. 1A, a transistor 12, an SiN film 13 as a passivation film, and an AsSG film 14 as a reflow film are formed on a Si substrate 11, and this AsSG film 14 is formed. Was reflowed and the wafer was stored.

After receiving the code data from the user, a contact hole (not shown) reaching the source / drain region 15 which is an impurity diffusion region in the Si substrate 11 is written in the AsSG film 14 and the SiN film 13 in order to write storage information. Then, the Al holes (not shown) are patterned by filling the contact holes, and various processes are performed until the memory device is completed.

[Problems to be solved by the invention]

However, patterning of Al wiring requires many steps such as sputtering of Al, application and patterning of resist, etching of Al, and removal of resist.

Therefore, in the conventional mask ROM as described above, TAT (turn
around time-after receiving the code data from the user,
The time required to deliver the product is long, and the product is low.

[Means for solving the problem]

The memory device according to the present invention includes a wiring layer 16 provided above the impurity diffusion region 15 and a contact formed selectively and reaching the impurity diffusion region 15 and exposing a side wall of the wiring layer 16. A hole 21, and a conductive layer 22 filling the contact hole 21 and contacting the wiring layer 16 and the impurity diffusion region 15, respectively, and forming the contact hole 21 and filling the conductive layer 22. Is stored information.

[Action]

In the memory device according to the present invention, since the storage information is written by forming the contact hole 21 and embedding the conductive layer 22 in the contact hole 21, the wiring layer 16 is patterned before writing the storage information. be able to.

Therefore, if the conductive layer 22 is selectively buried in the contact hole 21, the number of steps required for writing the stored information is smaller than in the case where the contact hole 21 is buried and the wiring layer 16 is patterned.

In addition, the conductive layer 22 fills the contact hole 21 to form a wiring layer.
16 and the impurity diffusion region 15 are in contact,
Compared to the case where the wiring layer 16 fills the contact hole 21,
The wiring layer 16 has good step coverage. Further, the conductive layer 22 may be a barrier metal.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIG.

FIG. 1 shows a manufacturing process of this embodiment. Also in this embodiment, the steps up to the step shown in FIG. 1A are performed in the same manner as in the above-described conventional example.

Thereafter, in the present embodiment, as shown in FIG.
Although located in the upper layer of the drain region 15, this source
The Al wiring 16 not connected to the drain region 15 is covered with an AsSG film.
Patterned on 14 and PS as overcoat film
A relatively thin G film 17 is deposited by CVD.

In the present embodiment, the wafer is stored in the state shown in FIG. 1B, and after receiving the code data from the user, a process subsequent to FIG. 1B is performed to write the storage information.

That is, when receiving the code data from the user, the PSG film 17
A contact mask (not shown) for programming is first formed by applying and patterning a resist thereon.

Then, a contact hole 21 is formed as shown in FIG. 1C by etching using this contact mask,
After that, the contact mask is removed.

Contact hole 21 is PSG film 17, Al wiring 16, AsSG film 1
4, penetrating through the SiN film 13 to reach the source / drain region 15, so that the side wall of the Al wiring 16 is exposed.

Next, selective contact CVD of tungsten is performed to fill the contact holes 21 with tungsten 22 as shown in FIG. 1D.
As a result, the Al wiring 16 and the source / drain region 15 are in contact with each other via the tungsten 22.

The selective CVD of tungsten utilizes the fact that the deposition rate of tungsten is large on the surface of Si or a metal and small on the insulating film such as a silicon oxide film (for example, “Monthly Semi”
conductor World "Press Journal (1987.10) p.88
~ 93).

That is, since the surface of the Si substrate 11 is exposed in the contact hole 21, the tungsten 22 is exclusively deposited in the contact hole 21. However, PSG film 1 which is Si oxide film
Selective CVD because tungsten 22 is slightly deposited on 7
After that, the tungsten 22 is lightly etched.

Next, as shown in FIG. 1E, a PSG film 23 is deposited by CVD. The PSG film 23 is deposited so that the total thickness of the PSG film 23 and the PSG film 17 is about 7000 mm.

After that, similarly to the conventional memory device, a plasma SiN film 24 as an overcoat film is deposited by CVD, and the Al wiring 16 is formed.
An opening (not shown) for an electrode pad with respect to
Do a sinter.

In the present embodiment as described above, the storage information is written by the formation of the contact hole 21 and the selective CVD and light etching of the tungsten 22, and the patterning of the Al wiring 16 is already performed prior to the writing of the storage information. I have.

Therefore, in the present embodiment, the TAT is compared with the conventional example in which the stored information is written by the formation of the contact hole and the patterning of the Al wiring requiring many steps as described above.
Is short.

Further, since the tungsten 22 fills the contact hole 21, the step coverage of the Al wiring 16 is better than that of the conventional example in which the Al wiring fills the contact hole without performing reflow of the AsSG film 14, for example. . Therefore, the present embodiment has higher reliability than the conventional example.

Tungsten 22 is interposed between the Al wiring 16 and the Si substrate 11, and the tungsten 22 functions as a barrier metal. Therefore, the present embodiment has higher reliability than the conventional example in which the Al wiring and the Si substrate are in direct contact with each other.

In this embodiment, the tungsten 22 is used to fill the contact hole 21, but a refractory metal other than the tungsten 22 that can be selectively CVD may be used.

Also, for consistency with tungsten 22, Al wiring 16
Instead, a polycrystalline Si wiring, a tungsten wiring, or the like may be used.

[Effects of the Invention] In the memory device according to the present invention, the number of steps required for writing the stored information is small, so that the TAT is short.

In addition, since the wiring layer has good step coverage and the conductive layer can be made of a barrier metal, the reliability is high.

[Brief description of the drawings]

FIG. 1 is a side sectional view sequentially showing a manufacturing process of one embodiment of the present invention. In the reference numerals used in the drawings, 12 ... transistor 15 ... source / drain region 16 ... Al wiring 21 ... contact hole 22 ... tungsten.

Claims (1)

(57) [Claims] 1. A memory device in which presence / absence of a contact to an impurity diffusion region of a transistor corresponds to storage information, wherein the wiring device is selectively formed with a wiring layer provided above the impurity diffusion region. A contact hole reaching the impurity diffusion region and exposing a side wall of the wiring layer; and a conductive layer filling the contact hole and contacting the wiring layer and the impurity diffusion region. A memory device in which the storage information is written by forming a hole and filling the conductive layer.