JP2613967B2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JP2613967B2 JP2613967B2 JP2272760A JP27276090A JP2613967B2 JP 2613967 B2 JP2613967 B2 JP 2613967B2 JP 2272760 A JP2272760 A JP 2272760A JP 27276090 A JP27276090 A JP 27276090A JP 2613967 B2 JP2613967 B2 JP 2613967B2
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- Prior art keywords
- power supply
- transistor
- power
- semiconductor integrated
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Dram (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路に関し、特に電源電圧が異な
る２電源以上を有した半導体集積回路に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having two or more power supplies having different power supply voltages.
従来、この種の半導体集積回路は、第７図，第８図に
示すように、各電源VCC,VDD,VSSから直接内部回路１の
電源供給ライン２に接続されていた。Conventionally, this type of semiconductor integrated circuit is directly connected to the power supply line 2 of the internal circuit 1 from each of the power supplies VCC, VDD, and VSS, as shown in FIGS.
第８図において、内部回路１として、相補なる電界効
果トランジスタの直列体を複数段接続した回路例が示さ
れている。FIG. 8 shows, as the internal circuit 1, a circuit example in which a series body of complementary field-effect transistors is connected in a plurality of stages.
前述した従来の半導体集積回路の断面図は、第９図の
ようになっており、寄生素子が存在することがわかる。FIG. 9 is a cross-sectional view of the above-described conventional semiconductor integrated circuit, which indicates that a parasitic element exists.
第９図において、N-型半導体基板（サブストレイト）
10内に、Ｐウェル領域11が形成され、このＰウェル領域
11内にP+領域12,15,N+領域13,14が形成され、基板10内
のN-領域内にP+領域17,18,N+領域16,19が形成される。
入力信号INは、ゲート電極に接続される。ここで、P+領
域18をエミッタ,Pウェル領域11をコレクタ，基板10をベ
ースとするトランジスタTr1と、N+領域13をエミッタ，
基板10をコレクタ,Pウェル領域11をベースとするトラン
ジスタTr2とが形成され、さらにＰウェル領域11と電源V
SSとの間に抵抗R2,電源VDDと基板10との間に抵抗R1が存
在する。In FIG. 9, N - type semiconductor substrate (substrate)
A P-well region 11 is formed in 10, and this P-well region
P + regions 12 and 15 in the 11, N + regions 13 and 14 are formed, N of the substrate 10 - in the region P + regions 17, 18, N + regions 16 and 19 are formed.
The input signal IN is connected to a gate electrode. Here, a transistor Tr1 having a P + region 18 as an emitter, a P well region 11 as a collector, a substrate 10 as a base, and an N + region 13 as an emitter,
A transistor Tr2 having a substrate 10 as a collector and a P-well region 11 as a base is formed.
A resistor R2 exists between the power supply VDD and the power supply VDD, and a resistor R1 exists between the power supply VDD and the substrate 10.
第９図の寄生素子を等価回路として表わしたのが、第
10図である。第10図について説明する。電源投入時等に
低電位用電源VCCが、最高電位用電源VDD（基板電位）よ
りも高くなり、寄生PNP型バイポーラトランジスタTr1の
エミッタ−ベース間順方向電圧VF1よりも高くなるとト
ランジスタTr1が導通し、抵抗R2を介して電流が流れる
為、節点Ｘの電位が高くなり、この電位が寄生バイポー
ラトランジスタTr2のベース−エミッタ間順方向電圧VF2
よりも高くなるとトランジスタTr2が導通し、抵抗R1を
介して、電源VDDから電流が流れると共に、トランジス
タTr1のベースからも電流を引くことになり、トランジ
スタTr1とトランジスタTr2とで構成されるサイリスタが
動作し、電源VCC−VSS間に過大電流が流れ、ボンディン
グワイヤ切れ、または素子破壊を起こすという欠点があ
った。そのため、電源を投入する際、必ず電源VDDが電
源VCCよりも高くする必要があった。FIG. 9 shows the parasitic element of FIG. 9 as an equivalent circuit.
FIG. FIG. 10 will be described. When the power supply VCC for low potential becomes higher than the power supply VDD (substrate potential) for the highest potential and becomes higher than the forward voltage V F1 between the emitter and base of the parasitic PNP type bipolar transistor Tr 1 when the power is turned on, the transistor Tr 1 There conduct, since the current flows through the resistor R2, the potential of the node X is increased and the base this potential of the parasitic bipolar transistor Tr 2 - emitter forward voltage V F2
When it becomes higher, the transistor Tr 2 conducts, and current flows from the power supply VDD through the resistor R 1 , and also draws current from the base of the transistor Tr 1 , which is composed of the transistor Tr 1 and the transistor Tr 2 Thyristor operates, an excessive current flows between the power supply VCC and VSS, and the bonding wire is cut or the element is destroyed. Therefore, when the power is turned on, the power VDD needs to be always higher than the power VCC.
本発明の構成は、内部回路に電源を供給する第1,第2,
第３の電源ラインと、前記第1,第2,第３の電源ラインに
それぞれ電源を供給する第1,第2,第３の電源端子を備
え、前記第１及び第２の電源端子に同一極性で異なる電
圧を印加し、前記第３の電源端子に前記第１の電源端子
に印加される電圧と逆極性の電圧を印加する半導体集積
回路において、前記第１の電源端子と前記第１の電源ラ
インとの間に電界効果トランジスタのソース・ドレイン
を挿入し、前記トランジスタのゲートを前記第２の電源
端子に接続したことを特徴とする。The configuration of the present invention provides first, second,
A third power line, and first, second, and third power terminals for supplying power to the first, second, and third power lines, respectively, the same as the first and second power terminals; In a semiconductor integrated circuit for applying a voltage having a different polarity and applying a voltage having a polarity opposite to a voltage applied to the first power supply terminal to the third power supply terminal, the first power supply terminal and the first power supply terminal A source / drain of a field-effect transistor is inserted between the power supply line and the power supply line, and a gate of the transistor is connected to the second power supply terminal.
次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例の半導体集積回路の回
路図である。FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.
第１図に示すように、本第１の実施例は、電源VCCに
Ｎ型MOSトランジスタMN1のドレインが接続され、内部回
路１の電源供給ラインにソースが、ゲートには電源VDD
がそれぞれ接続されている。Ｎ型MOSトランジスタNM1の
導通抵抗を小さく設定しておくことにより、電源VDDが
電源VCCよりトランジスタMN1のしきい値電圧VTN以上高
くなっている時は、電源VCCからトランジスタMN1を介し
て内部回路１に供給される為、従来と同等な特性が得ら
れる。次に、電源VDDが電源VCCよりも低くなると、トラ
ンジスタMN1のゲート電圧も低くなり、内部回路１への
供給が停止する。As shown in FIG. 1, in the first embodiment, the drain of the N-type MOS transistor MN1 is connected to the power supply VCC, the source is connected to the power supply line of the internal circuit 1, and the power supply VDD is connected to the gate.
Are connected respectively. By setting a small conduction resistance of the N-type MOS transistors NM1, when the power supply VDD is higher than the threshold voltage V TN of the transistor MN1 from the power source VCC, the internal circuit from the power supply VCC via the transistor MN1 1, the same characteristics as the conventional one can be obtained. Next, when the power supply VDD becomes lower than the power supply VCC, the gate voltage of the transistor MN1 also becomes low, and the supply to the internal circuit 1 is stopped.
次に本実施例の寄生素子について、第４図，第５図で
示す。Next, the parasitic element of this embodiment is shown in FIGS.
第５図において、本実施例の半導体集積回路は、N-型
の（サブストレイト）基板20内に、Ｐウェル領域21,22
等が形成される。（本回路は、第４図に示す相補なる電
界効果トランジスタの直列体を複数接続したものであ
る。）Ｐウェル領域21内には、N+領域24,25があり、境
界上にP+領域23,26があり、基板20内にはN+領域27,30が
あり、P+領域29,P領域28があり、Ｐウェル領域22内にN+
領域32,33があり、境界上にP+領域31,34がある。In FIG. 5, a semiconductor integrated circuit according to the present embodiment has P-well regions 21 and 22 in an N − type (substrate) substrate 20.
Are formed. (This circuit is obtained by connecting a plurality of complementary field effect transistors in series as shown in FIG. 4.) In the P well region 21, there are N + regions 24 and 25, and the P + region is located on the boundary. There are 23 and 26, the substrate 20 has N + regions 27 and 30, there is P + region 29, P region 28, N in the P-well region 22 +
There are regions 32 and 33, and there are P + regions 31 and 34 on the boundary.
第４図において、電源VDD,VSSは直接電源供給ライン
２に接続され、電源VCCはトランジスタMN1を介して接続
される。In FIG. 4, power supplies VDD and VSS are directly connected to a power supply line 2, and a power supply VCC is connected via a transistor MN1.
第５図において、P+領域29をエミッタ,Pウェル領域21
をコレクタ，基板20をベースとするトランジスタTr
1と、N+領域24をエミッタ・基板20をコレクタ,Pウェル
領域21をベースとするトランジスタTr2とが形成され、
さらにトランジスタTr2のコレクタと電源VDDとの間に抵
抗R1,トランジスタTr2のベースと電源VSSとの間に抵抗R
2が介在する。さらに、電源VCCとトランジスタTr1のエ
ミッタとの間にダイオードＤが介在する形となる。In FIG. 5, a P + region 29 is an emitter, a P well region 21
Is a collector and the transistor Tr is based on the substrate 20
1 and a transistor Tr 2 having an N + region 24 as an emitter / substrate 20 as a collector and a P well region 21 as a base,
Moreover transistor resistance between Tr 2 of the collector and a power supply VDD R1, resistor R between the base and the power source VSS of the transistor Tr 2
2 intervenes. Furthermore, the form of the diode D is interposed between the emitter of the power source VCC and the transistor Tr 1.
第５図に示すように、寄生素子は本実施例のＮ型MOS
トランジスタにも存在し、第６図に示すように、電源VC
CとトランジスタTr1との間に逆バイアスされるようにダ
イオードＤが接続され、このダイオードＤがブレークダ
ウンしないかぎり、トランジスタTr1とトランジスタTr2
とで構成されるサイリスタには電流が流れない。As shown in FIG. 5, the parasitic element is the N-type MOS of this embodiment.
There is also a transistor, and as shown in FIG.
Diode D as a reverse bias between the C and the transistor Tr 1 is connected, as long as the diode D does not break down, transistor Tr 1 and the transistor Tr 2
No current flows through the thyristor composed of.
つまり、電源VDDの電位VCCよりも低い時は、電源VCC
からの内部回路１への供給、および寄生素子への供給が
なくなり、ラッチアップが起きることはなく、ボンディ
ングワイヤ切れ、素子破壊という問題が解消される。In other words, when the potential is lower than the potential VCC of the power supply VDD,
No supply to the internal circuit 1 and no supply to the parasitic element is caused, latch-up does not occur, and the problem of broken bonding wire and element destruction is solved.
第２図は本発明の第２の実施例の回路図である。 FIG. 2 is a circuit diagram of a second embodiment of the present invention.
第２図において、本第２の実施例はＰ型基板の場合で
ある。In FIG. 2, the second embodiment is for a P-type substrate.
（前記第１の実施例は、Ｎ型基板の場合である。）第
２図に示すように、本第２の実施例は、電源VEEにＰ型M
OSトランジスタMP1のドレインが接続され、内部回路１
の電源供給ラインにソースが、ゲートに電源VSSがそれ
ぞれ接続されている。Ｐ型MOSトランジスタMP1の導通抵
抗を小さく設定しておくことにより、電源VSSが電源VEE
よりトランジスタMP1のしきい値VTP以上低くなっている
時は、電源VEEからトランジスタMP1を介して内部回路１
に供給される為、従来と同等な特性が得られる。次に電
源VSSが電源VEEよりも高くなると、トランジスタMP1の
ゲート電圧も高くなり、内部回路１への供給が停止し、
前記第１の実施例と同様に、寄生素子への供給がなくな
る為、ラッチアップすることなく、素子破壊が起きな
い。(The first embodiment is for an N-type substrate.) As shown in FIG. 2, the second embodiment employs a P-type M
The drain of the OS transistor MP1 is connected, and the internal circuit 1
The source is connected to the power supply line, and the power supply VSS is connected to the gate. By setting the conduction resistance of the P-type MOS transistor MP1 small, the power supply VSS
Internal circuit 1 time, from the power source VEE through the transistor MP1 which is more than the threshold value V TP of the transistor MP1 low
, So that the same characteristics as those of the related art can be obtained. Next, when the power supply VSS becomes higher than the power supply VEE, the gate voltage of the transistor MP1 also increases, and supply to the internal circuit 1 is stopped.
As in the case of the first embodiment, supply to the parasitic element is eliminated, so that no latch-up occurs and no element destruction occurs.
第１図，第２図は共にMOSトランジスタのゲートを直
接電源に接続した実施例であるがMOSトランジスタのゲ
ートと電源の間に抵抗を介しても同様な効果が得られる
ことは明らかである。FIGS. 1 and 2 both show an embodiment in which the gate of the MOS transistor is directly connected to the power supply, but it is apparent that the same effect can be obtained even if a resistor is provided between the gate of the MOS transistor and the power supply.
第３図は本発明の第３の実施例の回路図である。第３
図は電源VDD−VSSに抵抗40,41,42の直列体からなる基準
電圧発生回路を構成し、その基準電圧にＮ型MOSトラン
ジスタMN1のゲートを接続した場合である。FIG. 3 is a circuit diagram of a third embodiment of the present invention. Third
The figure shows a case where a reference voltage generating circuit composed of a series body of resistors 40, 41, and 42 is configured to the power supply VDD-VSS, and the gate of the N-type MOS transistor MN1 is connected to the reference voltage.
第３図において、電源VC1と内部回路１との間にトラ
ンジスタMN1,電源VC2と内部回路１との間にトランジス
タMN2がそれぞれ接続される。In FIG. 3, a transistor MN1 is connected between the power supply VC1 and the internal circuit 1, and a transistor MN2 is connected between the power supply VC2 and the internal circuit 1.
第３図では、基準電圧発生回路に抵抗分割比を利用し
ているが、抵抗のかわりに、ダイオードのVFやMOSトラ
ンジスタの能力比を利用した場合でも、電源VCC,VDDが
定常状態の時、本実施例の電源間に接続されたMOSトラ
ンジスタを導通できるように電位を設定することによ
り、同様な効果が得られ、電源投入順序等によって起き
ていたラッチアップ現象によるボンディングワイヤ切れ
や素子破壊等が起きないことは明らかである。In Figure 3, but utilizes a resistance division ratio to the reference voltage generating circuit, instead of the resistor, even when using the capacity ratio of V F and MOS transistor diode, when the power source VCC, VDD is the steady state The same effect can be obtained by setting the potential so that the MOS transistor connected between the power supplies of the present embodiment can be made conductive, and the bonding wire breakage or element destruction due to the latch-up phenomenon caused by the power-on sequence or the like. Obviously, no such thing will happen.
尚、電源VCC,VC1,VC2,VEEの電位は、電源VSSよりも高
く、電源VDDよりも低い電位となっている。Note that the potentials of the power supplies VCC, VC1, VC2, and VEE are higher than the power supply VSS and lower than the power supply VDD.
以上説明したように、本発明は、電源と内部回路の電
源供給ラインとの間に、トランジスタを挿入することに
より、基板電位が他の電源電位より低い時にはMOSトラ
ンジスタがオフし、寄生素子による経路も例えば第６図
のようになくなる為、電源投入順序等によって起きてい
たラッチアップ現象による素子破壊がなくなり、また電
源投入順序等を調整するタイミング回路を用意する必要
もなくなるという効果がある。As described above, according to the present invention, by inserting a transistor between a power supply and a power supply line of an internal circuit, the MOS transistor is turned off when the substrate potential is lower than another power supply potential, and 6, for example, there is an effect that the element destruction due to the latch-up phenomenon caused by the power-on sequence and the like is eliminated, and it is not necessary to prepare a timing circuit for adjusting the power-on sequence and the like.
第１図は本発明の第１の実施例の半導体集積回路を示す
回路図、第２図は本発明の第２の実施例を示す回路図、
第３図は本発明の第３の実施例を示す回路図、第４図は
第１図の内部回路の回路図、第５図は第４図に示した回
路を半導体基板に形成した状態を示す断面図、第６図は
第５図で寄生的に存在する素子で構成した等価回路図、
第７図は従来の半導体集積回路装置の回路図、第８図は
従来例の内部回路の回路図、第９図は第８図に示した回
路を半導体基板に形成した状態を示す断面図、第10図は
第９図で寄生的に存在する素子で構成した等価回路図で
ある。 １……内部回路、２……電源供給ライン、10,20……基
板、11,21,22……Ｐウェル領域、12,15,17,18,23,26,2
8,29,31,34……P+領域、13,14,16,19,24,25,27,30,32,3
3……N+領域、40,41,42……抵抗、MN1,MN2……Ｎ型MOS
トランジスタ、MP1……Ｐ型MOSトランジスタ、Tr1……
寄生PNP型バイポーラトランジスタ、Tr2……寄生NPN型
バイポーラトランジスタ、R1,R2……寄生抵抗、VDD……
最高電位（Ｎ型基板の場合は基板電位）電源、VSS……
最低電位（Ｐ型基板の場合は基板電位）電源、VCC,VC1,
VC2,VEE……電位（通常）電源、A,a,b,X,Y……節点。FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a second embodiment of the present invention,
FIG. 3 is a circuit diagram showing a third embodiment of the present invention, FIG. 4 is a circuit diagram of an internal circuit of FIG. 1, and FIG. 5 shows a state in which the circuit shown in FIG. 4 is formed on a semiconductor substrate. FIG. 6 is an equivalent circuit diagram composed of parasitic elements in FIG. 5,
7 is a circuit diagram of a conventional semiconductor integrated circuit device, FIG. 8 is a circuit diagram of an internal circuit of a conventional example, FIG. 9 is a cross-sectional view showing a state where the circuit shown in FIG. 8 is formed on a semiconductor substrate, FIG. 10 is an equivalent circuit diagram of FIG. 9 constituted by parasitic elements. 1 ... internal circuit, 2 ... power supply line, 10,20 ... substrate, 11,21,22 ... p-well region, 12,15,17,18,23,26,2
8,29,31,34 …… P + area, 13,14,16,19,24,25,27,30,32,3
3 ... N + region, 40,41,42 ... Resistance, MN1, MN2 ... N-type MOS
Transistor, MP1… P-type MOS transistor, Tr 1 ……
Parasitic PNP bipolar transistor, Tr 2 … Parasitic NPN bipolar transistor, R1, R2… Parasitic resistance, VDD…
Maximum potential (substrate potential for N-type substrate) power supply, VSS ...
Minimum potential (substrate potential for P-type substrate) power supply, VCC, VC1,
VC2, VEE: Potential (normal) power supply, A, a, b, X, Y ... Nodes.
Claims (1)
電源ラインと、前記第1,第2,第３の電源ラインにそれぞ
れ電源を供給する第1,第2,第３の電源端子を備え、前記
第１及び前記第２の電源端子に同一極性で異なる電圧を
印加し、前記第３の電源端子に前記第１の電源端子に印
加される電圧と逆極性の電圧を印加する半導体集積回路
において、前記第１の電源端子と前記第１の電源ライン
との間に電界効果トランジスタのソース・ドレインを挿
入し、前記トランジスタのゲートを前記第２の電源端子
に接続したことを特徴とする半導体集積回路。1. A first, second, and third power supply line for supplying power to an internal circuit, and first, second, and third power supplies for supplying power to the first, second, and third power supply lines, respectively. And a third power supply terminal, wherein different voltages having the same polarity are applied to the first and second power supply terminals, and a voltage having a polarity opposite to the voltage applied to the first power supply terminal is applied to the third power supply terminal. In the semiconductor integrated circuit, the source / drain of a field effect transistor is inserted between the first power supply terminal and the first power supply line, and the gate of the transistor is connected to the second power supply terminal. A semiconductor integrated circuit characterized by the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2272760A JP2613967B2 (en) | 1990-10-11 | 1990-10-11 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2272760A JP2613967B2 (en) | 1990-10-11 | 1990-10-11 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04147666A JPH04147666A (en) | 1992-05-21 |
| JP2613967B2 true JP2613967B2 (en) | 1997-05-28 |
Family
ID=17518367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2272760A Expired - Fee Related JP2613967B2 (en) | 1990-10-11 | 1990-10-11 | Semiconductor integrated circuit |
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| Country | Link |
|---|---|
| JP (1) | JP2613967B2 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2907082B2 (en) * | 1995-10-23 | 1999-06-21 | 日本電気株式会社 | CMOS integrated circuit |
| JP2006269902A (en) * | 2005-03-25 | 2006-10-05 | Oki Electric Ind Co Ltd | Semiconductor integrated circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS574427Y2 (en) * | 1978-01-19 | 1982-01-27 | ||
| JPH01109818A (en) * | 1987-10-22 | 1989-04-26 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
-
1990
- 1990-10-11 JP JP2272760A patent/JP2613967B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04147666A (en) | 1992-05-21 |
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