JP2608648B2 - Image projection device and image projection method for projection display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image projection device and an image projection method for a projection display device, and more particularly to an image projection device for a projection type display device capable of projecting a large color image by a single monochromatic projection tube. The present invention relates to an apparatus and a video projection method.

[0002]

2. Description of the Related Art Generally used direct-view display devices such as CRTs are gradually becoming larger.
With the increase in size, the volume and weight of the tube have rapidly increased, and it is now almost impossible to manufacture a large CRT of 45 inches or more.

[0003] Accordingly, a projection type display device has been developed which projects an image displayed on a CRT or the like on a large screen so that the image can be viewed from a distant place.

[0004] The simplest projection type display device has a configuration in which an image displayed on a color picture tube is projected on a screen through an optical system. Not suitable for the formation of

In such a situation, the one mainly used in the conventional projection display apparatus is shown in FIG.
, Red (R), green (G), blue (B)
Three monochromatic picture tubes or projection tubes 352, 353, 35
4, a red, green, and blue single-color image is displayed, and is projected on a screen 351 through a focusing lens 357 to form a color image.

However, in this conventional example, three independent projection tubes must be provided, and the size of the projection device is increased, the price is increased, and it is difficult to adjust the convergence.

As another example of the projection type display device, as shown in FIG. 11, three liquid crystal display devices LC of red, green and blue for displaying monochromatic images of red, green and blue, respectively.
A liquid crystal light valve type image projection device using D1, LCD2, and LCD3 has also been proposed. In this apparatus, white light generated from the light source LAMP mirror M1,
The light is split into monochromatic lights of red, green and blue through M2 and spectral mirrors DM1, DM2 and DM3, and the respective liquid crystal display devices LCD1, LCD2 and LCD3 are scanned with driving light to form respective monochromatic images. Is projected onto a screen through the mirror M3, the spectral mirrors DM3 and DM4, and the lens LE to form a color image. In the figure, reference numeral FIL denotes a filter, and C1, C2, and C3 denote focusing lenses of a driving tube.

[0008]

In such a configuration, a projected image is formed on each liquid crystal display device, and the resolution thereof depends on the number of pixels of the liquid crystal display device. However, at present, there is a limit in increasing the number of pixels of the liquid crystal display device, so that this device is still unsuitable for high resolution.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an image projection apparatus and a projection type display apparatus capable of economically displaying a high-resolution large-color image using only one single-color projection tube. It is intended to provide a video projection method.

[0010]

To SUMMARY OF THE INVENTION To achieve the above object, a video projection device of the projection type display device of the present invention according to claim 1, in the video projector of the projection type display device, red, green A / D converters for inputting blue video signals and converting them into digital signals in accordance with a predetermined sampling frequency signal, and three memories for writing and reading the respective red, green and blue digital signals When a counter for outputting count by receiving a predetermined control signal, and a D flip-flop for providing the control signal as a clear signal of said counter by latching the output of said counter receives a clock signal, the output of the counter Switches according to the state, and switches among the three memories.
And the read control clock and sampling frequency
And the memory and the D / A converter.
A switch for connecting, to the switching of the switch
Red Accordingly read from the memory, green, by a predetermined sampling frequency signal a digital signal of blue, and speed unit having respective red, green, and a D / A converter that converts an analog signal of blue, A write / read control clock signal used for converting the red, green, and blue video signals in the double speed unit, a phase locked loop unit that supplies a sampling frequency signal and a control signal,
A sync separation / deflection unit for separating and generating a synchronization signal for vertical and horizontal deflection from green and blue video signals, and an output of the double speed unit according to the sync signal of the sync separation / deflection unit for red, green, and blue. separating each red, green, and blue monochromatic component optical signal from the optical signals converted by the conversion means and the conversion means and a picture tube for displaying an optical signal corresponding to
Separating means having a spectral mirror and an electronic liquid crystal shutter ;
The separated red, green, and a focusing means for focusing the light component signals of blue, the write / read control clock signal and the sampling frequency signal is supplied to the speed portion from said phase locked loop section, the red , green, and write control clock signal and the sampling frequency signal for converting the video signal of blue in the a / D converter is written into the memory, the control to read out the digital signal written in the memory D / a The converter has a read control clock signal and a sampling frequency signal for conversion into an analog signal. At this time, the read control clock signal and the sampling frequency signal have the same frequency as the write control clock signal and the sampling frequency signal.
Formed to be three times the frequency, the control signal supplied to the speed unit from said phase locked loop section, the counter output by one frame for each horizontal synchronizing frequency period of 175 times is supplied to the counter It is characterized in that it is formed so as to sequentially select red, green and blue video signal data.

According to a second aspect of the present invention, there is provided a video projection method for a projection type display device, wherein a red, green, and blue color video signal is converted into a serial color video signal tripled in speed, and
Green, the scanning section 175 times the horizontal synchronization frequency periodic color video signal in units of one frame of the blue, and the image signal speed process of have a process of superimposing scanned respectively by 525 lines,
The serial color video signal is passed through a single color picture tube to red, green,
A conversion process of converting into a light signal having a wavelength of light corresponding to blue, a separation process of respectively separating monochromatic component light signals of red, green, and blue from the converted light signal, and the separated red, And a focusing step of focusing green and blue component light signals.

According to a third aspect of the present invention, there is provided the image projection method for a projection type display apparatus, wherein the red color includes a synchronization signal.
The green and blue color video signals are converted from the horizontal synchronizing signal to a triple speed according to a predetermined control signal generated by the PLL method and serially output, and at this time , the red, green and blue color video signals are converted. 175 times the horizontal synchronization frequency per frame
In the period of the scanning section, separating the 3-speed conversion step of respectively superposed scanned one 525 lines, the 3-speed conversion stage 3-speed red output from, green, from the color image signal of blue, vertical and horizontal synchronizing signals Synchronizing signal separating step;
A display step of serially inputting red, green, and blue color video signals tripled from the double-speed conversion step, and polarizing the display with a vertical / horizontal synchronization signal output in the synchronization signal separation step to display a single color; A separation / reflection step of selectively separating and reflecting red, green, and blue component light signals according to the wavelength of light from the monochromatic light signal displayed in the display step, and a predetermined level supplied from the triple speed conversion step. In response to the control signal of, the red, green, blue component light signals separated from the separation and reflection stage are sequentially passed,
A selecting step of selecting red, green, and blue component light signals; and a combining and projecting step of combining the red, green, and blue component light signals selected from the selecting step and enlarging and projecting the screen on a screen by adjusting a focusing magnification. And characterized in that:

[0013]

According to the first aspect of the present invention, one monochromatic projection is performed by operating the image projection apparatus of the projection type display apparatus according to the second and third aspects of the invention. A high-resolution large color image can be displayed using the tube.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a video projection apparatus and a video projection method for a projection type display apparatus according to the present invention will be described in detail with reference to FIGS.

Before describing a preferred embodiment of a video projection apparatus and a video projection method for a projection display apparatus according to the present invention, the present invention will be described with reference to the accompanying drawings for understanding the present invention. Japanese Patent Application No. 2-40 by the present applicant
The contents described in 1996 are explained.

FIG. 1 is a diagram illustrating the configuration of an image projection apparatus according to the present invention.

In FIG. 1 , the triple speed circuit 100 has R,
The R, G, B video signals input to the G, B input terminals R, G, B are output in series at a triple speed. The PLL circuit 200
Horizontal synchronization end Hs output from a synchronization detection circuit (not shown)
In response to the horizontal sync signal of “sync”, a PLL (Phase
3x speed circuit 10 by Locked Loop method
0 of R, G, control signals for triple speed the B video signal, etc.
The occur. The picture tube 300 outputs R, which is output from the triple speed circuit 100 through a line 170 and tripled in speed,
Upon receiving the G and B analog signals, they are scanned at a triple speed and displayed as a monochrome image. Synchronous separation and polarization circuit 400
Is 3 times faster had you in 3-speed circuit 100 line 170
That comprise a composite sync signal outputted through R, G,
Separating the B video signals or al synchronization signals, the picture tube 300 3
A vertical / horizontal synchronization signal for vertical / horizontal deflection for scanning a video signal at double speed is generated.

First to third electronic liquid crystal shutters 80, 90,
Reference numeral 110 denotes an R, G, B single color component by an electrical control signal.
This is for selectively transmitting a spectral signal. Sha
The driver driving circuit 500 uses the line 18 in the triple speed circuit 100.
R, G, B video signal output through 0TooutputDoWas
Decoding the switching signal for
1 to 3 electronic liquid crystal shutters 80, 90, 110Stay
Drive signals for sequentially passing R, G, and B component optical signals
Issue a signal.

The first spectral mirror 40 is provided with the image tube 30 described above.
0, the red component light is totally reflected at 90 ° and the blue and green component lights are transmitted according to the wavelength of the light, and the second spectral mirror 50 is connected to the first spectral mirror 40. Of the blue and green component lights transmitted through, the green component light is totally reflected at 90 ° depending on the wavelength of the light,
The blue component light is transmitted.

The first and second mirrors 10 and 20 are provided with the first and second mirrors 10 and 20, respectively.
The red and green component lights totally reflected by the two spectral mirrors 40 and 50 are respectively totally reflected at 90 ° horizontally, and the third mirror 30
Reflects the red component light reflected by the first mirror 10 output through the first electronic liquid crystal shutter 80 by the output of the shutter drive circuit 500 at 90 °.

The third spectral mirror 60 reflects the green component light totally reflected by the second mirror 20 through the second electronic liquid crystal shutter 90 at 90 ° in accordance with the output of the shutter drive circuit 500 and the wavelength of the light. , Third mirror 30
Transmits the red component light totally reflected.

The fourth spectral mirror 70 transmits the blue component light of the second spectral mirror 50 output through the third electronic liquid crystal shutter 110 according to the output of the shutter drive circuit 500 and the wavelength of the light. Total reflection at 90 °.

The lens 600 focuses the output of the fourth spectral mirror 70 and projects it on a large color screen by adjusting the magnification.

A method of projecting an image as an apparatus according to the invention of the present application having such a configuration is as follows.

First, in the video projection method performed by the configuration as shown in FIG. 1, R, G, B including a synchronization signal are included.
A video signal is converted from a horizontal signal to a triple speed by a predetermined control signal generated by a PLL system and output in series.
A double speed conversion stage is performed.

A synchronization separation step for separating the vertical and horizontal synchronization signals from the triple speed R, G, B video signals output from the triple speed conversion stage is performed.
A display step is performed in which the double-speed R, G, and B video signals are serially input, deflected by the vertical / horizontal synchronization signal output in the synchronization separation step, and displayed in a single color.

Next, a separation / reflection step of selectively separating and reflecting R, G, and B monochromatic component light signals according to the wavelength of light from the monochromatic light signal displayed in the display step is performed. R tripled in the double speed conversion stage,
The R, G, and B component optical signals separated from the separation / reflection stage are sequentially passed by a switch signal for outputting the G and B video signals , and the R, G, and B component optical signals are selected. A selection step is performed.

R, G, finally passed from the selection stage
A focusing and projecting step of synthesizing the B component light signals and projecting them on a screen by adjusting the focusing magnification is performed.

FIG. 2 is a detailed circuit diagram of the triple speed circuit 100 and the shutter drive circuit 500 of FIG.
Is formed as follows.

The first to third A / D converters 121 to 123 are:
R, G, B input terminals R, G, analog red input through B, green, a video signal of blue, the aforementioned PLL circuit 200
Converted into a digital signal by 8MHz sampling signal input is output to the write control clock and sampling frequency end 202 from.

The first to third memories 141 to 143 include the first to third memories 141 to 143, respectively.
The digital signal output from the 3A / D converters 121 to 123 is converted into a write control clock and a sampling frequency terminal 2 receiving the signal output from the PLL circuit 200.
02 is sequentially written by the address signal counted according to the input clock signal of No. 02, and a signal which is three times the write control clock signal and the sampling frequency signal output from the PLL circuit 200 is read out. Digital data written by address signal counted by receiving input
Read the signal .

That is, the R, G, and B signals are sequentially recorded in the first to third memories 141 to 143 in accordance with the sampling signal of 8 MHz for each horizontal synchronization signal section during recording. 24 MHz for each horizontal synchronization signal section
R, G, and B signals are simultaneously reproduced from the first to third memories 141 to 143 in accordance with the sampling signals of At this time, the memories used are the first to third A / D converters 121 to 12.
3 comprises a line memory having a sufficient capacity to record and store digital signal data.

The counter 144 receives and counts the control signal of the control signal terminal 201 which receives the signal output from the PLL circuit 200. The D flip-flop 145 receives the input of the control signal terminal 201 as a clock signal, and
The output of 44 is latched and a clear signal is provided to this counter 144.

The switch 150 is switched according to the state of the output terminals Qa and Qb of the counter 144, and switches the read control clock and the sampling frequency terminal 203.
24 MHz clock of the first to third memories 141 to 14
A third read clock terminal RDCK controls the outputs of the first to third memories 141 to 143.

The D / A converter 160 outputs the data from the first to third memories 141 to 143 according to the read control clock and the sampling signal at the sampling frequency terminal 203.
The converted digital signal is converted into an analog signal.

The output terminals Qa, Qb of the counter 144
Are the AND gates 5 of the shutter drive circuit 500, respectively.
01, 502 and the input terminal of the NOR gate 503, the output terminal 504 of one AND gate 501 is connected to the first electronic liquid crystal shutter 80 for transmitting red light, and the output terminal 505 of the other AND gate 502 transmits green light. The second electronic liquid crystal shutter 90, and the NOR gate 503
Is connected to the third electronic liquid crystal shutter 110 for passing blue light.

FIG. 3 schematically shows an example of the configuration of a PLL circuit 200 applied to the apparatus of FIG. 1 as described in Japanese Patent Application No. 2-401996 filed earlier than the present invention. FIG. 3 is a configuration block diagram.

According to FIG. 3, the phase comparator 204 comprises a horizontal synchronizing signal at the horizontal synchronizing signal end Hsync and the first frequency divider 207.
And outputs a difference by comparing the phase with the signal that is fed back via the. A low-pass filter (LPF) 205 performs low-pass filtering on the output of the phase comparator 204 and converts the output to a DC voltage level. A voltage controlled oscillator (VCO) 206 generates a 24 MHz transmission frequency according to the output level of the low-pass filter 205.

The first frequency divider 207 is connected to the voltage controlled oscillator 20
6 output (24 MHz) to a predetermined value (24 MHz / fh)
[24MHz ÷ (24MHz / fh)]
Then, the pulse width, that is, the phase is different from that of the horizontal synchronization signal Hsync, and the signal fh having the same frequency and cycle as the horizontal synchronization signal is generated and output to the phase comparator 204.

The AND gate 208 reads the output of the above-described voltage controlled oscillator 206 which is generated by a signal having a stable 24 MHz frequency when the applied voltage of the power supply terminal Vcc connected to one end of the resistor R is in the "high" state. The control clock and the sampling frequency terminal 203 are supplied.

The second frequency divider 209 includes an AND gate 208
Divides the 24 MHz signal output from the write control clock and the sampling frequency terminal 202 by 8 MHz.
Supply the z signal. The third frequency divider 210 is the second frequency divider 2
09 is divided by a predetermined value (8 MHz / 8fh) [8 MHz ÷ (8 MHz / 3fh)], and a frequency 3fh corresponding to three times the frequency of the horizontal synchronization signal is applied to the control signal terminal 201 of the triple speed circuit 100. input.

As described above, Japanese Patent Application No. 2-401996 filed by the present applicant is disclosed.
Hereinafter, preferred embodiments of the video projection apparatus and the video projection method according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a block diagram schematically showing another embodiment of the PLL circuit 200 of FIG.

The PLL circuit 200 shown in FIG.
2 is almost similar to the configuration of the PLL circuit 200 shown in FIG. 2, and a detailed description of the configuration is omitted. However, the configuration for generating the input signal 201 input to the clock terminal CLK of the counter 144 in FIG.

In FIG. 3, the write control clock signal and the sampling frequency signal 202 are frequency-divided via the third frequency divider 210 to generate the control signal 201, and 3fh, which is three times the horizontal synchronization frequency. In FIG. 4, the counter 211 receives the horizontal synchronization signal Hsync and outputs a pulse every 175H section.
The control signal 201 input to the counter 144 in FIG. 2 is a pulse signal having a period of 175H. Here, “H” is the horizontal synchronizing signal frequency fh = 1.
It is about 63.5 μs as the inverse of 5.374 KHz.

FIGS. 5A to 5D are operation waveform diagrams of triple speed conversion of the triple speed circuit 100 of FIGS. 1 and 2 according to the present invention.
5A to 5C are first to third A / D converters 121 to 121 in FIG.
R, G, B analog signals input to 123 are written
Input to control clock and sampling frequency end 202
8MHz sampling signal
Converted into signals and stored in the first to third memories 141 to 143
FIG. 5D shows a data waveform diagram of a digital signal to be read , and FIG.
FIG. 3 is a data waveform diagram read from the first to third memories 141 to 143 in FIG. 2 by a 24 MHz clock signal input to a number terminal 203.

6A to 6G are waveform diagrams for explaining the operation of the shutter drive circuit of FIG. 2 based on the output of the PLL circuit shown in FIG. 3, and FIG. 6A shows the PLL circuit of FIG. 6B is an input waveform diagram of the horizontal synchronization end Hsync. FIG. 6B is an output waveform diagram of the third frequency divider 210, and FIG.
FIG. 3 is a waveform diagram illustrating outputs Qa and Qb of the counter 144 in FIG. 2, respectively.

FIGS. 6E to 6G show the triple speed circuit 100 shown in FIG.
The result counted by the counter 144 by the clock signal similar to B of FIG. 6 inputted to the control signal terminal 201 of FIG. 6 is inputted to the AND gates 501 and 502 and the NOR gate 503 and outputted by the logical value thereof. FIG. 3 is a waveform diagram of driving signals for driving the first to third electronic liquid crystal shutters 80, 90, and 110.

7A to 7G are waveform diagrams for explaining the operation of the shutter drive circuit of FIG. 2 in accordance with the output of the PLL circuit shown in FIG. 4, and FIG. 7A shows the PLL of FIG. 7B is an input waveform diagram of the horizontal synchronization end Hsync of the circuit, FIG. 7B is an output waveform diagram of the counter 211, and FIG. 7C and D are waveform diagrams respectively showing the outputs Qa and Qb of the counter 144 of FIG. is there. 7 are the triple speed circuit 100 of FIG.
The result counted by the counter 144 in response to the clock signal equal to B in FIG. 7 inputted to the control signal terminal 201 of FIG. FIG. 7 is a waveform diagram of a drive signal for driving the first to third electronic liquid crystal shutters 80, 90, 110 of FIG.

FIGS. 8A to 8D are operation diagrams exemplifying triple speed scanning in the picture tube 300 of FIG. 1 according to the output of the PLL circuit shown in FIG. 3, and are shown in FIGS. 8A to 8C. This is an example in which such an existing R, G, B video signal is scanned at 3 times speed as shown in FIG. 8D.

FIGS. 9A to 9D are explanatory diagrams exemplifying triple-speed scanning in the picture tube 300 of FIG. 1 according to the output of the PLL circuit shown in FIG. This is an example in which R, G, and B frame data are scanned on one screen for each frame (525 lines) of the existing R, G, and B video signals as shown.

That is, during the 175H section, the R frame data is scanned over 525 lines of one screen, and the next 17 frames are scanned.
During the 5H section, the G frame data is scanned over 525 lines of the screen, and during the next 175H section, the B frame data is scanned over 525 lines of the screen.

Hereinafter, the specific operation of the preferred embodiment of the apparatus of the present invention will be described in detail after describing the operation of Japanese Patent Application No. 2-401996 of the present applicant with reference to the attached drawings. I do.

According to FIG. 1, the R, G, B input terminals R, G,
Red, green, and blue analog video signals are supplied to B at a triple speed circuit 100
1 and output from a not-shown sync separation circuit, the horizontal sync signal H of the PLL circuit 200 shown in FIG.
A signal having a waveform as shown in FIG. 6A is input to sync.

The PLL circuit 200 configured as shown in FIG.
The phase comparator 204 compares the phase of the frequency fh signal, which is the same as the frequency of the horizontal synchronizing signal fed back from the first frequency divider 207, with the input signal of the horizontal synchronizing end Hsync. The comparison difference value generated from the phase comparator 204 is low-pass filtered by the low-pass filter 205 to be DC.

D output from the low-pass filter 205
The transmission frequency of the voltage controlled oscillator 206 is determined by the C voltage level, and locking is performed so as to oscillate at a frequency of 24 MHz. The output of the voltage controlled oscillator 206 is frequency-divided by the first frequency divider 207 by a predetermined value (24 MHz / fh).
MHz ÷ (24 MHz / fh)] to generate a signal fh having a frequency corresponding to the horizontal frequency. As described above, this signal is compared with the phase of the horizontal synchronization signal by the phase comparator 204 to detect a phase difference value. This phase difference value is intermittently fed back and locked so that a desired stable 24 MHz frequency is always output.

The output frequency of 24 MHz of the voltage controlled oscillator 206 is input to one end of the AND gate 208, and the applied voltage at the voltage terminal Vcc through the resistor R connected to the other end of the AND gate 208 is in the "high" state. In the case of, a 24 MHz signal is output from the output terminal of the AND gate 208. This 24 MHz signal is input to the read control clock and sampling frequency terminal 203 of the triple speed circuit 100.

On the other hand, this 24 MHz signal is divided into a second frequency divider 2
If the frequency is divided by three at 09, the signal becomes an 8 MHz signal and is input to the write control clock and sampling frequency terminal 202 of the triple speed circuit 100. This 8 MHz signal is frequency-divided by the third frequency divider 210 at a predetermined value (8 MHz / 3fh) [8
MHz ÷ (8 MHz / 3fh)] and the horizontal frequency (f
A signal 3fh having a frequency three times that of h) is generated as shown in FIG. 6B and input to the control signal terminal 201 of the triple speed circuit 100.

Accordingly, the first to third A /
The red, green, and blue analog video signals are input to the red, green, and blue ends R, G, and B by the D converters 121 to 123 according to the write control clock and the sampling frequency input to the sampling frequency end 202. Ie 8M
The signal is converted into a digital signal as shown in FIGS . In the first to third memories 141 to 143, when the write control clock and the output signal of the sampling frequency terminal 202 are input to the write clock terminal WRCK, they are counted inside the memory to generate an address signal. By this address signal, the first to third memories 141 to 141
143, the first to third A / D converters 12
Digital signals output from 1 to 123 are sequentially written.

[0060] Then, count to output Qa signals 3fh striking to three times the horizontal synchronizing signal frequency which is illustrated in Figure 5 which is input to the control clock terminal 201 in the counter 144, Q
b. On the other hand, when the output state is generated in three states and the switch 150 is sequentially switched,
Read control clock and sampling frequency end 20
24 are input to the first to third memories 1.
The data is input to the read clock terminals RDCK of 41 to 143 and is counted inside the memory to generate a read address signal. Data corresponding to the read memory area is read by this address signal. At the time of reading, since the signal is read at a frequency of 24 MHz, which is three times faster than the 8 MHz signal at the time of writing, a signal as shown in FIG. 6D can be output.

The R, G, B digital data as shown in FIG. 5D passing through the switch 150 is converted into an analog signal by the read control clock and the 24 MHz frequency of the sampling frequency terminal 203 by the D / A converter 160. Output after conversion.

The triple-speed R, G, B analog signal output from the D / A converter 160 is input to the electron gun of the monochrome image tube 300. Then, the composite synchronizing signal included in the R, G, and B video signals output from the D / A converter 160 is separated into vertical and horizontal synchronizing signals by a synchronizing separation / deflection circuit 400. if control for scanning during the vertical and horizontal deflection at triple speed to 300, the high brightness or low brightness, as D in the color video signal as shown in D of FIG. 5 in FIG. 8, for example, black or white Is displayed in the state of.

On the other hand, the counter 144 of the triple speed circuit 100
Is latched by a D flip-flop 145, and the counter 144 is alternately cleared each time the signal is low, and the outputs of the output terminals Qa and Qb of the counter 144 are AND gated in the shutter drive circuit 500. 501, 50
2 and NOR gate 503.

When the states of the output terminals Qa and Qb of the counter 144 are all “low”, the output of the NOR gate 503 is “high”, and the states of the output terminals Qa and Qb of the counter 144 are “high” and “low”, respectively. ", The output of the AND gate 501 is" high ", and when the states of the output terminals Qa, Qb of the counter 144 are" low "and" high ", respectively, the output of the AND gate 502 is" high ". That is, when the output of the AND gate 501 is “high”,
The first electronic liquid crystal shutter 80 of FIG. 1 is turned on with a signal as shown in FIG. 6E, and when the output of the AND gate 502 is "high", the first electronic liquid crystal shutter 80 with a signal as shown in FIG. The two-electron liquid crystal shutter 90 is turned on, and the NOR gate 503 is turned on.
Is high, the third electronic liquid crystal shutter 110 is turned on by a signal as shown in FIG. 6G and driven sequentially. At this time, waveforms such as E to G in FIG. 6 generated by counting by the counter 144 to which the signal as B in FIG. 6 is input are signals synchronized with the R, G, and B color video signals. .

When the R, G, and B color video signals are compressed and scanned in H / 3 increments as shown in FIG.
00 is displayed as a high-low luminance video signal, for example, a black-and-white video signal. Since light has an intrinsic wavelength depending on the color, only the red component light is reflected by the first spectral mirror 40 depending on the wavelength, and the blue and green component lights are reflected. Let through. This is a basic characteristic of the spectral mirror. Then, the first spectral mirror 40
The red component light incident at an angle of 90 ° is reflected by the first mirror 10 at an angle of 90 °. On the other hand, the blue and green component lights transmitted through the first spectral mirror 40 reflect the green component light at 90 ° in the second spectral mirror 50 according to the wavelength of the light, the blue component light is transmitted, and the green component light is again transmitted. The light is totally reflected at 90 ° by the second mirror 20.

At this time, the output of the AND gate 501 of the shutter drive circuit 500 drives the first electronic liquid crystal shutter 80 to pass the red component light reflected from the first mirror 10, and the output of the AND gate 502 changes to the The two-electron liquid crystal shutter 90 is driven to pass the green component light reflected from the second mirror 20. Then, the output of the NOR gate 503 drives the third electronic liquid crystal shutter 110 to pass the blue component light transmitted through the second spectral mirror 50.

The red component light that has passed through the first electronic liquid crystal shutter 80 is totally reflected at 90 ° by the third mirror 30,
The green component light that has passed through the spectral mirror 60 and passed through the second electronic liquid crystal shutter 90 is reflected at 90 ° by the third spectral mirror 60 and is incident on the fourth spectral mirror 70. And
The fourth component mirror 70 transmits the blue component light that has passed through the third electronic liquid crystal shutter 110 according to the wavelength of the light, and reflects the red component light that has been reflected and transmitted by the third component mirror 60. The red, green, and blue component lights are focused by the lens 600 to project a color image on a screen. At this time, the color image that has passed through the fourth spectral mirror 70 can be enlarged to a desired magnification depending on the magnification of the lens 600.

As described above, in the triple speed circuit 100, when the R, G, B signals are supplied to the picture tube 300 at triple speed, the R, G, B
The first to third memories 141 to 14 store the signal data for each line.
3, i.e. the control signal supplied by the PLL circuit 200 into three line memories, i.e., to record in response to the control signal 201 and the write and read control clock signal 202 and 203, or is read out. At this time, at the time of reading, the R, G, and B signals are output at triple speed by using the read control signal 203 having a frequency three times as high as that of the recording and the control signal 201 of the counter 144 having a frequency three times as high as the horizontal synchronization frequency. I am trying to do it. At this time, as shown in FIGS.
By compressing and scanning the G and B signals for each H / 3 section, each of the R, G and B signals actually has a position error of about the maximum H / 3 line. The line memory used at this time only needs to have a sufficient capacity to store about H / 3 lines of signal data of R, G, and B signals.

Next, according to a preferred embodiment of the video projection apparatus of the present invention, the PLL circuit 200 of the present invention receives the horizontal synchronization frequency Hsync using the counter 211 as shown in FIG. The counter control signal 201 shown in FIG. 2 is counted and output by the counter 211 as a signal having a synchronization frequency of 175H.

At this time, one frame period, that is, 3 × 175
In the H section, the output Qa of the counter 211 is the first 175H
The high signal is output in the interval, the output Qb is output in the next 175H interval, and the outputs Qa and Qb both output the low signal in the remaining 175H interval.

At this time, the switch 150 receives the outputs Qa and Qb and outputs the output terminals 4 and 4 according to the read control clock and the sampling frequency signal 203.
′ Are connected to input terminals 1 and 1 ′ when Qa is high and Qb is low, respectively, and when Qa is low and Qb is high,
When both Qa and Qb are connected to the input terminals 2 and 2 'and are low, they are connected to the input terminals 3 and 3' to output R, G, and B frame signals for each 175H. . These R, G, and B frame signals are converted into analog signals by a D / A converter 160 in accordance with the sampling frequency signal 203, and supplied to an image tube 300 via an output line 170.

R, G, B supplied to the picture tube 300
The frame signal is 1 as shown in FIGS.
By scanning 525 lines of R, G, and B frame signals every 75H, the R, G, and B signals are superimposed on each line without any interval and displayed as shown in FIG. 9D.

As described above, in order to write / read the R, G, B frame data to / from the memory, a frame memory sufficient to store at least one frame capacity of frame data is used.

It should be noted that the present invention is not limited to the above-described embodiment, and can be changed as needed.

[0075]

The video projection apparatus and the video projection method of the projection type display apparatus according to the present invention are constructed and operated as described above. Therefore, a high-precision color image can be obtained by using a single monochromatic picture tube. Can be projected on a large screen economically.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram illustrating a configuration of a video projection device related to the present invention.

FIG. 2 is a circuit diagram schematically illustrating a triple speed circuit and a shutter driving circuit of the device illustrated in FIG. 1;

FIG. 3 is a block diagram schematically showing an embodiment of a PLL circuit of the apparatus shown in FIG. 1;

FIG. 4 is a configuration block diagram schematically showing another embodiment of a PLL circuit applied to the video projection device of the present invention.

5A to 5D are operation waveform diagrams of the triple speed circuit of FIGS. 1 and 2;

6A to 6G are waveform diagrams for explaining the operation of the shutter drive circuit of FIG. 2 in relation to the output of the PLL circuit shown in FIG. 3;

7A to 7G are waveform diagrams for explaining the operation of the shutter drive circuit of FIG. 2 in relation to the output of the PLL circuit shown in FIG. 4;

FIGS. 8A to 8D are explanatory diagrams exemplifying triple speed scanning in the picture tube of FIG. 1 by the output of the PLL circuit shown in FIG. 3;

9A to 9D are explanatory diagrams illustrating triple speed scanning in the picture tube of FIG. 3 by the output of the PLL circuit shown in FIG. 4;

FIG. 10 is a schematic configuration diagram of a conventional video projector using R, G, and B image tubes.

FIG. 11 is a schematic configuration diagram of a conventional video projection device using a liquid crystal display device.

[Explanation of symbols]

 10, 20, 30 First to third mirrors 40, 50, 60, 70 First to fourth spectral mirrors 80, 90, 110 First to third electronic liquid crystal shutters 100 Triple speed circuit 200 PLL circuit 300 Image tube 400 Synchronous separation and deflection Circuit 500 Shutter drive circuit 600 Lens

Claims (3)

(57) [Claims] 1. An image projection apparatus for a projection type display device, comprising three A / D converters for inputting red, green, and blue video signals and converting them into digital signals in accordance with a predetermined sampling frequency signal.
A D converter, three memories for writing and reading the red, green, and blue digital signals, a counter for receiving and counting a predetermined control signal, and a counter for receiving and receiving the control signal as a clock signal; A D flip-flop that latches the output of the counter and provides it as a clear signal of the counter, and switches according to the output state of the counter to connect one of the three memories to a read control clock and a sampling frequency end And a switch for connecting the memory and the D / A converter, and switching the switch to convert the red, green, and blue digital signals read from the memory into respective red, green, and blue signals by a predetermined sampling frequency signal. A double-speed unit having a D / A converter for converting the analog signal into an analog signal of A phase locked loop unit for supplying a write / read control clock signal, a sampling frequency signal, and a control signal used for conversion of green and blue video signals, and a red, green and blue video signal converted by the double speed unit. A synchronization separation and deflection unit that separates and generates a synchronization signal for vertical and horizontal deflection, and an output of the double speed unit is output with an optical signal corresponding to red, green, and blue according to the synchronization signal of the synchronization separation and deflection unit. A conversion unit having a picture tube to be displayed; a separation unit having a spectral mirror and an electronic liquid crystal shutter for respectively separating red, green, and blue single-color component light signals from the light signal converted by the conversion unit; Converging means for converging the separated red, green, and blue component light signals; and a write / read control clock signal and a sun signal supplied from the phase locked loop section to the double speed section. The pulling frequency signal includes a write control clock signal and a sampling frequency signal for converting the red, green, and blue video signals by the A / D converter and writing the converted signals to the memory, and a digital signal written to the memory. A read control clock signal and a sampling frequency signal for performing read control and converting into an analog signal by a D / A converter, wherein the frequency of the read control clock signal and the sampling frequency signal is And a control signal which is formed to be three times the frequency of the sampling frequency signal, and which is supplied from the phase locked loop unit to the double speed unit is supplied to the counter, and the output of the counter provides a 175 times horizontal synchronization frequency period. One frame of red, green, and blue video signal data is selected sequentially Video projector of the projection type display apparatus characterized by being formed as. 2. A red, green, and blue color video signal is converted into a serial color video signal tripled in speed, and the red, green, and blue color video signals are converted into 175 times the horizontal synchronizing frequency period in one frame unit. red scanning section, and the video signal speed process of have a process of each superimposed scanned one 525 lines, the serial color video signal through a single color picture tube, green,
A conversion process of converting into a light signal having a wavelength of light corresponding to blue, and a separation process of respectively separating monochromatic component light signals of red, green, and blue from the converted light signal, and the separated red, A focusing step of focusing green and blue component light signals. 3. A red, green, and blue color video signal including a synchronization signal is converted from a horizontal synchronization signal to a triple speed according to a predetermined control signal generated by a PLL system, and is output in series. In this case, the red, green, and blue color video signals are superimposed and scanned 525 lines at a time in a scanning section of a 175-times horizontal synchronization frequency in one frame unit. A synchronizing signal separating step for separating vertical and horizontal synchronizing signals from the triple-speed red, green, and blue color video signals; and a red, green, and blue color video signal tripled from the triple-speed conversion step in series. A display step of displaying a single color by polarizing according to a vertical / horizontal synchronization signal output in the synchronization signal separation step, and a monochromatic light displayed in the display step A separation / reflection step of selectively separating and reflecting red, green, and blue component light signals according to a wavelength of light from the signal; and a separation / reflection step according to a predetermined control signal supplied from the triple speed conversion step. A selection step of sequentially passing red, green, and blue component light signals separated from the reflection step and selecting red, green, and blue component light signals; and a red, green, and blue selected from the selection step. And synthesizing the component light signals and enlarging and projecting them on a screen by adjusting the convergence factor.