JP2549029B2 - Video signal display device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal display device, and more particularly to a matrix video signal display device such as a liquid crystal projector or a liquid crystal TV receiver.

[0002]

2. Description of the Related Art As a matrix type display device, there is, for example, a liquid crystal projector. As a conventional liquid crystal projector for displaying a television image signal of NTSC system (hereinafter referred to as NTSC signal), there is one shown in FIGS. The optical system is shown in FIG.
1 is a signal processing system, and FIG. 9 is a signal processing system of the main part thereof.
At 0, the time chart of FIG. 9 is shown.

First, the optical system will be described. As shown in FIG. 7, light emitted from a light source 110 such as a halogen lamp is first emitted from a blue (B) dichroic mirror 11.
2 and where the blue light is separated. The separated blue signal is reflected by the reflection mirror 114 and enters the blue liquid crystal light valve LB. A blue video signal is input to the blue liquid crystal light valve LB from a signal processing system to be described later, and the liquid crystal is driven based on the blue video signal to form a B image.

Next, the light transmitted through the blue dichroic mirror 112 is converted into green (G) dichroic mirror 116.
Incident on where the green light is separated. The separated green light enters the green liquid crystal light valve LG. Then, here, in the same manner as in the case of B described above, a G image is formed. Furthermore, the green dichroic mirror 116
The red (R) light transmitted through is reflected by the reflection mirrors 118 and 120.
Are sequentially reflected by and enter the red light valve LR. Then, an R image is formed in the same manner here.
The R, G, and B images formed as described above are combined by the color combining dichroic prism 122, and the combined color image is displayed on the screen 126 by the projection optical system 124.

Next, the signal processing system will be described. As shown in FIG. 8, the NTSC signal input to the terminal 10 is first input to the NTSC Y / C separation circuit 12 and then the luminance signal (hereinafter referred to as "Y"). Signal) and a color signal (hereinafter referred to as "C signal"). Of these,
The C signal is further decoded by the NTSC decoder 16 into color difference signals of RY and BY, and the scan converter 1 together with the Y signal.
4 is supplied. In the scan converter 14, the input Y,
Scan line interpolation is performed based on the RY and BY signals,
Non-interlaced Y, R- with twice the number of scanning lines
Y, BY signals are obtained. These non-interlaced signals are supplied to the matrix circuit 18 and converted into R, G, B video signals, and then the respective signal supply circuits 2 for the liquid crystal light valves LR, LG, LB.
4 is input.

On the other hand, the NTSC signal is the sync separation circuit 20.
Is also input to each of the horizontal and vertical synchronizing signals HD and V.
D is separated from each other. Separated horizontal and vertical sync signals H
The D and VD are input to the timing generator 22. In this timing generator 22, a read clock RCK, a write clock WCK, and a vertical scanning clock Hck are generated based on the respective synchronization signals HD and VD.
Of these, the read clock RCK is also used to fetch the R, G, B signals for one line into the signal supply circuit 24. The vertical synchronizing signal VD is also used as a signal indicating the display start of one screen. The vertical scanning clock Hck is also a signal used to perform vertical scanning in the liquid crystal light valves LR, LG, LB, and has a frequency twice that of the horizontal synchronizing signal HD.

In each of the liquid crystal light valves LR, LG, LB, the signal supply circuit 2 is read at the timing of the read clock RCK.
Each of the R, G, and B signals fetched in 4 is transferred to the horizontal line designated by the scanning circuit 26 by the input of the vertical scanning clock Hck. This operation is repeated in sequence, and the liquid crystal light valves LR, LG, LB receive R, G,
The image of B is formed. These images are further combined and projected on the screen 126.

Scan conversion is performed as shown in FIGS. 9 and 10. The video signal input to the input terminal 39 of the scan converter 14 shown in FIG. 8 is converted into a digital signal (hereinafter also referred to as a video signal) by the A / D converter 40 shown in FIG. 1 line delay circuit 130,
It is supplied to the 1-field delay circuit 132, one input terminal of the adder 134, and the motion detection circuit 140. The video signal from the A / D converter 40 is stored in the line memory 1 as shown in FIG.
Data is sequentially written as shown in FIG. The other input terminal of the adder 134 is set to 1 by the 1-line delay circuit 130.
A video signal delayed by a scanning line (hereinafter, also referred to as line) period is input, and the output is attenuated to a level of 1/2 by an attenuator 136 and supplied to one fixed terminal of the switch SW4 (FIG. 10). (I)). A video signal delayed by one field period by the one field delay circuit 132 is supplied to the other fixed terminal of SW4 (FIG. 10).
(J)). The output of the 1-field delay circuit 132 is also supplied to the motion detection circuit 140 via the 1-field delay circuit 138 to detect the motion of the video signal. Motion detection circuit 14
The switch 4 supplied with the switch switching control signal from 0 supplies the output of the attenuator 136 to the line memory 2 when the motion detection circuit 140 determines that there is motion, and when the motion detection circuit 140 determines that there is no motion. Switching is controlled so that the output of the 1-field delay circuit 132 is supplied to the line memory 2. Therefore, the line memory 2 is written as shown in FIG. 10L according to the movement of the video signal.

The frequency of the horizontal synchronizing signal HD is multiplied by (× 9
10) Write clock W generated by multiplying 910 by 32
The video signals written in the line memory 1 and the line memory 2 at the rate of CK are line memory at the rate of the read clock RCK generated by multiplying the frequency of the horizontal synchronizing signal HD by 1820 by the multiplier (× 1820) 142, respectively. 1
And line memory 2 to FIG. 10 (H) and FIG. 10 (M)
It is read as shown in. These signals are combined, and eventually the non-interlaced video signal shown in FIG.
8 and the signal supply circuit 24, the liquid crystal panels LR, LG,
Displayed in LB. As a liquid crystal projector,
For example, there is one disclosed in JP-A-62-125791.

When the number of lines of the NTSC signal is doubled and converted into a non-interlaced signal, the number of lines in one field becomes 525, and the number of lines effective for screen display is about 480. The number of display lines of the liquid crystal panel for NTSC is set to this value.
However, a PAL or SECAM video signal (hereinafter referred to as PAL signal or SECAM signal) has two lines.
When doubled and subjected to non-interlace conversion, the number of lines per field is 625, and the number of effective lines is about 575. When this signal is displayed on the liquid crystal panel for NTSC as it is, since there are only about 480 display portions, the screen is vertically extended and displayed, and the lower end portion of the screen of one field is not displayed.

Therefore, in the liquid crystal panel corresponding to the non-interlaced NTSC signal as described above, NT
When displaying a PAL signal or a SECAM signal instead of the SC signal, it is necessary to convert the system to the NTSC signal. That is, since the PAL or SECAM system differs from the NTSC signal in the field frequency and the number of scanning lines, it is generally converted into the NTSC signal by the standard system converter. This converted NTSC signal was displayed on the liquid crystal panel.

[0012]

As described above, in the prior art, a matrix type display device such as a liquid crystal projector for NTSC signals shown in FIGS. 7 to 10 is based on a different standard system, for example, a PAL signal. When displaying an image, a large-scale and complicated standard system conversion device is required, which is disadvantageous in terms of cost. Further, in the standard format conversion, there are inconveniences such as the occurrence of a jagged unnatural image pattern in the horizontal direction of the display and the thin lines extending in the horizontal direction being swung up and down.

In order to solve this problem, the present applicant has proposed a video signal display device in which the number of scanning lines of the PAL signal or SECAM signal is doubled and only the vertical scanning clock Hck is thinned out. Since the vertical scanning clock Hck interval of the thinned-out portion is twice the vertical scanning clock Hck interval of the other portion, the above-mentioned problems and flicker may occur depending on the image content of the video signal to be displayed. There was not a complete solution to the problem. The present invention has been made in view of the above point, and compresses the vertical direction of the screen with a simple and inexpensive configuration without using an expensive standard format converter even for images of different standard formats. It is an object of the present invention to provide an image display device capable of displaying natural and excellent images.

[0014]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a video signal display device for performing scanning line interpolation on an input video signal to generate and display a non-interlaced video signal. Scanning line conversion means for generating a non-interlaced video signal by time-compressing so as to reduce the number of scanning lines interpolated with respect to the number of scanning lines of the input video signal for a certain period, and the non-interlaced A video signal display device comprising a matrix display means for displaying the video signal,
Generating a non-interlaced video signal by performing scan line interpolation on the first video signal or the second video signal having more scan lines per frame than the first video signal,
An image signal display device for displaying an image based on this, comprising: input signal determination means for determining whether one of the first image signal and the second image signal has been input; and the input determination. When the means determines that the first video signal has been input, it is time-compressed and non-interlaced so that the number of interpolated scanning lines is equal to the number of scanning lines of the first video signal for a certain period. When the input determining means determines that the second video signal is input, the number of interpolation scanning lines is smaller than the number of scanning lines of the second video signal for a certain period. And a matrix display means for displaying the non-interlaced video signal. There is provided a video signal display apparatus according to.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the video signal display device of the present invention will be described below with reference to the drawings. FIG. 1 is a block system diagram of the first embodiment. In the figure, 10 is PA
Input terminal for inputting L signal, 12a is Y / C for PAL
Separation circuit, 14a is a scan converter, 16a is a PAL decoder for color signal demodulation, 18 is a matrix circuit for generating R, G, B signals, 20a is a sync separation circuit, 22
a is a timing generator, 24 is a signal supply circuit, 2
Reference numeral 6 is a scanning circuit, and LR, LG and LB are liquid crystal panels.
A signal supply circuit 24, a scanning circuit 26 and a liquid crystal panel LR,
LG and LB form the matrix display means of the present invention.

One of the PAL signals input to the input terminal 10 is separated into a luminance signal (Y signal) and a carrier color signal (C signal) by the PAL Y / C separation circuit 12a. The separated Y signal and C signal are supplied to the scan converter 14a and the PAL decoder 16a. The PAL decoder 16a decodes the C signal by a well-known technique and supplies two color difference signals (RY signal and BY signal) to the scan converter 14a. The scan converter 14a receives the input Y signal, R-
The number of lines per field is converted for each of the Y signal and the BY signal by time compression and line interpolation. In the conventional scan converter 14 shown in FIG.
The number of lines per field of the C signal was doubled for scan conversion. However, in the scan converter 14a of the present embodiment, the number of lines is 1.
Y signal with 312.5 lines per field, R-
5 Y signals and 5 Y signals per field
The scan conversion is performed so as to have 20 lines. This scan conversion is performed by the write / read control of the digital memory provided in the scan converter 14a as described later. Since the number of lines per field in the signal outputted from the scan converter 14a is close to the number of lines obtained by converting the NTSC signal into double the number of lines, the liquid crystal panels LR, LG for the NTSC signal, It becomes possible to display in LB.

On the other hand, the other of the PAL signals input to the input terminal 10 is also supplied to the sync separation circuit 20a, where the horizontal sync signal HD and the vertical sync signal VD are separated and supplied to the timing generator 22a. The timing generator 22a uses a write clock WCK, a read clock RCK, and a vertical scanning clock Hck for the digital memory.
And the vertical synchronizing signal VD are supplied to the scan converter 14a, and the vertical scanning clock Hck and the vertical synchronizing signal VD are supplied to the scanning circuit 2.
Supply to 6. The write clock WCK and the read clock RCK are generated by multiplying the frequency of the horizontal synchronizing signal HD as described later, and the vertical scanning clock Hck is generated.
Is generated by dividing the write clock WCK as described later so that its frequency becomes 5/3 times the horizontal synchronizing signal HD. Therefore, the frequency of the vertical scanning clock Hck becomes the same as the line frequency of the video signal deinterlaced by the scanning converter 14a. In the scan converter 14a, the number of lines per field of the video signal is converted based on the write clock WCK, the read clock RCK, the vertical scan clock Hck, and the vertical sync signal VD supplied from the timing generator 22a. It is displayed on the liquid crystal panels LR, LG, LB.

Next, the timing generator 22a and the scan converter 14a, which are the main parts of FIG. 1, deinterlace the input PAL signal and change the number of lines per field to 1 of the noninterlaced NTSC signal.
It works to approximate the number of lines per field. The configurations and operations of the timing generator 22a and the scan converter 14a will be described with reference to FIGS.

In FIG. 2, VD and HD are the vertical sync signal VD and the horizontal sync signal HD separated from the PAL signal by the sync separation circuit 20a shown in FIG. The input terminal 39 has the Y / C separation circuit 12 shown in FIG.
The Y signal is input from a. The horizontal synchronizing signal HD is a multiplier (× 1517) 30 and a multiplier (× 910) shown in FIG.
32, and the frequency of the horizontal synchronizing signal HD is changed to 1517
A multiplied read clock RCK and a 910 multiplied write clock WCK are generated. The read clock RCK and the write clock WCK are used for the line memory 1 and the line memory 2.
Is supplied to. Also, the write clock WCK is divided by the frequency divider 34.
By dividing by 1/546 at (1/546),
The vertical scanning clock Hck is generated. The multiplication ratio of 1517 and the division ratio of 1/546 are set values when the write clock WCK is generated by multiplying the frequency of the horizontal synchronizing signal HD by 910. 37 is each frequency dividing circuit 3
It is a pulse generator for generating pulses for resetting 4, 36 and 38 in synchronization with the vertical synchronizing signal VD.

Next, the line memory 1 and the line memory 2
Write control will be described. Sync separation circuit 20a
The horizontal synchronizing signal HD supplied from the frequency divider (1/2) 3
The frequency is divided by 8 to output a normal output and an inverted output. The normal output is the write enable pulse WE2 (FIG. 3 (D)) and the write enable terminal RE2 ′ of the line memory 2.
In addition, the inverted output is the write enable pulse WE1 (see FIG. 3).
(E)) is supplied to the write enable terminal RE1 ′ of the line memory 1. Then, the Y signal converted into a digital signal by the A / D converter 40 is written in the line memory 1 when the write enable pulse WE1 is at L level, and the write enable pulse WE2 is at L level. Sometimes written in the line memory 2.

The start control of the data write address of the line memory 1 and the line memory 2 is performed as follows. With the delay circuit 42 and the NAND circuit 44a,
The write reset pulse RR1 (FIG. 3 (P)) is generated immediately after the fall of the inverted output (FIG. 3 (E)) of the frequency divider 38, and this is the write reset terminal WR of the line memory 1.
1'is supplied. In this way, the line memory 1 can perform write control for writing the Y signal data for one line from the zero address. Similarly for the line memory 2, the write reset pulse WR2 (FIG. 3 (T)) is generated immediately after the fall of the non-inverted output (FIG. 3 (D)) of the frequency divider 38 by the delay circuit 42 and the NAND circuit 44a. It is generated, and this is the write reset terminal WR of the line memory 2.
2'supplied. In this way, the line memory 2 can perform write control for writing the Y signal data for one line from the zero address.

Next, the line memory 1 and the line memory 2
The read control will be described. The frequency divider 34 described above
The vertical scanning clock Hck is divided by 1/5 by the frequency divider (1/5) 36. As a result, a 5-line sequence for reading the line memory 1 and the line memory 2 is formed. That is, one of the outputs of the frequency divider 36 has a delay circuit 46.
3 is delayed by 3 vertical scanning clocks Hck to become the pulse shown in FIG. 3G, and the other output of the frequency divider 36 is frequency-divided by the frequency divider 48 into 1/2 to be shown in FIG. It becomes a pulse. These pulses are passed through the EX-OR circuit 50 and shown in FIG.
The pulse shown in (H) is obtained. One of the outputs of the EX-OR circuit 50 is delayed by the delay circuit 52 by one vertical scanning clock Hck, and its non-inverted output is the read enable pulse RE.
2 (FIG. 3 (I)) is supplied to the read enable terminal RE2 ′ of the line memory 2, and the inverted output is supplied to the read enable terminal RE1 ′ of the line memory 1 as a read enable pulse RE1 (FIG. 3 (J)). Then, when the read enable pulse RE1 is at the L level, data is compressed and read from the line memory 1 at the rate of the read clock RCK, and the read enable pulse R
When E2 is at the L level, the data is compressed and read from the line memory 2 at the rate of the read clock RCK.

The start control of the read addresses of the line memories 1 and 2 is performed as follows.
The vertical scanning clock Hck from the frequency divider 34 and the EX-OR circuit 50 are controlled by the delay circuit 54 and the NAND circuit 56a.
From the other output of the read reset pulse RR1 (FIG. 3 (Q)) and the write enable pulse RE1 (FIG. 3).
(J)) It is generated at a position corresponding to the vertical scanning clock Hck in the L level period. By supplying this to the read reset terminal RR1 ′ of the line memory 1, the line memory 1 reads the Y signal from the zero address. Similarly for the line memory 2, the read reset pulse R shown in FIG. 3 (U) is generated by the delay circuit 54 and the NAND circuit 56b.
R2 is generated and is supplied to the read reset terminal RR2 ′ of the line memory 2, so that the line memory 2
Reads the Y signal from the zero address.

The read clock RCK output from the multiplier 30 shown in FIG. 2 is also supplied to the signal supply circuit 24 shown in FIG. 1, and the non-interlaced video signals (R, G, B) supplied from the matrix 18 are supplied. ) Is taken in. Also,
The vertical synchronizing signal VD and the vertical scanning clock Hck which is the output of the frequency divider 34 are supplied to the scanning circuit 26, and the video signals (R, G, B) taken in by the signal supply circuit 24 are supplied to the liquid crystal panels LR, LG ,. Transfer to the corresponding line of LB.

From the above description, the odd-numbered lines of the interlaced video signal (Y signal) shown in FIG. 3 (K) are written in the line memory 1 as shown in FIG. 3 (M), As shown in FIG. 3 (R), even-numbered lines are written in the line memory 2. Then, the horizontal period of the first line is compressed to 3/5 and is read from the line memory 1 twice in succession (see FIG. 3).
Next, the second line is similarly read twice from the line memory 2 (58 in (N)) (6 in FIG. 3 (S)).
0), and the third line is read from the line memory 1 only once (62 in FIG. 3N). Thereafter, the Y signal is written and read in the same cycle, and the Y signal shown in FIG. 3L, which is non-interlaced into 5 lines with respect to 3 lines of the input PAL signal, is output from the scan converter. It is taken out from 41. This is displayed by the matrix display means including the signal supply circuit 24, the scanning circuit 26 and the liquid crystal panels LR, LG and LB via the matrix circuit 18.

In the scan converter of the first embodiment described above, when converting the Y signals for 3 lines into the non-interlaced Y signals for 5 lines, the interpolation line repeats the previous line. I am trying to display it. Such a configuration is simple and sufficiently practical, but depending on the image to be displayed, diagonal lines may be displayed in a staircase pattern, resulting in an unnatural display.

Therefore, in the second embodiment, a more natural display is made possible by taking the average of the lines before and after and generating the interpolation line. The configurations and operations of the timing generator and the scan converter in the second embodiment will be described below with reference to the block system diagram of FIG. 4 and the time chart of FIG. Description of the same parts as those in FIGS. 2 and 3 is omitted. Further, since the configuration of the other parts is the same as that of FIG. 1, the same components are designated by the same reference numerals, and the description thereof will be omitted.

The Y signal (FIG. 5 (J)) input to the input terminal 39 of the scan converter 14a passes through the A / D converter 40,
1 line delay circuit 64, one input terminal of adder 66,
It is input to one fixed terminal of the switch SW and the line memory 1. The video signal delayed by the 1-line delay circuit 64 by the 1-line period is supplied to the other input terminal of the adder 66. The output of the adder 66 is attenuator 68 and the level is 1 /
2 Therefore, the output signal of the attenuator 68 is always the Y signal of the average value level of the lines before and after the video signal (see FIG. 5).
(K)). This signal is supplied to the other fixed terminal of the switch SW. The switch SW is a Y signal of a real line (a line which is not interpolated) which is the output of the A / D converter 40, or the switch SW, which will be described later.
The Y signal of the interpolation line which is the output of the attenuator 68 is supplied to the line memory 2.

Next, the line memory 1 and the line memory 2
Writing and reading control of will be described. The horizontal synchronizing signal HD is a frequency dividing circuit 70 including a counter.
It is divided into 1/3 at (1/3). One of the outputs of the first bit of the frequency dividing circuit 70 (FIG. 5 (D)) is supplied to the write enable terminal WE1 ′ of the line memory 1 as the write enable pulse WE1, and the other one controls the switching of the switch SW. . The switch SW is shown in FIG.
When the write enable pulse WE1 shown in (D) is at the H level, the real line signal output from the A / D converter 40 is stored in the line memory 2 when the write enable pulse WE1 is at the L level, and the average value level interpolation signal from the attenuator 68 is stored in the line memory 2. Controlled to supply.
Therefore, as shown in FIG. 5 (R), the Y signal data is repeatedly supplied to the line memory 2 in the order of the interpolation line, the real line, the interpolation line, and then written by the write control described later. In the line memory 1, when the write enable pulse WE1 shown in FIG.
The Y signal from the / D converter 40 is written. Therefore, as shown in FIG. 5 (M), control is performed so that two lines are written every three lines and one line is not written.

As the write reset pulse WR2 (FIG. 5 (T)) for the line memory 2, the horizontal synchronizing signal HD
Are supplied to the write reset terminal WR2 '. Every time this pulse is supplied, Y signal data for one line is written in the line memory 2 from the zero address. Write reset pulse WR1 for line memory 1 (see FIG.
(P)) is a logic O of the write enable pulse WE1 (FIG. 5D) and the horizontal synchronizing signal HD by the OR circuit 72.
By taking R, the write enable pulse WE1
It is generated at a position corresponding to the horizontal synchronizing signal HD when (FIG. 5 (D)) is at L level. By supplying this to the write reset terminal WR1 ′ of the line memory 1, the Y signal for one line is written in the line memory 1 from the zero address.

Next, the line memory 1 and the line memory 2
The read control from will be described. Line memory 1
And read enable pulses RE1 and RE2 of 2 are generated as follows. Vertical scanning clock Hck (Fig. 5
1 of the frequency dividing circuit 74 (1/5) that divides (C)) by 1/5
The output of the bit (FIG. 5F) is delayed by 3 Hck and inverted, and the delay circuit 78 is delayed by 1 Hck.
Is delayed by 4Hck to become the pulse shown in FIG. 5H, and this pulse is supplied to the read enable terminal RE1 ′ of the line memory 1 as the read enable pulse RE1. Similarly, the pulse shown in FIG. 5 (I) delayed by 4 Hck and inverted is the read enable pulse RE.
2, the read enable terminal RE of the line memory 2
2'supplied. In addition, from the output of the vertical scanning clock Hck and the delay circuit 76, the delay circuit 80 and the NAND circuit 82a move to a position corresponding to the vertical scanning clock Hck when the read enable pulse RE1 is at the L level, as shown in FIG. ) Read reset pulse RR
1 and the read reset terminal RR of the line memory 1
Supply 1 '. Similarly, the delay circuit 80 and the NAND circuit 82b generate a read reset pulse RR2 shown in FIG. 5 (U) and supply it to the read reset terminal RR2 ′ of the line memory 2.

Read enable pulses RE1 and RE2
Is at L level and read reset pulses RR1 and R
Each time R2 is supplied, the line memory 1 and the line memory 2 read the Y signal from the zero address at the rate of the read clock RCK. Therefore, the Y signal read from the line memory 1 and the line memory 2 is shown in FIG.
(S), and the output from the output terminal 41 of the scan converter 14a is a composite of these, as shown in FIG. 5 (L). That is, the scan converter 14a
From the 1st line, the average of the 1st and 2nd lines, the 2nd line, the 3rd line, the average of the 3rd and 4th lines, and so on. . This signal is a non-interlaced signal composed of 312 real lines and 208 interpolation lines per field, as in the first embodiment.
The matrix display means configured for C signal display enables the display in which the vertical direction of the image is compressed. The video signal display devices described in the first and second embodiments are time-compressed to 5/3 times the input video signal to be non-interlaced, and have equal intervals corresponding to the line frequency of the non-interlaced video signal. Since the matrix display means is driven by the vertical scanning clock Hck, there is no occurrence of image flicker or flicker.

The first and second embodiments described above are as follows.
Liquid crystal panels LR, LG, L configured for NTSC signals
It is a display device dedicated to the PAL signal using B. In the third embodiment, the NTSC signal (first video signal) and PAL
A display device capable of switching and displaying a signal (second video signal) will be described with reference to FIG. The same components as those of the conventional example, the first embodiment and the second embodiment are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 6, the scan conversion means of the present invention according to claim 2 is an NTSC memory control circuit 8 to be described later.
6, PAL memory control circuit 88, NTSC signal input circuit 100, PAL signal input circuit 102, switching circuit 9
0 and 104, a memory 106 and a scan converter 108. The sync separation circuit 84 receives the input NT
The horizontal synchronizing signal HD and the vertical synchronizing signal VD are separated from the SC signal or the PAL signal. In addition, the sync separation circuit 84
Has an input video signal field frequency of 60 Hz (NT
It has an input signal discriminating means for discriminating between the SC signal input) and the 50 Hz (PAL signal input). NTSC signal has 525 lines per frame
The PAL signal has 62 lines per frame.
Therefore, the difference in the number of lines per frame of the input video signal can be determined by determining the field frequency. The input signal discriminating means outputs the discrimination signal d to output the switching circuit 90, the switching circuit 104, the switch SW2.
The data is supplied to the switch SW3 and the scan converter 108 described later. As a result, when the NTSC signal is input, the NTS
C memory control circuit 86 and NTSC signal input circuit 1
The outputs of 00 are the switching circuit 90 and the switching circuit 10, respectively.
By being selected in 4 and supplied to the memory 106,
The configuration is similar to that shown in FIG. 9 shown as a conventional example. Also, N
The Y signal from the NTSC Y / C separation circuit 92 is supplied to the TSC signal input circuit 100 by the switch SW2. As a result, the NTSC Y / C separation circuit 9
It is possible to perform scan conversion of the Y signal from 2. Next, when the PAL signal is input, the PAL memory control circuit 88
And outputs of the PAL signal input circuit 102 are selected by the switching circuit 90 and the switching circuit 104, respectively.
By supplying to No. 6, the same configuration as that of FIG. 2 or FIG. 4 shown as the first embodiment or the second embodiment is formed. In addition, the switch SW3 is provided in the PAL signal input circuit 102.
Thus, the Y signal from the PAL Y / C separation circuit 94 is supplied. As a result, the PAL Y / C separation circuit 9
The scanning conversion of the Y signal from 4 can be performed. The scan converter 108 is a scan converter for color signals. N
When the TSC signal is input, the color difference signal from the NTSC decoder 96 selected by the switch SW3 is scan-converted. When the PAL signal is input, the color difference signal from the PAL decoder 98 selected by the switch SW3 is scan-converted. The non-interlaced color difference signals that are scan converted by the scan converter 108 are supplied to the matrix circuit 18.

With the above structure, when the NTSC signal is input, the non-interlaced signal, which is twice compressed in time and formed with an interpolation line for each line, and the scanning line number is doubled, is applied to the matrix circuit 18 and the signal. It is displayed on the liquid crystal panels LR, LG, LB via the supply circuit 24. On the other hand, P
When an AL signal is input, a non-interlaced signal, which is time-compressed to 5/3 times and in which two interpolation lines are formed every three lines, is similarly displayed on the liquid crystal panels LR, LG, LB. Therefore, the liquid crystal panel configured for displaying the NTSC signal can switch and display both the NTSC signal and the PAL signal, and the display does not look unnatural even when the PAL signal is input. Non-interlaced display is possible by compressing the vertical direction of.

In the above description of the first and second embodiments,
The scan converter 14a will be described only for the Y signal,
Although the description of the color difference signal is omitted, the scan converter 14
Reference character a has a configuration for performing scan conversion of color difference signals. Further, in each embodiment, the scan conversion for the color signal may be the scan conversion by the same line interpolation as the Y signal,
Scan conversion by line interpolation, which is simpler than the Y signal, may be used. Also, the PAL signal was explained, but SECAM
The same can be done for signals.

[0037]

As described above, the video signal display device according to the present invention is non-interlaced by time compression so that the number of interpolated scanning lines becomes smaller than the number of scanning lines of the input video signal in a certain period. Since it is configured to generate a video signal that has been generated and to display it by the matrix display means, it is not necessary to use an expensive standard system conversion device like the conventional one.
For example, a PAL signal or a SECAM signal, for example, can be displayed on the matrix display means configured for NTSC signals with a simple configuration and with high quality while performing more natural vertical compression.

Further, the video signal display device according to the present invention is
In addition to the above configuration, it is determined whether any one of a plurality of video signals having different scanning lines per frame is input,
According to the input video signal, it is configured to generate a non-interlaced video signal by time compression so as to change the number of interpolated scanning lines with respect to the number of scanning lines for a certain period.
A single video signal display device can display a plurality of video signals with different number of scanning lines per frame naturally and satisfactorily without using an expensive standard system converter as in the prior art.

[Brief description of drawings]

FIG. 1 is a block system diagram for explaining a first embodiment of the present invention.

FIG. 2 is a block system diagram for explaining a main part of FIG.

FIG. 3 is a time chart for explaining the operation of FIG.

FIG. 4 is a block system diagram for explaining an essential part of a second embodiment of the present invention.

FIG. 5 is a time chart for explaining the operation of FIG.

FIG. 6 is a block system diagram for explaining an essential part of a third embodiment of the present invention.

FIG. 7 is a configuration diagram showing an example of an optical system of a conventional liquid crystal projector for NTSC signals.

FIG. 8 is a block system diagram for explaining a signal processing system of a conventional liquid crystal projector for NTSC signals.

9 is a block system diagram for explaining a main part of FIG.

10 is a time chart for explaining the operation of FIG.

[Explanation of symbols]

 12a Y / C separation circuit for PAL 14a Scan converter 16a PAL decoder 18 Matrix circuit 22a Timing generator 24 Signal supply circuit 26 Scan circuit 30 Multiplier 32 Multiplier 34 Divider 36 Divider 40 A / D converter 64 1 Line delay circuit 66 Adder 68 Attenuator 84 Sync separation circuit 90 Switching circuit 104 Switching circuit LR Liquid crystal panel LG Liquid crystal panel LB Liquid crystal panel

Claims (2)

(57) [Claims] 1. A video signal display device for generating a non-interlaced video signal by performing scanning line interpolation on an input video signal and displaying the non-interlaced video signal. Scanning line conversion means for time-compressing so as to reduce the number of scanning lines to generate a non-interlaced video signal; and matrix display means for displaying the non-interlaced video signal. Characteristic video signal display device. 2. A non-interlaced video signal is generated by performing scan line interpolation on the first video signal or a second video signal having more scan lines per frame than the first video signal, An image signal display device for displaying an image based on this, comprising: input signal determination means for determining whether one of the first image signal and the second image signal has been input; and the input determination. When the means determines that the first video signal has been input, it is time-compressed and non-interlaced so that the number of interpolated scanning lines is equal to the number of scanning lines of the first video signal for a certain period. When the input determining means determines that the second video signal is input, the number of interpolation scanning lines is smaller than the number of scanning lines of the second video signal for a certain period. Time to be A video signal display device comprising: a scanning line conversion means for compressing and generating a non-interlaced video signal; and a matrix display means for displaying the non-interlaced video signal.