JP2605890B2 - Sense amplifier circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a sense amplifier circuit.

[Conventional technology]

The signal voltage read from the memory cell is decreasing due to the miniaturization of the circuit elements constituting the LSI and the decrease in the power supply voltage. Nevertheless, in order to shorten the memory access time, high speed operation of a sense amplifier circuit for amplifying a signal voltage is an essential condition.

As a circuit for speeding up this sense amplification, for example, a preprint of the 1989 VSLI Circuit Symposium “1989, Symposium in VSI Circuit, Digest of Technical Papers (1989 SYMPO)
SIUM ON VSLI CIRCUITS, DIGEST OF TECHNICAL PAPER
S) ”on page 114. This circuit is shown in FIG.

This sense amplifier circuit includes, in addition to an amplifier circuit composed of a CMOS flip-flop, a common source SAP of a P-channel MISFET of the flip-flop and a transfer gate Q of a P-channel MISFET having a gate connected to a sense start signal line φ _SP. Connected to power supply voltage level VCC through _P and N
The common source SAN channel type MISFET, connected to the ground level VSS through the transfer gate Q _N of the N-channel type MISFET connecting a sense start signal line phi _SN to the gates.

Here, by setting φ _SP to a low level and φ _SN to a high level, the drivers MISFET, Q _DP , and Q _DN are operated, and the node SA
Sense amplification is performed by setting P and SAN from the precharge level to VCC and VSS, respectively.

In the sense amplification in which only the SAP and SAN are driven by the driver MISFET, the amplification is slow because the resistance of the SAP and SAN signal lines is large. However, in addition to this, the transfer gate Q _P
And Q _N are rendered conductive, since the node SAP, SAN are short-circuited to each power supply line, VCC, reaching the VSS level is increased, thus, also to speed signal amplification of the bit line.

[Problems to be solved by the invention]

In conventional sense amplifier circuits, the wiring length of φ _SP and φ _SN signal lines becomes longer, the wiring delay increases, and the falling and rising of φ _SP and φ _SN are delayed, resulting in transfer gates in the sense amplifier circuit. There is a disadvantage that conduction of Q _P and Q _N is delayed.

An object of the present invention is to provide a circuit that eliminates the operation delay due to the resistor r and realizes high-speed sense amplification.

[Means for Solving the Problems] A sense amplifier circuit according to a first invention comprises a bit line connecting a plurality of memory cells, first and second P-channel MISFETs.
Cross-connect the drain and the gate of
A P-channel dynamic flip-flop circuit in which the source and the second P-channel MISFET are connected to each other, and the drain and the gate of the first and second N-channel MISFETs are cross-connected to each other and connected to a second bit line; An N-channel dynamic flip-flop circuit connecting the sources of the first and second N-channel MISFETs; a drain of the first P-channel MISFET and the first N-channel MISFET;
Connect to the drain of the SFET, connect to the first bit line,
A CMOS flip-flop circuit in which a drain of the second P-channel MISFET is connected to a drain of the second N-channel MISFET and connected to a second bit line;
A circuit in which a common source of the second N-channel type MISFET is connected to a ground level power supply line via a transfer gate composed of an N-channel type MISFET in which a column selection signal line as an output of a column selection circuit is connected to a gate; And a third P-channel type MISFET having a gate connected to a common source of the second P-channel type MISFET and a signal line for transmitting an inverted signal of a column selection signal.
It is composed of a circuit connected to a power supply voltage level power supply line via a transfer gate composed of an SFET.

The sense amplifier circuit of the second invention is a third P-channel type.
In place of the MISFET, a common source of the first and second P-channel MISFETs is provided with a circuit for generating an inverted signal of the column selection signal, and the output signal is connected to the gate and the fourth P-channel MISFET is connected. It is composed of a circuit connected to a power supply voltage level power supply line via a transfer gate.

The sense amplifier circuit of the third invention is a third P-channel type sense amplifier circuit.
In place of the MISFET, a common source of the first and second P-channel MISFETs is connected to a power supply voltage level power supply line via a transfer gate composed of a third N-channel MISFET having a gate connected to a column selection signal line. It consists of the circuit which did.

[Action]

Conventionally, transfer gates Q _P and Q _N in all sense amplifier circuits in one block are driven by signals φ _SP and φ _SN . In the present invention, however, the transfer gates are output from a column selection circuit. Is driven by the column selection signal YDEC.

Generally, low resistance wiring such as aluminum is used for the column selection signal line. Regarding wiring, φ _SP and φ _SN must be connected from the driver circuit to all sense amplifier circuits in one block, while YDEC is connected to one sense amplifier circuit selected from the column selection circuit. For this reason, the wiring length can be reduced as compared with the signal lines φ _SP and φ _SN .

Therefore, according to the present invention, the influence of wiring delay when driving the transfer gates Q _P and Q _N in the sense amplifier circuit is reduced, and the speed of sense amplification can be increased.

〔Example〕

 Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a sense amplifier circuit on which the present invention is based.

After the data is read from the memory cell and the signal voltage appears on the bit line, the common source of the CMOS flip-flop is
SAP, drives each driver MISFET a SAN, Q _DP, the Q _DN, performing initial amplification.

Thereafter, a column selection signal is generated from the column selection circuit, and the
And Q _N are turned to connect the ground line VSS, the sense amplifier is accelerated. As described in (acts) term, compared with a method of driving the transfer gate Q _N in a conventional sense start signal phi _SN, method of driving the column selection signal YDEC of the invention it is possible to reduce the wiring delay, Higher speed sense amplification can be performed.

 FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

In addition to connecting the SAN and VSS when the sense amplifier, to conduct Q _P by an inverted signal ▲ ▼ column select signal YDEC,
By connecting the common source SAP of the P-channel type dynamic flip-flop to the VCC power supply line, the SAP VCC
Reaching the level is also speeding up.

 FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

In the invention of FIG. 2, the inverted signal of the column selection signal YDEC
The point that ▼ is generated from the column selection circuit section and the two signal lines of YDEC and ▲ ▼ are formed on the memory cell array is improved, and a circuit for generating an inverted signal of YDEC is provided in the sense amplifier circuit. the output of the connected to the gate of Q _P. By doing so, the number of signal lines extending over the memory cell array can be reduced to one, and the same effect as the second invention can be obtained.

 FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

In the invention of FIG. 3, to improve the point that must be provided inverting circuit to the sense amplifier, the transfer gate Q _P which connects the SAP and VCC is N-channel type MISFET. By doing so, the signal line extending over the memory cell array
In addition to using only EC, there is no need to generate the inverted signal ▲ ▼ of YDEC. Therefore, there is no need to provide an inverting circuit as in the invention of FIG.

〔The invention's effect〕

As described above, the sense amplifier circuit of the present invention includes the transfer gate connecting the sense amplifier circuit and the power supply line, and controls the conduction / non-conduction of the transfer gate by the column selection signal line from the column selection circuit. By doing so, there is an effect that high speed sense amplification can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a sense amplifier circuit on which the present invention is based. FIGS. 2, 3, and 4 are circuit diagrams showing one embodiment of the first to third inventions, respectively, and FIG. 5 is a circuit diagram showing an example of the prior art. VCC: High-level power supply voltage, VSS: Low-level power supply voltage,
BL, ▲ ▼… Bit line, IO, ▲ ▼… I / O line, SA
P: Sense amplifier P-channel flip-flop common source, SAN: Sense amplifier N-channel flip-flop common source, φ _SP , φ _SN Sense start signal, YDEC Column selection signal line, ▲ ▼ ... YDEC inverted signal, QN ... Transfer gate connecting SAN and VSS, QP ... Transfer gate connecting SAP and VCC, Q
_DP: SAP driver circuit, Q _DN: SAN driver circuit, YSW
…… Transfer gate that connects BL and IO, r …… Wire resistance.

Claims (3)

(57) [Claims] 1. A bit line connecting a plurality of memory cells, a drain and a gate of first and second P-channel MISFETs are cross-connected, and said first and second P-channel MISFETs are connected to each other.
A drain and a gate of a P-channel type dynamic flip-flop circuit to which the source of the ET is connected, and a drain and a gate of the first and second N-channel type MISFETs which are connected to each other;
N-channel dynamic flip-flop circuit connecting the sources of the N-channel MISFETs, the drain of the first P-channel MISFET and the first N-channel MISF
The drain of the ET was connected to the first bit line, and the drain of the second P-channel MISFET and the drain of the second N-channel MISFET were connected to the second bit line. A CMOS flip-flop circuit, an N-channel type in which a common source of the first and second N-channel type MISFETs is connected to a gate of a column selection signal line which is an output of a column selection circuit;
A circuit connected to a ground level power supply line via a transfer gate composed of an MISFET, first and second P-channel type MIs
A circuit in which a common source of the SFET is connected to a power supply voltage level power supply line via a transfer gate including a third P-channel type MISFET in which a signal line for transmitting an inverted signal of a column selection signal is connected to a gate. Sense amplifier. 2. A semiconductor device comprising: a first P-channel type MISFET;
And a common source of the second P-channel MISFET is provided with a circuit for generating an inverted signal of a column selection signal, and the output signal is connected to a gate through a transfer gate composed of a fourth P-channel MISFET. 2. The sense amplifier according to claim 1, further comprising a circuit connected to the level power supply line. 3. A first P-channel type MISFET instead of a third P-channel type MISFET.
And a circuit in which a common source of the second P-channel MISFET is connected to a power supply voltage level power supply line via a transfer gate composed of a third N-channel MISFET having a gate connected to a column selection signal. 2. The sense amplifier according to claim 1, wherein: