KR19980026426A - Bit line sensing method using dummy cell - Google Patents

Abstract

In order to provide an improved bit line sensing method in a memory having a high density structure, a method of disposing a dummy cell having the same structure as a memory cell for storing data is provided for each of a plurality of memory cells, wherein a power supply voltage is provided in a word line of the dummy cell. And a common ground terminal of the driving transistors in the dummy cell are connected through a switching unit to amplify the voltage difference between the pair of bit lines represented by the current of the selected memory cell immediately before the sense amplifier performs a sensing operation. The dummy cell may be driven by applying a switching signal to the switching unit.

Description

Bit line sensing method using dummy cell

The present invention relates to a volatile semiconductor memory, and more particularly, to a bit line sensing method using a dummy cell in a memory such as a fast SRAM.

In general, a bit line sensing scheme for reading data stored in a memory cell in a volatile semiconductor memory such as a static RAM or the like has a structure as shown in FIG. 1. In Fig. 1, reference numerals 2 and 3 denote precharge elements, and reference numeral 4 denotes equalization elements for equalizing bit line pairs BL and / BL. Also, reference numerals 5, 6, and 7 denote memory cells MC1, 2, ... n. Reference numerals 8 and 9 denote transmission gates for transmitting the level of data respectively appearing in the bit line pair BL, / BL in response to the column decoding signal. The block sense amplifier 10 receives, as input signals through the transfer gates 8 and 9, the level of data respectively appearing in the bit line pair BL, / BL after a specific word line is selected in SWL1-n among the word lines. Then, it senses and amplifies and generates output signals SASP and / SASP as outputs.

1 having the above-described structure is a circuit diagram of a typical bit line sensing scheme of a semiconductor memory, and has been mainly employed in synchronous SRAMs of 1 megabit or less. In recent years, in accordance with the demand for high integration and high speed of memory chips, the size of CMOS devices mounted on high-speed SRAMs and the like has gradually decreased, and the operating speed of peripheral circuits also increases. However, it can be seen that the sensing speed of the bit line sensing circuit as described above is determined by the loading of the memory cells and the capacitance between the bit line and the section data line and is not related to the scale-down of the CMOS device. In other words, in order to increase the sensing speed of the bit line sensing circuit, the cell current flowing from the memory cell to the bit line must be increased. As the size of the SiMOS device mounted on the high speed SRAM or the like decreases more and more, the cell current becomes rather low, and thus the speed of sensing decreases. This slowing down of sensing speed in the field is caused more seriously by going from 1 Megabit SRAM to 4 Megabit SRAM. This problem is fundamentally attributable to the increase in the loading of memory cells as the density of memory cells increases.

Accordingly, an object of the present invention is to provide an improved bit line sensing method of a volatile semiconductor memory which can solve the above-mentioned conventional problems.

Another object of the present invention is to provide a bit line sensing method using a dummy cell that can improve the speed of a sensing operation of a semiconductor memory device.

1 is a circuit diagram of a semiconductor memory applied to the prior art.

2 is a circuit diagram of a semiconductor memory to which the present invention is applied.

3 is a detailed circuit diagram of a dummy cell according to an embodiment of FIG. 2;

Figure 4 is a waveform diagram showing the effect of bit line sensing according to an embodiment of the present invention.

According to the method of the present invention for achieving the above object, a dummy cell having the same structure as the memory cell for storing data is arranged for each of the plurality of memory cells, the power supply voltage is provided to the word line of the dummy cell The common ground terminal of the driving transistors in the dummy cell is connected to the switching unit to switch the switching unit to amplify the voltage difference between the pair of bit lines represented by the current of the selected memory cell immediately before the sense amplifier performs the sensing operation. The dummy cell is driven by applying a signal.

According to the above method, since the sense amplifier receives the voltage of the bit line pair sensed and amplified primarily by the dummy cell, the sensing operation speed is faster than in the related art.

Hereinafter, a sensing method according to a preferred embodiment of the present invention will be described with the accompanying drawings. Like elements in the accompanying drawings are labeled with the same or similar reference numerals or names for ease of understanding. In the following description, specific details are set forth by way of example and in detail in order to provide a more thorough understanding of the present invention. However, for those skilled in the art, the present invention may be practiced by the above description without these details. Furthermore, semiconductor manufacturing processes so well known in the art, and the basic operations of each device, are not described in detail in order not to obscure the subject matter of the present invention.

In the following description, a preferred embodiment of the present invention will be described by way of example only and with reference to the accompanying drawings.

2 is a circuit diagram of a semiconductor memory according to an embodiment of the present invention, and FIG. 3 is a detailed circuit diagram of a dummy cell according to an embodiment of FIG. 2. 4 is a waveform diagram showing the effect of bit line sensing according to an embodiment of the present invention.

First, referring to FIG. 2, reference numerals 2 and 3 denote precharge elements, and reference numeral 4 denotes equalization elements for equalizing bit line pairs BL and / BL. In addition, reference numerals 5 and 7 denote memory cells MC1, ... n. Reference numerals 8 and 9 denote transmission gates for transmitting the level of data respectively appearing in the bit line pair BL, / BL in response to the column decoding signal. The block sense amplifier 10 receives, as input signals through the transfer gates 8 and 9, the level of data respectively appearing in the bit line pair BL, / BL after a specific word line is selected in SWL1-n among the word lines. Then, it senses and amplifies and generates output signals SASP and / SASP as outputs. Here, the above components have the same structure and function as the components of FIG.

However, it should be noted that in FIG. 2, dummy cells 50 and 70 having the same structure as that of the memory cell storing data are disposed for each of the plurality of memory cells. A power supply voltage Vcc is provided to each word line DSWL1, n of the dummy cells 50 and 70, and the common ground terminal A of the driving transistors in the dummy cell is connected to the ground through the switching unit 100. A semiconductor memory having such a structure is manufactured, and the dummy cell is driven by applying a switching signal to the switching unit 100 immediately before the sense amplifier 10 performs a sensing operation, that is, immediately before a sense amplifier enable signal is provided. Then, the voltage difference between the pair of bit lines represented by the current of the selected memory cell is amplified than the original voltage difference. That is, the sense amplifier 10 may receive a voltage level higher than the voltage level of the developed bit line pair from the memory cell to perform sensing amplification.

Here, the switching unit 100 is preferably implemented with an N-type MOS transistor, and a pulse signal Yi + K is applied to the gate terminal thereof as the switching signal. In addition, the pulse signal is generated by the peripheral circuit portion generating the column decoding signal. The reason for providing a pulse to the gate terminal is to quickly return the bit line pair to the precharge level when the amplification operation of the dummy cell ends. Meanwhile, the common ground terminal A may be connected to a separate metal layer through a contact. In this case, the metal layer of the semiconductor memory device may be three layers. That is, when the bit line pair BL // BL is implemented as the first metal layer and the word line of the memory cell is the second metal layer, the common ground terminal A becomes the third metal layer.

Referring to FIG. 3, a concrete circuit of the dummy cell is shown. It can be seen that the structure of the dummy cell is the same as that of a general memory cell, except that a power supply voltage is applied to a portion where a word line of a normal cell is connected, and a common ground terminal A is connected to a separate metal layer through a contact. The connection is different.

4, the effect of bit line sensing according to the present embodiment is shown in contrast to that of the conventional. 4 is a graph illustrating time versus voltage as a result of dividing two dummy cells when one block sense amplifier 10 of FIG. 2 is connected to 256 memory cells. In Fig. 4, reference numerals P1 and P2 denote input and output waveforms of a conventional general sense amplifier, and T1 and T2 are input and output waveforms for the embodiment of the present invention. As described above, since the sense amplifier generates an output by receiving the voltage of the bit line pair sensed and amplified by the dummy cell, the sensing speed of the sensing operation is faster than in the related art.

According to the present invention as described above, there is an effect that can improve the bit line sensing speed.

Although the above-described invention has been described and limited by way of example with reference to the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention.

Claims (6)

A bit line sensing and amplification method of a semiconductor memory device, comprising: disposing a dummy cell having a structure identical to that of a memory cell storing data, for each of a plurality of memory cells, wherein a power supply voltage is provided to a word line of the dummy cell; The common ground terminal of the driving transistors in the micelle is connected through the switching unit, so that the switching signal is switched to the switching unit to amplify the voltage difference between the pair of bit lines represented by the current of the selected memory cell immediately before the sense amplifier performs the sensing operation. Applying a driving method to drive the dummy cell. A data sensing and amplifying method of a synchronous SRAM: A dummy cell having the same structure as a memory cell storing binary data is arranged for each of a plurality of memory cells, wherein a power supply voltage is provided to a word line of the dummy cell, and the dummy cell The common ground terminal of the driving transistors in the connection is connected through a switching unit, so that when the sense amplifier starts a sensing operation, the switching signal is applied to the switching unit to drive the dummy cell bit, the sense amplifier developed from the memory cell And detecting amplification by receiving a voltage level higher than that of the line pair. The method of claim 1, wherein when the switching unit is implemented as a MOS transistor, a pulse signal is applied to the gate terminal thereof as the switching signal. The method of claim 1, wherein the pulse signal is generated by a peripheral circuit part generating a column decoded signal. 4. The method of claim 3, wherein the MOS transistor is an N-type MOS transistor. The method of claim 1, wherein the common ground terminal is connected to a separate metal layer through a contact.