KR100228525B1 - Method for sensing bit-line using dummy cell - Google Patents

Abstract

A method for providing an improved bit line sensing method in a highly integrated memory includes disposing a plurality of memory cells each having a structure identical to that of a memory cell storing data, And the common ground terminal of the driving transistors in the dummy micelles are connected through the switching unit so that the voltage difference between the bit line pairs indicated by the current of the selected memory cell immediately before the sense amplifier performs the sensing operation is amplified And a switching signal is applied to the switching unit to drive the dummy micelles.

Description

METHOD FOR SENSING BIT-LINE USING DUMMY CELL [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a volatile semiconductor memory, and more particularly, to a bit line sensing method using a micelle in a memory such as a high-speed scrambler (SRAM).

Generally, a bit line sensing scheme for reading data stored in a memory cell in a volatile semiconductor memory, such as a static RAM, has a structure as shown in FIG. In Fig. 1, reference numerals 2 and 3 denote a precharging circuit, and reference numeral 4 denotes an equalizing circuit for equalizing the bit line pair BL and / BL. Reference numerals 5, 6 and 7 denote memory cells MC1, MC2, ... MCn. Reference numerals 8 and 9 denote transfer gates (or column select gates) for transferring the level of data appearing respectively in the bit line pair BL and / BL in response to the column decode signal. The block sense amplifier 10 receives the level of data appearing on the bit line pair BL and / BL as input signals through the transmission gates 8 and 9 after a specific word line is selected in SWL1-SWLn among the word lines , And sense amplifies it to generate output signals SASP and / SASP.

1 having the above-described structure is a circuit diagram of a typical bit line sensing scheme of a semiconductor memory, and has been mainly employed in synchronous esters of less than 1 megabit. Recently, with the demand for high integration and speeding up of memory chips, the size of a CMOS device mounted on a high-speed ESRAM is gradually decreasing, and the operating speed of a peripheral circuit is gradually increasing. However, the sensing speed of the bit line sensing circuit as described above is determined by the loading of the memory cells and the capacitance between the bit line and the section data line, and is independent of the scale-down of the CMOS sensor. That is, in order to increase the sensing speed of the bit line sensing circuit, the cell current flowing from the memory cell to the bit line must be increased. If the size of a CMOS sensor mounted on a high-speed ESRAM or the like is gradually reduced, the cell current is lowered, and the sensing speed is lowered. The problem of slowing down the sensing speed in this field is caused more severely by going from 1 megabit sram to 4 megabit sram. This problem is fundamentally caused by an increase in the loading of the memory cells as the degree of integration of the memory cells increases.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an improved bit line sensing method of a volatile semiconductor memory capable of overcoming the above-described problems of the related art.

It is another object of the present invention to provide a bit line sensing method using a dummy cell which can improve the speed of a sensing operation of a semiconductor memory device.

According to an aspect of the present invention, there is provided a memory cell array including a plurality of memory cells, each memory cell including a plurality of memory cells, The common ground terminal of the driving transistors in the dummy micelles is connected through the switching unit to switch the switching unit to amplify the voltage difference between the bit line pairs indicated by the current of the selected memory cell immediately before the sense amplifier performs the sensing operation And a signal is applied to drive the dummy micelles.

According to the above-described method, since the sense amplifier receives the voltage of the bit line pair that is primarily sensed and amplified by the dummy micelles, the speed of the sensing operation is faster than that of the conventional art.

1 is a circuit diagram of a semiconductor memory applied to the prior art;

2 is a circuit diagram of a semiconductor memory according to an embodiment of the present invention;

FIG. 3 is a specific circuit diagram of a dummy micelle according to an embodiment of FIG. 2. FIG.

FIG. 4 is a waveform diagram showing the effect of bit line sensing according to an embodiment of the present invention; FIG.

Hereinafter, a sensing method according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the following description, specific details are set forth, by way of example only, to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In addition, the semiconductor manufacturing processes well known in the art, and the basic operations of each element, are not described in detail in order to avoid obscuring the gist of the present invention.

In the following description, a preferred embodiment of the present invention will be described by way of example only and with reference to the accompanying drawings.

FIG. 2 is a circuit diagram of a semiconductor memory according to a preferred embodiment of the present invention, and FIG. 3 is a specific circuit diagram of a dummy cell according to an embodiment of FIG. FIG. 4 is a waveform diagram illustrating the effect of bit line sensing according to an embodiment of the present invention.

2, reference numerals 2 and 3 denote a precharging circuit, and reference numeral 4 denotes an equalizing circuit for equalizing bit line pairs BL and / BL. Reference numerals 5 and 7 denote memory cells MC1, ..., MCn. Reference numerals 8 and 9 are transmission gates for transmitting the level of data appearing respectively in the bit line pair BL and / BL in response to a column decoding signal. The block sense amplifier 10 outputs the level of data appearing respectively in the bit line pair BL and / BL to the transfer gates 8 and 9 after the word line is selected from SWL1 to SWLn and dummy word lines DSWL1 to DSWLn among the word lines, 9, and senses and amplifies the signals to generate output signals SASP and / SASP. Here, the above-described components have the same structure and function as the components of Fig.

It should be noted that in FIG. 2, the micelles 5 and 7 having the same structure as that of the memory cell storing data are arranged for a plurality of memory cells. The dummy word lines DSWL1 and DSWLn of the dummy micelles 5 and 7 are provided with a power supply voltage Vcc and the common ground terminal A of the driving transistors in the dummy cells 5 and 7 is connected to the ground through the switching unit 100. [ A semiconductor memory having such a configuration is manufactured and a switching signal is applied to the switching unit 100 immediately before the block sense amplifier 10 performs a sensing operation, that is, immediately before a sense amplifier enable signal is provided, When driven, the voltage difference between the bit line pairs represented by the current of the selected memory cell is amplified rather than the original voltage difference. That is, the block sense amplifier 10 receives the voltage level higher than the voltage level of the bit line pair developed from the memory cell, and performs the sensing amplification.

Here, it is preferable that the switching unit 100 is implemented as a mono-transistor of a round shape, and a pulse signal Yi + K is applied to the gate terminal thereof as the switching signal. In addition, the pulse signal Yi + K is generated in a peripheral circuit section for generating a column decoding signal. The reason for providing a pulse to the gate terminal is to return the pair of bit lines BL and / BL to the free charge level at the end of the amplification operation of the data signal output from the dummy cells 5 and 7. [

Meanwhile, the common ground terminal A may be connected to a separate metal layer through a contact. In this case, the metal layer of the semiconductor memory device becomes three layers. That is, when the bit line pair BL and / BL are implemented as the first metal layer and the word line of the memory cell as the second metal layer, the common ground terminal A becomes the third metal layer.

Referring to FIG. 3, a specific circuit of the dummy micelle is shown. It can be seen that the structure of the dummy cell is the same as that of a general memory cell. However, the power supply voltage is applied to the portion of the memory cell where the word line is connected, and the common ground terminal A is connected to a separate metal layer through the contact.

Referring to FIG. 4, the effect of the bit line sensing according to the present embodiment is shown in comparison with the conventional one. 4 is a graph of time vs. voltage as a result of dividing and arranging two dummy cells when one block sense amplifier 10 of FIG. 2 is connected to 256 memory cells. In FIG. 4, reference symbols P1 and P2 indicate input / output waveforms of a conventional sense amplifier, and T1 and T2 are input / output waveforms according to the embodiment of the present invention. As described above, the sense amplifier receives the voltage of the bit line pair sensed and amplified first by the dummy micelles and generates an output, so that the emulation speed of the sensing operation is faster than that of the prior art.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art without departing from the spirit and scope of the invention.

According to the present invention as described above, the bit line sensing speed can be improved.

Claims (6)

A bit line sensing and amplifying method for a semiconductor memory device, Wherein a dummy cell having the same structure as a memory cell storing data is disposed for each of a plurality of memory cells, a power supply voltage is provided to the word line of the dummy cell, and a common ground terminal of the driving transistors in the dummy cell is connected And a switching signal is applied to the switching unit to amplify the voltage difference between the pair of bit lines represented by the current of the memory cell selected immediately before the sense amplifier performs the sensing operation to drive the the micelles Way. In a synchronous ESRAM data detection amplification method, Wherein a source voltage is provided to the word line of the dummy cell and a common ground terminal of the driving transistors in the dummy cell is connected to the drain of the memory cell through the switching unit When the sense amplifier starts a sensing operation, a switching signal is applied to the switching unit to drive the dummy cell so that the sense amplifier receives a voltage level higher than the voltage level of the bit line pair developed from the memory cell To perform the detection amplification. The method of claim 1, wherein when the switching unit is implemented as a MOSFET, a pulse signal is applied to the gate terminal thereof as the switching signal. 2. The method of claim 1, wherein the pulse signal is generated in a peripheral circuit portion generating a column decoding signal. 4. The method of claim 3, wherein the morse transistor is a mono type transistor. 2. The method of claim 1, wherein the common ground terminal is connected to a separate metal layer through a contact.