JP2600345B2 - Refresh delivery method for dynamic random access memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system using a dynamic random access memory (hereinafter abbreviated as DRAM) as a main memory.

2. Description of the Related Art As shown in FIG. 3, in a system using a current DRAM as a main memory, only one DRAM interface 100 refreshes the DRAM. Where 102
Is a processor A, 104 is a processor B, 106 is a main memory composed of DRAM, 108 is a system data bus, and 110 is a system address bus.

It is expected that processor chips having a DRAM interface and a function of refreshing main memory will appear in the future as processors become more sophisticated. Further, when a multi-processor configuration is adopted with such a chip, one of the processors only needs to refresh the main memory. Therefore,
In such a system, a situation appears in which the processor for refreshing the main memory is changed.

In the system shown in FIG. 3, the processor A 102 starts refreshing from the head address of the main memory 106 as shown in step a of FIG. 4 and refreshes an address as shown in step b of FIG. 106
Refresh master from processor A102 to processor
In the case of changing to B104, as shown in steps c to d in FIG. 4, the address that refreshes the main memory 106 is passed between the processors and the refresh is continued with the succeeded address.

Alternatively, as shown in FIG. 5, when the processor to be refreshed is changed at the same timing as before, as shown in steps c to d in FIG. 5, the address for refreshing the main memory is not transferred between the processors. It is conceivable to start refreshing from a new head address.

Problems to be Solved by the Invention However, in the former case, an operation of passing an address for refreshing the main memory between processors is required,
In the latter case, there is a possibility that a portion where refresh is not performed for a refresh cycle exceeding the DRAM specification may appear in the hatched portion of step d in FIG.
There is a possibility of destroying the data stored in.

Means for Solving the Problems In view of such a problem, the present invention shares a main memory including a dynamic random access memory and a function of refreshing the main memory having a dynamic random access memory interface and having a function of refreshing the main memory. In a system having a plurality of processors, means for indicating that each of the processors is a master that refreshes the main memory is provided, and a master that refreshes the main memory among the plurality of processors is different from a first processor from a first processor. When transferring to a second processor which is a processor, the first processor
Processor passes the refresh master to the second processor through means indicating that it is the master that refreshes the main memory, after which the second processor initiates a refresh, and the first processor and the second processor A refresh transfer method for a dynamic random access memory, wherein a processor refreshes different addresses of the main memory at the same time.

Action Each processor is provided with a means for indicating that it is a master for refreshing the main memory, which is a DRAM, thereby indicating that each processor is a master for refreshing.

When transferring the refresh master of the DRAM, the master of the refresh is transferred to the second processor through the means for indicating that the first processor of the original refresh is the master of refreshing the main memory, and then the second processor is transferred to the second processor. Starts refreshing, and the first processor and the second processor simultaneously refresh different addresses of the main memory, respectively, thereby preventing a refresh cycle exceeding the specification of the DRAM from occurring. Prevent the destruction of.

Embodiment An embodiment according to the present invention is shown in FIG. After system startup, processor A2 is the only refresh master in main memory 10 created by DRAM. The processor A2, which is the master of the refresh, performs the refresh of the main memory from the start address of the main memory 10 as shown in step a of FIG. 2, and the main memory 10 as shown in step b of FIG.
Is refreshing the address with 12 is a system data bus and 14 is a system address bus.

At this time, the processor for refreshing the main memory 10 is changed from the processor A2 to the processor B2.

First, the processor A2 accesses the control register 8 of the processor that is not in the execution state and writes that the refresh master is transferred to the processor B and that the processor is in the execution state. Further, the processor A2 writes in the control register 6 that it has abandoned the refresh master itself. Thereafter, the processor A2 performs refresh until the main memory 10 is refreshed until all the words in the main memory 10 are refreshed, as shown in step b of FIG. 2, and then the refresh operation ends. On the other hand, the processor B4 starts refreshing from the head address of the main memory 10 (steps b to d in the figure).

Here, as shown in the switching timing of the refresh master in FIG. 2, since both the processor A2 and the processor B4 are refreshing different addresses of the main memory 10 for the common refresh period, there is a need for a refresh cycle exceeding the DRAM specification. To prevent data corruption. Also, the refresh operation is only a few percent of the total DRAM access and does not significantly degrade system performance by having both processors refresh main memory at the same time.

Effect of the Invention In a system including a plurality of processors, by using the method for refreshing a dynamic random access memory according to the present invention, destruction of data in a main memory including a DRAM is prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram of a processor system according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the embodiment according to the present invention, and FIG. 3 uses a dynamic random access memory as a main memory. FIG. 4 is a configuration diagram of a conventional system, FIG. 4 is a timing chart illustrating the operation of the conventional system, and FIG. 5 is another timing chart illustrating the operation of the conventional system. 2 ... processor A, 4 ... processor B, 6, 8 ... control register, 10 ... main memory, 12 ... system data bus, 14 ... system address bus.

Continuing on the front page (72) Inventor Yuji Tanigawa 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. 56) References JP-A-52-3347 (JP, A) JP-A-57-195384 (JP, A) JP-B-57-34596 (JP, B2)

Claims (4)

(57) [Claims] 1. A system comprising: a main memory comprising a dynamic random access memory; and a plurality of processors having a dynamic random access memory interface and having a function of refreshing the main memory and sharing the main memory. Means for indicating that the master is a master for refreshing the main memory,
When transferring a master that refreshes the main memory among a plurality of processors from a first processor to a second processor that is another processor, the first processor is a master that refreshes the main memory. Passing a refresh master to the second processor through the means shown, after which the second processor initiates a refresh, wherein the first processor and the second processor each simultaneously refresh a different address of the main memory. A method for delivering and receiving a refresh of a dynamic random access memory. 2. The method according to claim 1, wherein the first processor refreshes the main memory when transferring a master that refreshes the main memory among the plurality of processors from the first processor to a second processor that is another processor. Passing the master of refresh to the second processor through means indicating the master and relinquishing the master of refresh of the main memory, after which the first processor refreshes all the words of the main memory only once And the second processor starts refreshing, and the first processor and the second processor respectively refresh different addresses of the main memory at the same time.
2. The method of delivering a refresh of a dynamic random access memory according to item 1. 3. A means for indicating a master for refreshing the main memory is a control register provided in each processor, and the master for refreshing the main memory is not in an execution state from the first processor in operation. When transferring to another processor, the second processor, the first processor accesses a control register of the second processor, passes a refresh master to the second processor, and enters an execution state. And the first processor relinquishes the master of the main memory refresh, after which the first processor refreshes all the words of the main memory only once, and the second processor refreshes the main memory. Starting, the first processor and the second processor each simultaneously store different addresses in the main memory. Dynamic random access memory refresh delivery method according to claim 1 or claim 2, characterized in that fresh. 4. The method according to claim 1, wherein the number of processors is two.