JP2597992B2 - Character code character data conversion circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a character code character data conversion circuit used for a dot matrix type display or the like.

(Conventional technology) A character code character data conversion circuit is a circuit for converting a character code into character data, and displays alphanumeric characters, kanji, and the like based on the converted character data. As character codes,
There are 7-bit ASCII code, 8-bit ISO code, and 16-bit JIS code (JIS Kanji code).

Conventionally, as a technique in such a field, for example, there is a technique as shown in FIG. Hereinafter, the configuration will be described with reference to the drawings.

FIG. 2 is a block diagram showing a configuration example of a conventional character code character data conversion circuit. This conversion circuit is for performing alphanumeric display of character data of 5 × 7 dots with an 8-bit character code. FIG. 3 shows the correspondence between 8-bit character codes and character patterns.

The character code character data conversion circuit of FIG. 2 includes a display data memory (hereinafter, referred to as display data RAM) 1, a read-only character generator memory (hereinafter, character generator ROM) 2, and a timing generator 3, which can be read and written at any time. It is configured.

The display data RAM 1 is a memory that stores display data represented by an 8-bit character code shown in FIG. 3 and outputs it as an 8-bit character code signal S1. The timing generator 3 is a circuit for generating a vertical direction designation code (hereinafter, referred to as a scan code) signal S2 of a character composed of 4 bits (or 3 bits). The character generator ROM2 is a circuit that generates a 5-bit character data signal S3 specified by the character code signal S1 and the scan code signal S2.

Ten common drivers (DRV) 4 are connected to the output side of the timing generator 3, and five segment drivers (DRV) 5 are connected to the output side of the character generator ROM 2. The common driver 4 is connected to ten scanning lines No. 0 to No. 9 in the dot matrix display 6, and the segment driver 5 is connected to the display 6.
Are connected to the five segments No. 1 to No. 5, respectively, and the display 6 is driven by these drivers 4, 5.

In the above configuration, the 8-bit character code signal S1 output from the display data RAM1 functions as an address signal for the character generator ROM2, and is a 35-bit (5 × 7 = 35 dot) character corresponding to the output character code. The data is selected by the character generator ROM2.
Timing generator 3 to character generator
The 4-bit scan code signal S2 to the ROM 2 and the common driver 4 takes scan code (0) _H to (9) _H , and 35-bit character data selected by the character code output from the display data RAM1. From scanning line No. 0
9 is selected by the character generator ROM2, and a 5-bit character data signal S3 is output from the ROM2. Also, the scan code signal
S2 is 10 when scan code (0) _H to (9) _H
One of the common drivers 4 corresponding to the scanning lines No. 0 to No. 9 is selected. Among the ten common drivers 4, the selected common driver outputs a drive waveform,
Other common drivers output non-selected waveforms.

Next, with reference to FIGS. 4 and 5 (a) and (b), an operation in the case of displaying the character A of the character code 01000001 in FIG. 3 will be described.

First, the character code 01000001 of the character A stored in the display data RAM1 is output from the RAM1 as an 8-bit signal S1, which becomes the address of the character generator ROM2, and the 35-bit character data shown in FIG. 4 is selected. You. Next, the value of the signal S2 output from the timing generator 3 becomes the scan code (0) _H , and the signal S3 representing the 5-bit character data 01110 corresponding to the scanning line NO. Output from character generator ROM2. Then, among the five segment drivers 5, the segment drivers of the segments NO. 2, NO. 3, and NO. 4 are turned on, and the segments NO. 1, NO.
The segment driver 5 turns off. At this time, since the common driver 4 of the scanning line No. 0 outputs a driving waveform according to the signal S2 = (0) _H, FIG.
Is displayed.

Next, the signal S2 becomes (1) _H , and the display on the scanning line No. 1 is displayed as shown in FIG. Signal S2
Is incremented from (0) _H to (9) _H , the character A is displayed on the dot matrix display 6 as shown in FIG.

(Problems to be Solved by the Invention) However, the circuit having the above configuration has the following problems when displaying a specific character, for example, g, j, p, q, y.

For example, when displaying characters b and j, FIG.
As shown in (b), the dots at the lower ends of the characters b and j are displayed on the same scanning line, making the character j difficult to read. The same is true for the other characters g, p, q, y.

In order to solve the above problem, three blank portions of the lower scanning lines NO.7 to NO.9 are used in the ISO specification of FIG. 3 as in the character code 11101010 of FIG. There is a method of newly defining and displaying a character j using 5 × 7 dots or more as the character code of the definition.

However, in this method, the capacity of the character generator ROM2 is required by the number of dots of the newly defined character j. When a display and a printer are used together, even if the display uses the character code 11101010 of FIG. 3 for easy viewing, the character code 01101010 of FIG. 3 must be used at the time of printing. Then, even though the characters are the same, the display data on the display
The character code 11101010 sent to the RAM 1 is different from the character code 01101010 sent to the printer, which complicates display and printer control.

The present invention has the following problems.
An object of the present invention is to provide a character code character data conversion circuit that solves the problem that a specific character is difficult to read on a display, an extra memory capacity is required, and control is complicated.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a character code character data conversion circuit that outputs a character code for selecting character data, a memory, A circuit, an adder circuit, and an erasing circuit are provided.

Here, the memory stores a plurality of the character data constituted by predetermined dots among a plurality of dots arranged in a matrix, and scans the character data selected by the character code by sequentially incrementing the character data. , And is sequentially output in units of rows of the dots, and is constituted by a ROM or the like. The detection circuit includes g,
This circuit detects a specific character code such as j, p, q, y and outputs a detection signal. The adding circuit outputs the scan code as it is to the memory and the erasing circuit when the detection signal is not output, and adds predetermined shift data to the scan code when the detection signal is output, and This is a circuit that outputs to the erasing circuit. Further, when the scan code to which the predetermined shift data is not added is given, the erasing circuit outputs the character data output from the memory as it is, and the erasing circuit adds the predetermined shift data. When a scan code is given, the circuit outputs a constant logic level for the number of lines of the character data corresponding to the predetermined shift data, and subsequently outputs the character data.

(Operation) According to the present invention, since the character code character data conversion circuit is configured as described above, when the detection circuit detects a character code meaning a specific character such as g, j, p, q, y, The detection signal is given to the addition circuit. Then, the adder circuit adds the predetermined shift data to the scan code and gives the added value to the memory and the erase circuit. When a specific character code is detected by the detection circuit, the erasing circuit outputs a constant logical level (for example, L or H) by the number of lines of the character data corresponding to the predetermined shift data. As a result, character data indicating a specific character such as g, j, p, q, y, etc. is apparently moved (shifted) N dots downward, for example, according to the value of the shift data. Further, when a predetermined logic level is output from the erasing circuit for a predetermined number of rows, the output is prohibited from being in a floating state, and flicker on the display is eliminated. Therefore, the above problem can be eliminated.

(Embodiment) FIG. 1 is a block diagram showing the configuration of a character code character data conversion circuit showing an embodiment of the present invention. The same elements as those in FIG. 2 are designated by the same reference numerals. I have.

This character code character data conversion circuit is for displaying 5 × 7 dots, and has a circuit configuration for shifting the five characters g, j, p, q, y downward by one dot. This conversion circuit is different from the conventional one shown in FIG. 2 in that a detection circuit 10 is connected to the output side of the display data RAM 1 and an addition circuit 11 is connected to the output side of the detection circuit 10 and the output side of the timing generator 3. And the erasing circuit 12 is connected to the output side of the addition circuit 11 and the character generator ROM2.

Here, the detection circuit 10 detects whether the 8-bit character code signal S1 output from the display data RAM1 corresponds to any one of the five character codes g, j, p, q, y. The circuit outputs a detection signal S4 when the characters correspond to the five characters. The adder circuit 11 outputs the shift data (F) _H (where F = 1111) when the detection signal S4 is input, and outputs the data (O) _H when the detection signal S4 is not input, using the output of the timing generator 3. This is a circuit that adds a certain 4-bit scan code signal S2 and outputs a 4-bit signal S5 as a result of the addition.

The erasing circuit 12 inputs the 5-bit character data signal S6 of the character generator ROM2 and the addition result signal S5 of the addition circuit 11, and sets the character data signal S6 to 0000 when the addition result signal S5 is (F) _H , and A bit signal S3 is output. When the addition result signal S5 is other than (F) _H , the character data signal S6 is output.
Is output as a 5-bit signal S3 as it is, and the signal S3 is supplied to the segment driver 5.

FIG. 7 is a diagram showing a circuit configuration example of the detection circuit 10 in FIG. The detection circuit 10 includes unit detection circuits 20-1 to 20-5 for detecting character codes of characters g, j, p, q, and y, respectively.
And an OR gate 21 for calculating the logical sum of the outputs of the unit detection circuits 20-1 to 20-5.

In the detection circuit 10 of FIG. 7, a unit detection circuit 20-2 for detecting, for example, the code of the character j is configured as shown in FIG. This unit detection circuit 20-2 is connected to the inverter 30-1.
30-4 and an AND gate 31. Note that M
SB is the most significant bit and LSB is the least significant bit.

As shown in FIG. 3, since the upper 4 bits of the character code of the character j are 0110 and the lower 4 bits are 1010,
6A (H) (01101010 (B)). for that reason,
When this character code is input to the unit detection circuit 20-2,
The 0-bit portion in the character code corresponds to inverters 30-1 to 30
-4, and the logical product is obtained by the AND gate 31, so that a signal of logical 1 is output.

Thus, the unit detection circuits 20-1 to 20-5 in FIG.
Is output as a detection signal S4 through the OR gate 21 and supplied to the addition circuit 11.

FIG. 9 is a diagram showing a configuration example of the erase circuit 12 in FIG. The erasing circuit 12 includes a NAND gate 40 for negating a logical product in the 4-bit addition result signal S5,
AND gates 41-1 to 41-1 which take the logical product of the output of gate 40 and the output character data signal S6 of character generator ROM2
-5. When the addition result signal S5 is (F) _H , the output of the NAND gate 40 becomes logic 0, the respective AND gates 41-1 to 41-5 are closed, and the 5-bit output signal S3 becomes 0000.
It becomes 0. When the signal S5 is other than (F) _H , each AND gate 4
1-1 to 41-5 are opened, and the 5-bit character data signal S6 is output as it is as the signal S3.

Operations (1) and (2) for displaying a character b and a character j shifted downward by one dot as shown in FIGS. 10 (a) and (b) in the above configuration will be described.

(1) Display operation of character b When signal S1 representing character code 01100010 of character b is output from display data RAM1, this signal S1 becomes the address of character generator ROM2 and selects 35-bit character data of character b. . Next, the scan code signal S2 becomes (0) _H , which is sent from the timing generator 3 to the addition circuit 11. On the other hand, the detection circuit 10 does not output the detection signal S4 because the character code signal S1 represents the character code of b other than the five characters g, j, p, q, y. Therefore, the addition circuit 11 outputs the signal S2 = (O) by adding the data (O) _H to _H sum signal S5 = (O) _H, gives a character generator ROM2 and erase circuit 12. In the character generator ROM2, the signal S5 = (O) _H
The 5-bit character data 10000 corresponding to the scanning line No. 0 is selected from the 35-bit character data, and is output as a character data signal S6 to be given to the erasing circuit 12.

Since the signal S5 = (O) _H is input, the erasing circuit 12 outputs the character data 10000 of the signal S6 = S3, turns on the segment driver 5 of the segment No. 1 and turns on the other segment drivers. 5 is turned off. At this time, since the common driver 4 of the scanning line No. 0 outputs a driving waveform according to the signal S2 = (O) _H , the tenth line on the scanning line NO.
The display is as shown in FIG.

Next, the signal S2 becomes (1) _H , and the display on the scanning line No. 1 is displayed as shown in FIG. The character b is displayed on the dot matrix display 6 by incrementing the signal S2 from (O) _H to (9) _H in this manner.

(2) Display operation of character j A signal S1 representing the character code 01101010 of character j is output from the display data RAM1, and this signal S1 becomes the address of the character generator ROM2, and 35-bit character data of character j is selected. . Next, the timing generator 3
Outputs a signal S2 = (O) _H.

The detection circuit 10 outputs the detection signal S4 to the addition circuit 11 because the signal S1 represents the character code of j. Adder circuit
11, the detection signal S4 is output, so the signal S2 =
(O) by adding the shifted data (F) _H to _H, the signal S5 =
(F) _H. The signal S5 = (F) _H causes the erase circuit 12
A signal S3 of 00000 is output, and the segment drivers 5 corresponding to the segments No. 1 to No. 5 are turned off. At this time, since the common driver 4 of the scanning line NO.0 outputs a driving waveform due to the signal S2 = (O) _H , all dots are turned off on the scanning line NO.0 as shown in FIG. 10 (b). State.

Next, from the timing generator 3, the signal S2 =
(1) _H is output. Since the detection signal S4 has been output, the shift data (F) _H is added to the signal S2 = (1) _H in the adding circuit 11, and the addition result signal S5 = (0) _H is output. In character generator ROM2, signal S5
= (0) _H is input, and the scanning line NO.
It selects 5-bit character data 00010 corresponding to 0 and outputs its output signal S6. The erasing circuit 12 outputs the signal S5 as (0)
_{Since it is H} , the signal S6 is output as it is as the signal S3, and the segment driver 5 corresponding to the segment No. 4 is turned on, and the segment driver 5 corresponding to the segment Nos. 1, 2, 3, 5 is turned off. I do. At this time, the signal S2 =
(1) Since _H causes the common driver 4 of the scanning line NO. 1 to output a driving waveform, the scanning line NO. 1 is shown in FIG.
Is displayed.

Thus, when the signal _{S2 (0) H ~ (9} ) is incremented to _H, the signal S2 (F) addition of the _H result signal S5 is respectively _{(F) H, (0)} H ~ (8) H and Become. S2 =
When (0) _H causes the common driver 4 corresponding to the scanning line No. 0 to output a drive waveform, the signal S5 becomes (F) _H
Therefore, the signal S3 becomes 00000, and all the dots on the scanning line No. 0 are turned off. Further, when the common driver 4 corresponding to the scanning lines NO. 1 to NO. 8 outputs a driving waveform by the signal S2 (= 1 to 8) _H , the erasing circuit 12 outputs the signal S5 (= 0 to 8), respectively. 7) By _H , the character data signal S3 (= S6) corresponding to the scanning lines NO.0 to NO.7 is output, each segment driver 5 is turned on or off, and the character j shifted down by one dot is output. Dot matrix display 6
To be displayed.

 The present embodiment has the following advantages.

By adding the detecting circuit 10, the adding circuit 11, and the erasing circuit 12, the value of the signal S2 for selecting the common driver 4 and the segment data are selected when the specific characters g, j, p, q, y are displayed. The value of the signal S5 is S5 = S2−N (where N = 1),
When S5 = 0 to 1-N, the segment data is set to (00) _H
By doing so, it is possible to display a specific character shifted downward by N dots.

Further, in the present embodiment, when the detection circuit 10 detects a specific character code, the erasing circuit 12 outputs a predetermined logical level for a predetermined number of lines, so that the output can be inhibited from being in a floating state. . Therefore, the problem that a predetermined number of rows to be blanked on the dot matrix display 6 are in a floating state, and as a result, the display 6 flickers can be reliably solved.

The present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, there are the following modifications.

(I) Constant (F) _H (= −) to be added in the adding circuit 11
For example, (E) _H (= −2), (D) _H (= −3)
While changing the configuration of the erasing circuit 12 to the signal S2.
Is (O) from (E) _H (= -2) and (D) _H (= -3).
By prohibiting the transfer of the signal S6 until it becomes _H , the number of dots to be shifted can be arbitrarily selected, such as two or three. Display examples when the shift number N = 2 are shown in FIGS. 11 (a) and 11 (b).

(Ii) The character to be shifted can be arbitrarily selected by changing the character code to be detected in the detection circuit 10 to a Greek character or other lower-written characters.

(Effects of the Invention) As described above in detail, according to the present invention, when a specific character code is detected by the detection circuit, the addition circuit adds predetermined shift data to the scan code, and All indications corresponding to the added scan code are erased. Therefore, the specific character can be shifted by N dots in the predetermined direction. As a result, the character codes at the time of displaying a specific character on a display and at the time of outputting to a printer are unified to character codes conforming to ISO regulations or the like, thereby simplifying control and suppressing an increase in memory capacity.

Furthermore, in the present invention, when a specific character code is detected by the detection circuit, the erasing circuit outputs a predetermined logical level for a predetermined number of lines, so that the output can be prevented from being in a floating state. Therefore, a predetermined number of rows that should be blank on the display are floating,
As a result, the problem that the display flickers can be reliably solved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a character code character data conversion circuit showing an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a conventional character code character data conversion circuit, and FIG. Figures, 4 and 5 (a),
(B) and FIGS. 6 (a) and (b) are the character display operation diagrams of FIG. 2, FIG. 7 is a circuit diagram of the detection circuit in FIG. 1, and FIG. 8 is a unit in FIG. 9 is a circuit diagram of the detecting circuit, FIG. 9 is a circuit diagram of the erasing circuit in FIG. 1, and FIGS. 10 (a) and (b) and FIGS. 11 (a) and (b) are character display operations of FIG. FIG. 1 ... Display data RAM, 2 ... Character generator R
OM (memory), 3 …… timing generator, 10 ……
Detection circuit, 11 addition circuit, 12 deletion circuit.

Claims (1)

(57) [Claims] A means for outputting a character code for selecting character data; a plurality of character data composed of predetermined dots among a plurality of dots arranged in a matrix are stored; A memory for sequentially outputting the selected character data in units of rows of the dots in accordance with sequentially incremented scan codes, a detection circuit for detecting a specific character code among the character codes and outputting a detection signal, When the detection signal is not output, the scan code is directly output to the memory and the erasing circuit. When the detection signal is output, predetermined scan data is added to the scan code and output to the memory and the erasing circuit. An adder circuit, when the scan code to which the predetermined shift data is not added is given, The character data output from the memory is output as it is, and when the scan code to which the predetermined shift data is added is given, a fixed number of lines of the character data corresponding to the predetermined shift data are fixed. A character code character data conversion circuit, comprising: a deletion circuit that outputs a logic level and subsequently outputs the character data.