JP2586812B2 - Phase locked oscillator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked oscillator frequently used in a multiplexing device for digital transmission, and the like.
In particular, it receives an external high-speed clock signal and a low-speed clock signal synchronized with the high-speed clock signal, and outputs a high-speed clock signal and a low-speed clock signal that are phase-synchronized with the received input high-speed clock signal and input low-speed clock signal. The present invention relates to a phase locked oscillator.

[0002]

2. Description of the Related Art A digital signal multiplexing technique in digital transmission is defined as SDH, and an interface speed of a high-speed synchronous network is 155.52 Mb / s as one unit. The multiplexed data signal is processed on a frame basis, with 8 KHz being the sampling frequency of the audio signal as one frame. In this multiplex transmission technology, in order to efficiently perform signal processing between connected devices, their frequencies are strictly equal,
The frame phase is also required to be a predetermined phase. A general phase-locked oscillator includes a voltage-controlled oscillator that generates a clock signal having a frequency corresponding to a value of a given control voltage, and one phase comparator that outputs a voltage proportional to the phase difference between two input clock signals. It consists of.

When this phase-locked oscillator is applied to the above-described multiplex transmission clock, it is conceivable that the phase comparison is made by comparing the bit phase of a high-speed clock signal. However, as described above, the high-speed clock signal is 1 bit = 1.
/155.52 Mb / s = 6.4 ns, and the frames are viewed at a very short period, so that the phase comparison is very difficult. Therefore, it is conceivable to perform frame phase comparison using a low-speed clock signal. However, in a general phase-locked oscillator, the input / output clock signal
Steady-state phase error (the amount that remains steady in a phase-synchronous state)
(E.g. , phase difference ) φ _e , input / output phase difference ω _m when not controlled , and loop gain α have the following relationship (JP-A-2-127817).
Gazette) . φ _e = ω _m / α (1) As can be seen from this equation, the stationary phase error of the phase locked oscillator is
In order to reduce the difference phi _e is to increase the loop gain α
Need to be That is, in order to compare the clock signal at a frame rate of 8 KHz per frame, the stationary phase error φ _e
Must be set to tens of thousands of times in order to reduce, and it is practically impossible to achieve this.

As a method for solving this problem, there is known a phase locked oscillator using two phase comparators as shown in FIG. In this phase-locked oscillator, a high-speed clock signal f1 (see FIG. 2A) having a period t from the outside is given to a high-speed clock input terminal 2 and the input high-speed clock signal f1 is supplied to a first phase comparator 6 Given to. The low-speed clock input terminal 1 has a high-speed clock signal f1
External low-speed clock signal f2 with period T synchronized with
2 (see FIG. 2B), and the input low-speed clock signal f2 is supplied to the second phase comparator 8. The voltage-controlled oscillator 5 outputs a high-speed clock signal f3 (see FIG. 2C) having a frequency corresponding to the value of the applied control voltage, and the high-speed clock signal f3 is supplied to the first phase comparator 6 and the frequency divider. 7 given. The frequency divider 7 divides the frequency of the input high-speed clock signal f3 and generates a low-speed clock signal f4 (FIG. 2D).
And output it. The low-speed clock signal f4 output from the frequency divider 7 is supplied to the second phase comparator 8.

The first phase comparator 6 compares the phase of the external high-speed clock signal f 1 with the phase of the high-speed clock signal f 3 from the voltage controlled oscillator 5. The phase comparator 6 includes, for example, a D flip-flop (D-F) with set and reset.
F), and outputs a voltage value corresponding to the phase difference as a continuous value within a range in which the phase changes. The second phase comparator 8 is
The phase comparison between the external low-speed clock signal f2 and the low-speed clock signal f4 from the frequency divider 7 is performed. Similarly to the first phase comparator 6, the second phase comparator 8 is constituted by, for example, a D-FF with set and reset, and outputs a voltage value according to the phase difference as a continuous value within a range in which the phase changes. I do.

[0006] The output of the second phase comparator 8 is integrated by an integrator 9 and supplied to a voltage adder 10 as an average voltage. The output of the first phase comparator 6 is also provided to the voltage adder 10. The voltage adder 10 adds the input voltages and supplies the result of the addition to the voltage controlled oscillator 5 as a control voltage. The voltage-controlled oscillator 5 outputs a high-speed clock signal f3 having a frequency corresponding to the value of the control voltage from the voltage adder 10.
Is output. With the above configuration, the high-speed clock signal f3
Controls the output phase of the low-speed clock signal f4, and controls the output phase of the high-speed clock signal f3 by comparing the phases of the high-speed clock signals f1 and f3 and the phase of the low-speed clock signals f2 and f4. Practically, it is possible to solve a part where the bit phase comparison and the frame phase comparison are difficult.

[0007]

However, in such a conventional phase-locked oscillator, a voltage obtained by comparing the phases of the high-speed clock signals f1 and f3 and a voltage obtained by comparing the phases of the low-speed clock signals f2 and f4 are used. Adder 1
0, the high-speed clock signal f1
Even when the phase comparison between the low-speed clock signals f2 and f4 is performed, the result of the phase comparison between the low-speed clock signals f2 and f4 is always supplied to the voltage adder 10. Therefore, even when the phase comparison characteristic of only the high-speed clock signal is required, the jitter due to the unnecessary low-speed clock signal is included. As described above, since the frequency of the low-speed clock signal is much lower than that of the high-speed clock signal, it is also difficult to remove this low-frequency component by a loop filter. Therefore,
In the phase-locked oscillator shown in FIG. 4, a low-frequency component obtained by comparing the phases of the low-speed clock signals f2 and f4 with the high-speed clock signal f3 output from the voltage-controlled oscillator 5 becomes jitter (low-frequency jitter). There was a drawback that it would appear.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a phase-locked oscillator that does not cause low-frequency jitter in a high-speed clock signal output from a voltage-controlled oscillator. It is in.

[0009]

In order to achieve the above object, the present invention is to receive a high-speed clock signal from the outside and a low-speed clock signal synchronized with the high-speed clock signal, and receive the input signal. A phase-locked oscillator that outputs a high-speed clock signal and a low-speed clock signal that are phase-synchronized with a high-speed clock signal and an input low-speed clock signal; A frequency divider that converts a high-speed clock signal output from the voltage-controlled oscillator into a low-speed clock signal and outputs the same, and a trailing edge of a pulse train of the low-speed clock signal output from the frequency divider outputs a high-speed clock signal output from the voltage-controlled oscillator. A pulse width conversion circuit that alternately increases and decreases by one-half cycle and outputs the pulse width; With the leading edge of the pulse train of the input low speed clock signal phases of the click signal and the input low-speed clock signal
If the phase difference is negative, the first voltage value V1
If the phase difference is positive, the second voltage value V2 (V1 <
V2) , an integrator that integrates the output of the second phase comparator and outputs an average voltage VX , and a second phase comparator that outputs the average voltage VX according to the average voltage VX output by the integrator.
The average voltage VX is V0 (V0 = (V1 + V2) / 2) and V0.
2 or higher (VA <V
X), the digital signal corresponding to [1, 0] is
The comparison voltage set when the average voltage VX is set between V0 and V1.
If the pressure is equal to or lower than VB (VX <VB), the value becomes [0, 1].
A digital signal whose average voltage VX is between VB and VA.
A voltage determination circuit that outputs a daisy <br/> Tal signal to be if [0,0] it is in (VB ≦ VX ≦ VA), according to the digital signal output of the voltage determining circuit, the digital signal
Is [1,0], pass only the input high-speed clock signal
If the digital signal is [0, 1],
Only the high-speed clock signal from the
If the digital signal is [0,0], input high-speed clock
High speed clock signal from signal and voltage controlled oscillator
A gate circuit which Ru was bulk, input high through the gate circuit
When only the fast clock signal is given, the phase comparison result
Set to “1” and the high-speed clock signal from the voltage-controlled oscillator
Is given, the phase comparison result is set to "-1",
High-speed clock signal and high-speed clock
It is obtained by a first phase comparator for outputting a voltage both clocks corresponding to the phase difference given Erareru and both lock signal as a control voltage.

[0010]

Therefore, according to the present invention, the high-speed clock signal (f3) having a frequency corresponding to the value of the control voltage is output from the voltage controlled oscillator. This high-speed clock signal (f3)
Is supplied to a frequency divider, converted into a low-speed clock signal (f4), and supplied to a pulse width conversion circuit. The pulse width conversion circuit alternately increases or decreases the trailing edge of the pulse train of the low-speed clock signal (f4) from the frequency divider by a half cycle of the high-speed clock signal output from the voltage-controlled oscillator, The low-speed clock signal (f5) is supplied to the second phase comparator. The second phase comparator, the input phases of the low-speed clock signal from the pulse width converter circuit (f5) and the input low-speed clock signal (f2)
Using the leading edge of the pulse train of the low-speed clock signal (f2)
If the phase difference is negative, the voltage value V1 is
If the phase difference is positive, a voltage value V2 (V1 <V2) is output. Output of the phase comparator is applied to the integrator. The integrator integrates the input output of the phase comparator and supplies an average voltage VX , which is the integration result, to the voltage determination circuit. The voltage determination circuit calculates the average of the average voltage VX according to the input average voltage VX.
If the voltage VX is equal to or higher than VA (VA <VX), [1, 0]
Is less than VB (VX <VB)
The digital signal of [0, 1] is applied between VB and VA.
If (VB ≦ VX ≦ VA), a digital signal of [0, 0] is supplied to the gate circuit. The gate circuit in accordance with the digital signal from the voltage judging circuit, the digital
If the signal is [1,0], only the input high-speed clock signal
Pass, and if [0, 1], the high
Pass only the fast clock signal, and enter if it is [0,0].
High-speed clock signal and high-speed clock
The lock signal is passed and supplied to the first phase comparator. The first phase comparator receives only the input high-speed clock signal.
The phase comparison result is set to "1" and the voltage controlled oscillator
Given only the high-speed clock signal from the
The comparison result is "-1", and the input high-speed clock signal and power
Both clocks of the high-speed clock signal from the pressure-controlled oscillator
Then, a voltage corresponding to the phase difference between the two is supplied to the voltage controlled oscillator as a control voltage.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail based on embodiments. FIG. 1 is a block diagram of a phase locked oscillator according to an embodiment of the present invention. 4, the same reference numerals as those in FIG. 4 denote the same or equivalent components, and a description thereof will be omitted. In the present embodiment, the pulse width conversion circuit 11 is provided, and the low-speed clock signal f4 output from the frequency divider 7 (FIG.
2 (d)), the trailing edge of the pulse train (PW4) is alternately t
/ (See FIG. 2 (e)) 2 only increases or decreases, it is assumed that give it to the second phase comparator 8 as the low-speed clock signal f 5 '.

The second phase comparator 8 'compares the phase of the low-speed clock signal f2 from the outside with the phase of the low- speed clock signal f5 from the pulse width conversion circuit 11 by the pulse of the low- speed clock signal f2.
Are compared using the leading edge of the row of signals (PW2), and binary voltages (binary signals) V1 and V2 (V1 <V
2: If the phase difference is positive, V2 is output, and if negative, V1) is output. The second phase comparator 8 'is composed of, for example, a D-FF. The result of the phase comparison of the second phase comparator 8 ' (signal
The signal f6) is integrated by the integrator 9.

That is, the phase comparator 8 'operates at a low speed clock.
If the phase difference between the lock signals f2 and f4 is "+ t / 2" or more
If V2 (see FIGS. 2 (g) to (i)), "-t / 2"
If it is below, V1 is output (see FIGS. 2 (j) to (l)).
See). The phase difference between f2 and f4 is "-t / 2 to + t / 2"
Within this range, the voltages of V2 and V1 alternately appear in the cycle 2T.
(See FIGS. 2D to 2F). did
Therefore, the integrator 9 outputs the low-speed clock signals f2 and f4.
If the phase difference is “+ t / 2” or more, V2 is changed to “−t /
2 "or less, V1 is within" -t / 2 to + t / 2 "
Then, (V2 + V1) / 2 = V0 is output. The output of the integrator 9 is provided to the voltage determination circuit 12. The voltage determination circuit 12 outputs three different digital signals depending on the input voltage value.

That is, the comparison voltage V is applied between V0 and V2.
Assuming that A is a comparison voltage VB between V0 and V1 and a voltage from the integrator 9 is VX, the voltage determination circuit 12
If VA <VX, the digital signal that becomes [1, 0]
A digital signal of [0, 0] is output if VB ≦ VX ≦ VA, and a digital signal of [0, 1] is output if VX <VB. The gate circuit 13 is supplied with a high-speed clock signal f1 from the outside and a high-speed clock signal f3 from the voltage-controlled oscillator 5, and receives a digital signal from the voltage determination circuit 12
The passage of the high-speed clock signals f1 and f3 is restricted.

The gate circuit 13 has, for example, a two-input Ex-
The first OR circuit is composed of two OR (exclusive OR) circuits.
The high-speed clock signal f1 is input to the circuit, the high-speed clock signal f3 is input to the second OR circuit, and the digital signal from the voltage determination circuit 12 is input to each OR circuit. Restrict passage as follows: That is, the digital signal is [1,
0], only f1 is passed. If the digital signal is [0, 0], f1 and f3 are passed. If the digital signal is [0, 1], only f3 is passed.

The high-speed clock signal f1 that has passed through the gate circuit 13 is supplied to the first phase comparator 6. The first phase comparator 6 sets the phase comparison result to “1” when only the high-speed clock signal f1 is supplied, and sets the phase comparison result to “−1” when only the high-speed clock signal f3 is supplied.
When both high-speed clock signals f1 and f3 are supplied, a voltage corresponding to the phase difference between f1 and f3 is supplied to the voltage-controlled oscillator 5 as a control voltage.

Accordingly, in this configuration, the phase comparison characteristic for determining the control voltage of the voltage controlled oscillator 5 is as shown in FIG.
The phase difference between f2 and f4 is "-1" between "-T / 2 to -t / 2", "1" between " + t / 2 to + T / 2", and "-t / 2 + t / 2 ”, the first phase comparator 6
Will be performed.

According to the above configuration, for the low-speed clock signal, the phase comparison with the high-speed clock signal is performed by the first phase comparator 6, so that the control of the phase correction by the phase synchronization of the high-speed clock signal can be used. Thus, a clock signal with little phase fluctuation can be output. Further, with respect to the high-speed clock signal, the phase comparison of the low-speed clock signal is performed by the second phase comparator 8 ′. The comparison result is obtained by the voltage determination circuit 12 and the gate circuit 13 by the first phase comparator 6 ′. Since the low-speed clock signal is processed before input to the high-speed clock signal, the low-speed clock signal does not affect the high-speed clock signal output from the voltage-controlled oscillator 5 as jitter. Therefore, the low-speed clock signal f4 and the high-speed clock signal f3 with little phase fluctuation are output from the low-speed clock output terminal 3 and the high-speed clock output terminal 4.

[0019]

As is apparent from the above description, according to the present invention, only the phase comparison of the high-speed clock signal is performed, and there is essentially no low-speed clock signal component. Low-frequency jitter does not occur in the high-speed clock signal, and a low-speed clock signal and a high-speed clock signal with little phase fluctuation can be output.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a phase locked oscillator according to the present invention.

FIG. 2 is a time chart of each signal for explaining the operation of the phase locked oscillator.

FIG. 3 is a diagram showing phase comparison characteristics in the phase locked oscillator.

FIG. 4 is a block diagram showing a conventional phase locked oscillator.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 low-speed clock input terminal 2 high-speed clock input terminal 3 low-speed clock output terminal 4 high-speed clock output terminal 5 voltage-controlled oscillator 6 first phase comparator 7 frequency divider 8 ′ second phase comparator 9 integrator 11 pulse width conversion Circuit 12 Voltage judgment circuit 13 Gate circuit

Claims (1)

(57) [Claims] An external high-speed clock signal and a low-speed clock signal synchronized with the high-speed clock signal are received,
In phase-locked oscillator for outputting an input high-speed clock signal and high speed clock signal synchronized in phase with the input speed clock signal and the low-speed clock signals this is received, and outputs the high-speed clock signal having a frequency corresponding to the value of the given example is a control voltage A voltage-controlled oscillator, a frequency divider that converts a high-speed clock signal output from the voltage-controlled oscillator to a low-speed clock signal, and outputs the same. After a pulse train of the low-speed clock signal output from the frequency divider,
A pulse width conversion circuit that alternately increases and decreases edges by a half cycle of the high-speed clock signal output by the voltage-controlled oscillator, and outputs the low-speed clock signal output by the pulse width conversion circuit and the input low-speed clock signal; Phase of the input low-speed clock
Using the leading edge of the pulse train of the
If negative, the first voltage value V1 is used, and if the phase difference is positive,
For example, a second phase comparator that outputs a second voltage value V2 (V1 <V2), and an output of the second phase comparator is integrated to obtain an average voltage VX.
An integrator for outputting Te, depending on the average voltage VX to be output from the integrator, the average electrostatic its
Pressure VX is equal to V0 (V0 = (V1 + V2) / 2) and V2.
The comparison voltage VA (VA <VX) that is set between
If the digital signal becomes [1, 0], its average voltage
VX is a comparison voltage VB set between V0 and V1.
If (VX <VB), the digital value becomes [0, 1].
A signal whose average voltage VX is between VB and VA (VB ≦
A voltage determination circuit that outputs a digital signal to be if [0,0] it is in VX ≦ VA), according to the digital signal output of the voltage determining circuit, its
If the digital signal is [1,0], the input high-speed
Only the lock signal is passed, and the digital signal is
If [0, 1], the high-speed clock from the voltage controlled oscillator
And only the digital signal is passed through [0,
0], the input high-speed clock signal and the voltage
A gate circuit for high-speed clock signal Ru is passed through a from-controlled oscillator, the input high-speed clock signal only through the gate circuit
When given as much phase comparison result is "1", the electric
Only high-speed clock signal from pressure-controlled oscillator is given
And the phase comparison result as "-1", and
Clock signal and high-speed clock from the voltage controlled oscillator
A first phase comparator that outputs a voltage corresponding to a phase difference between the two clocks as the control voltage when both clocks of the signal are supplied.