JPH07135465A - Phase synchronization oscillator - Google Patents

Abstract

PURPOSE:To prevent low frequency jitter from being produced in a high speed clock signal outputted from a voltage controlled oscillator. CONSTITUTION:A high speed clock signal f3 outputted from a voltage controlled oscillator 5 is converted into a low spied clock signal f4 by a frequency divider 7 and given to a pulse width conversion circuit 11, in which the pulse width of the signal f4 is increased/decreased alternately for 1/2 period of the signal f3 and the result is given to a phase comparator 8' as a signal f5. A binary signal is outputted in response to a phase difference between the signal f5 and the input low speed clock signal f2 and provides a mean voltage VX resulting from an integrated signal to a voltage discrimination circuit 12. Then a predetermined digital signal is given to a gate circuit 13 in response to the voltage VX. The circuit 13 limits the passing of the input high speed clock signals f1, f3 in response to the given digital signal to provide the signal to a phase comparator 6. The phase comparator 6 gives a voltage in response to a phase difference of the signals f1, f3 as a control voltage to the voltage controlled oscillator 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked oscillator, which is frequently used in multiplexers in digital transmission.
In particular, it receives a high-speed clock signal from the outside and a low-speed clock signal synchronized with this high-speed clock signal, and outputs a high-speed clock signal and a low-speed clock signal phase-synchronized with the received input high-speed clock signal and input low-speed clock signal. The present invention relates to a phase locked oscillator.

[0002]

2. Description of the Related Art A digital signal multiplexing technique in digital transmission is defined as SDH, and the interface speed of a high speed synchronous network is 155.52 Mb / s as one unit. Further, the multiplexed data signal is processed in frame units with 8 KHz, which is the sampling frequency of the audio signal, as one frame. In this multiplex transmission technology, the frequencies are strictly equal in order to efficiently perform signal processing between connected devices,
The frame phase is also required to be a predetermined phase. A general phase-locked oscillator includes a voltage-controlled oscillator that generates a clock signal having a frequency corresponding to the value of a given control voltage, and one phase comparator that outputs a voltage proportional to the phase difference between two input clock signals. It is composed of

When this phase-locked oscillator is applied to the clock of the above-mentioned multiplex transmission, it can be considered that the phase comparison is performed by the bit phase comparison of the high speed clock signal. However, as described above, the high-speed clock signal has 1 bit = 1.
Since /155.52 Mb / s = 6.4 ns, which means that a frame is viewed with a very short period, it is very difficult to compare the phases. Therefore, it is conceivable to perform frame phase comparison using low-speed clock signals. However, in a general phase-locked oscillator, the clock signal input / output phase difference φ
_The following relationship is established between _e , the error frequency difference ω _m , and the loop gain α. φ _e = ω _m / α From this, in order to perform frame comparison of clock signals at 8 KHz per frame, α must be set to tens of thousands of times, which is practically impossible to realize. .

As a method for solving this, a phase locked oscillator using two phase comparators as shown in FIG. 4 is known. In this phase-locked oscillator, the high-speed clock input terminal 2 is supplied with a high-speed clock signal f1 (see FIG. 2A) from the outside, and the input high-speed clock signal f1 is supplied to the first phase comparator 6 Given to. Further, the low speed clock input terminal 1 has a high speed clock signal f1.
Low-speed clock signal f2 with period T from the outside synchronized with
(See FIG. 2B) is input, and the input low-speed clock signal f2 is given to the second phase comparator 8. The voltage controlled oscillator 5 outputs a high speed clock signal f3 (see FIG. 2 (c)) having a frequency corresponding to the value of the applied control voltage, and the high speed clock signal f3 is supplied to the first phase comparator 6 and the frequency divider. Given to 7. The frequency divider 7 divides the input high-speed clock signal f3 to generate a low-speed clock signal f4 (see FIG. 2 (d)).
(See) and output. The low-speed clock signal f4 output from the frequency divider 7 is given to the second phase comparator 8.

The first phase comparator 6 compares the phase of the high speed clock signal f1 from the outside with the high speed clock signal f3 from the voltage controlled oscillator 5. The phase comparator 6 is, for example, a D flip-flop (DF) with a set and a reset.
F), the voltage value corresponding to the phase difference is output as a continuous value in the range in which the phase changes. The second phase comparator 8 is
The phase of the low speed clock signal f2 from the outside and the low speed clock signal f4 from the frequency divider 7 are compared. Similarly to the first phase comparator 6, the second phase comparator 8 is also composed of, for example, a D-FF with a set and a reset, and outputs a voltage value corresponding to the phase difference as a continuous value within a range of phase change. To do.

The output of the second phase comparator 8 is integrated by the integrator 9 and given to the voltage adder 10 as an average voltage. The output of the first phase comparator 6 is also given to the voltage adder 10. The voltage adder 10 adds the input voltages and gives the addition result to the voltage controlled oscillator 5 as a control voltage. The voltage controlled oscillator 5 has a high-speed clock signal f3 having a frequency corresponding to the value of the control voltage from the voltage adder 10.
Is output. With the above configuration, the high-speed clock signal f3
The output phase of the low-speed clock signal f4 is controlled by, and the output phase of the high-speed clock signal f3 is controlled by the phase comparison of the high-speed clock signals f1 and f3 and the phase comparison of the low-speed clock signals f2 and f4. In fact, it is possible to solve the above-mentioned difficult part of bit phase comparison and frame phase comparison.

[0007]

However, in such a conventional phase-locked oscillator, the voltage obtained by the phase comparison between the high-speed clock signals f1 and f3 and the voltage obtained by the phase comparison between the low-speed clock signals f2 and f4 are used. Adder 1
Since it is added by 0, the high-speed clock signal f1
Even when the phase comparison between the low speed clock signals f2 and f3 is performed, the result of the phase comparison between the low speed clock signals f2 and f4 is always given to the voltage adder 10. Therefore, even if the phase comparison characteristic of only the high-speed clock signal is originally required, unnecessary jitter due to the low-speed clock signal is included. As described above, the frequency of the low-speed clock signal is very low with respect to that of the high-speed clock signal, so it is difficult to remove this low-frequency component by the loop filter. Therefore,
In the phase-locked oscillator shown in FIG. 4, a low-frequency component resulting from phase comparison of the low-speed clock signals f2 and f4 with respect to the high-speed clock signal f3 output from the voltage-controlled oscillator 5 becomes jitter (low-frequency jitter). It had the drawback of appearing.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a phase-locked oscillator in which low-frequency jitter does not occur in a high-speed clock signal output from a voltage-controlled oscillator. Especially.

[0009]

In order to achieve such an object, the present invention receives a high-speed clock signal from the outside and a low-speed clock signal synchronized with this high-speed clock signal, and receives the received input. A phase-locked oscillator that outputs a high-speed clock signal and a low-speed clock signal that are phase-locked to a high-speed clock signal and an input low-speed clock signal, and a voltage-controlled oscillator that outputs a high-speed clock signal having a frequency according to the value of a control voltage applied thereto, A frequency divider that converts a high-speed clock signal output from the voltage-controlled oscillator into a low-speed clock signal and outputs it, and a pulse width of the low-speed clock signal output from this frequency divider is 1/2 of the high-speed clock signal output from the voltage-controlled oscillator. The pulse width conversion circuit that alternately increases and decreases by the period and outputs, and the low-speed clock signal output by this pulse width conversion circuit Comparing the phases of the the input low speed clock signal, a second phase comparator for outputting a binary signal according to the phase difference therebetween, and outputs the first phase comparator 2
An integrator that integrates a value signal and outputs an average voltage, a voltage determination circuit that outputs a predetermined digital signal according to the average voltage output by this integrator, and an input according to the digital signal output by this voltage determination circuit A gate circuit for limiting the passage of the high-speed clock signal and the high-speed clock signal from the voltage controlled oscillator, and 2 provided through the gate circuit.
The first phase comparator compares the phases of two high-speed clock signals and outputs a voltage corresponding to the phase difference between the two high-speed clock signals as a control voltage.

[0010]

Therefore, according to the present invention, the voltage controlled oscillator outputs the high-speed clock signal (f3) having a frequency corresponding to the value of the control voltage. This high-speed clock signal (f3)
Is applied to the frequency divider, converted into the low-speed clock signal (f4), and applied to the pulse width conversion circuit. The pulse width conversion circuit converts the pulse width of the low-speed clock signal (f4) from the frequency divider into 1 of the high-speed clock signal output from the voltage controlled oscillator.
/ 2 cycles are increased / decreased alternately, and the low-speed clock signal (f
5) is given to the second phase comparator. The second phase comparator is a low-speed clock signal (f
5) and the input low-speed clock signal (f2) are compared in phase, and a binary signal is output according to the phase difference between the two. The binary signal output from this phase comparator is given to the integrator. The integrator integrates the input binary signal and gives the average voltage as the integration result to the voltage determination circuit. The voltage determination circuit gives a predetermined digital signal to the gate circuit according to the input average voltage. The gate circuit limits the passage of the input high-speed clock signal (f1) and the high-speed clock signal (f3) from the voltage-controlled oscillator in accordance with the digital signal from the voltage determination circuit, and supplies it to the first phase comparator.
The first phase comparator compares the phases of the two high-speed clock signals (f1, f3) supplied through the gate circuit and supplies a voltage according to the phase difference between the two as a control voltage to the voltage controlled oscillator.

[0011]

EXAMPLES The present invention will now be described in detail based on examples. FIG. 1 is a block diagram of a phase locked oscillator showing an embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 4 denote the same or equivalent components, and the description thereof will be omitted. In this embodiment, the pulse width conversion circuit 11 is provided to alternately convert the pulse width of the low-speed clock signal f4 output from the frequency divider 7 into "(T + t) / 2, (T-t) / 2". , Which is supplied to the second phase comparator 8'as a low speed clock signal f5 (see FIG. 2 (e)).

The second phase comparator 8'compares the phases of the low-speed clock signal f2 from the outside and the low-speed clock signal f5 from the pulse conversion circuit 11, and according to the phase difference between them, a binary voltage. (Binary signal) V1, V2 (V1 <V2:
If the phase difference is positive, V2 is output, and if it is negative, V1) is output. The second phase comparator 8'is composed of, for example, a D-FF. The result of the phase comparison of the second phase comparator 8'is integrated by the integrator 9.

Therefore, the integrator 9 has the low-speed clock signal f
If the phase difference between 2 and f4 is “t / 2” or more, V2 is
If "-t / 2" or less, V1 is output. f2 and f4
If the phase difference with is within "-t / 2-t / 2", the second
The output signal from the phase comparator 8'of V is V2, V with a cycle of 2T.
Since the voltage f1 is a signal f6 (see FIG. 2 (f)) that appears alternately, the integrator 9 calculates the average voltage (V2 + V1) / 2 = V.
Outputs 0. The output of the integrator 9 is the voltage determination circuit 12
Given to. The voltage determination circuit 12 outputs three different digital signals depending on the input voltage value.

That is, the comparison voltage V is applied between V0 and V2.
Assuming that A is a comparison voltage VB between V0 and V1 and the voltage from the integrator 9 is VX, the voltage determination circuit 12
If VA <VX, the digital signal of [1,0] is
If VB≤VX≤VA, a digital signal of [0,0] is output, and if VX <VB, a digital signal of [0,1] is output, and this is supplied to the gate circuit 13. The gate circuit 13 is supplied with a high-speed clock signal f1 from the outside and a high-speed clock signal f3 from the voltage controlled oscillator 5, and by the digital signal from the voltage determination circuit 12,
Limit the passage of the high speed clock signals f1 and f3.

The gate circuit 13 is, for example, a 2-input Ex-
The first OR is composed of two OR (exclusive OR) circuits.
The high-speed clock signal f1 is input to the circuit, the high-speed clock signal f3 is input to the second OR circuit, and the digital signal from the voltage determination circuit 12 is input to each OR circuit. Restrict the passage as follows. That is, the digital signal is [1,
If [0], only f1 is passed, if the digital signal is [0,0], f1 and f3 are passed, and if the digital signal is [0,1], only f3 is passed.

The high-speed clock signal f1 that has passed through the gate circuit 13 is given to the first phase comparator 6. The first phase comparator 6 sets the phase comparison result to "1" when only the high-speed clock signal f1 is supplied, and sets the phase comparison result to "-1" when only the high-speed clock signal f3 is supplied.
Then, when both clocks of the high speed clock signals f1 and f3 are given, a voltage according to the phase difference between f1 and f3 is given to the voltage controlled oscillator 5 as a control voltage.

Therefore, the phase comparison characteristic for determining the control voltage of the voltage controlled oscillator 5 in this configuration is as shown in FIG.
The phase difference between 2 and f4 is "-1" between "-T / 2 and -t / 2" and "1" between "t / 2 and T / 2".
The phase comparison by the first phase comparator 6 is performed between "-t / 2 and t / 2".

With the above configuration, since the first phase comparator 6 compares the phase of the low-speed clock signal with the high-speed clock signal, it is possible to use the phase correction control by the phase synchronization of the high-speed clock signal. A clock signal with little phase fluctuation can be output. Regarding the high-speed clock signal, the phase comparison of the low-speed clock signal is performed by the second phase comparator 8 ′. The comparison result is obtained by the voltage determination circuit 12 and the gate circuit 13 by the first phase comparator 6 ′. Since the low-speed clock signal is processed before being input to, the high-speed clock signal output from the voltage-controlled oscillator 5 is prevented from being affected by the jitter. Therefore, the low-speed clock output terminal 3 and the high-speed clock output terminal 4 output the low-speed clock signal f4 and the high-speed clock signal f3 with little phase fluctuation.

[0019]

As is apparent from the above description, according to the present invention, only the phase comparison of the high speed clock signals is performed, there is essentially no low speed clock signal component, and therefore the output from the voltage controlled oscillator is performed. The high-frequency clock signal does not have low-frequency jitter, and the low-speed clock signal and the high-speed clock signal with little phase fluctuation can be output.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a phase locked oscillator according to the present invention.

FIG. 2 is a time chart of each signal for explaining the operation of this phase locked oscillator.

FIG. 3 is a diagram showing a phase comparison characteristic in this phase locked oscillator.

FIG. 4 is a block diagram showing a conventional phase locked oscillator.

[Explanation of symbols]

 1 Low-speed clock input terminal 2 High-speed clock input terminal 3 Low-speed clock output terminal 4 High-speed clock output terminal 5 Voltage controlled oscillator 6 First phase comparator 7 Frequency divider 8'Second phase comparator 9 Integrator 11 Pulse width conversion Circuit 12 Voltage determination circuit 13 Gate circuit

Claims (2)

[Claims] 1. A high-speed clock signal from the outside and a low-speed clock signal synchronized with this high-speed clock signal are received,
In this phase-locked oscillator that outputs a high-speed clock signal and a low-speed clock signal that are phase-synchronized with the received input high-speed clock signal and input low-speed clock signal, the voltage that outputs the high-speed clock signal whose frequency corresponds to the value of the applied control voltage. A controlled oscillator, a frequency divider that converts the high-speed clock signal output from this voltage-controlled oscillator into a low-speed clock signal, and outputs the pulse width of the low-speed clock signal output from this frequency divider. 1/2 of clock signal
A pulse width conversion circuit that alternately increases / decreases by the period and outputs the low-speed clock signal output from this pulse width conversion circuit and the input low-speed clock signal are compared in phase, and a binary signal is output according to the phase difference between them. , A second phase comparator for outputting, an integrator for integrating a binary signal output by the second phase comparator to output an average voltage, and a predetermined digital signal according to the average voltage output by the integrator. A voltage judging circuit that outputs a signal, a gate circuit that limits the passage of the input high-speed clock signal and the high-speed clock signal from the voltage-controlled oscillator according to the digital signal output by the voltage judging circuit, and a gate circuit that passes the gate circuit. And a first phase comparator for comparing the phases of two high-speed clock signals given as a result and outputting a voltage corresponding to the phase difference between the two as the control voltage. Phase-locked oscillator according to symptoms. 2. A high-speed clock signal from the outside and a low-speed clock signal synchronized with this high-speed clock signal are received,
In this phase-locked oscillator that outputs a high-speed clock signal and a low-speed clock signal that are phase-synchronized with the received input high-speed clock signal and input low-speed clock signal, the voltage that outputs the high-speed clock signal whose frequency corresponds to the value of the applied control voltage. A controlled oscillator, a frequency divider that converts the high-speed clock signal output from this voltage-controlled oscillator into a low-speed clock signal, and outputs the pulse width of the low-speed clock signal output from this frequency divider. 1/2 of clock signal
The pulse width conversion circuit that alternately increases / decreases by the period and outputs the low-speed clock signal output from the pulse width conversion circuit and the input low-speed clock signal are compared in phase, and if the phase difference is negative, the first A voltage value V1 of the second phase comparator which outputs a second voltage value V2 (V1 <V2) if the phase difference is positive, and an average voltage obtained by integrating the output of the second phase comparator. Depending on the integrator output as VX and the average voltage VX output by this integrator, the average voltage VX is equal to or higher than the comparison voltage VA set between V0 (V0 = (V1 + V2) / 2) and V2 ( If VA <VX), a digital signal of [1,0] is output as a comparison voltage VB whose average voltage VX is set between V0 and V1.
If the following (VX <VB), a digital signal of [0,1] is output when the average voltage VX is between VB and VA (VB ≦
If VX ≦ VA), a voltage judgment circuit that outputs a digital signal of [0,0], and if the digital signal is [1,0] depending on the digital signal output by this voltage judgment circuit, the input If only the high speed clock signal is passed and the digital signal is [0, 1], only the high speed clock signal from the voltage controlled oscillator is passed and the digital signal is [0, 1].
0], a gate circuit that allows the input high-speed clock signal and the high-speed clock signal from the voltage controlled oscillator to pass therethrough, and if only the input high-speed clock signal is supplied via this gate circuit, the phase comparison result is "1. When only the high speed clock signal from the voltage controlled oscillator is applied, the phase comparison result is set to “−1”, and both the input high speed clock signal and the high speed clock signal from the voltage controlled oscillator are applied. A phase-locked oscillator comprising: a first phase comparator that outputs a voltage corresponding to a phase difference between the two as the control voltage.