JP2586158B2 - Dynamic frequency divider - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic frequency divider operating in a high frequency range, and more particularly to a dynamic frequency divider formed on a GaAs substrate.

[Conventional technology]

2. Description of the Related Art Conventionally, in a dynamic frequency divider operating in a high frequency region such as a microwave band, development for realizing high-speed operation with a simple circuit configuration has been performed.

FIG. 2 is a circuit diagram illustrating an example of a conventional dynamic frequency divider. As shown in the figure, the dynamic frequency divider has a first transfer gate FET 12 having a gate electrode connected to an input terminal 10 on a semi-insulating GaAs substrate,
A buffer circuit 13 composed of a plurality of FETs connected between the drain electrode of the FET 12 and the output terminal 11, a source electrode connected to the output side of the buffer circuit 13, and a gate electrode connected via the input inverter 15 A second transfer gate FET 14 connected to the input terminal 10, an inverter circuit 16 including a plurality of FETs each having a drain electrode connected to the input, and an output connected to the source electrode of the first FET 12; Is formed. The first and second transfer gate FETs 12 and 14 in this frequency divider connect the inverter circuit 16 and the buffer circuit 13 and have a gate function of dividing the frequency of a clock signal or the like from the input terminal 10 and extracting it to the output terminal 11. I'm sorry.

The inverter circuit 16 outputs a signal from the input terminal 10, for example, a clock signal to the N-channel FETs 17 to 20 and the diodes 21 and 22.
The buffer circuit 13 is a circuit for extracting a clock signal or the like from an input terminal by the N-channel FETs 23 and 24 and extracting the inverted output from the output terminal 11.

[Problems to be solved by the invention]

The operation lower limit frequency in the conventional dynamic frequency divider described above is such that the potential at the drain electrode end of the first transfer gate FET 12 is set while the low-level input potential is applied to the gate electrode of the first transfer gate FET. , Depending on not being able to hold the previous high level.

FIG. 3 is a waveform chart showing a result of analysis by a computer performed by the present inventors. First transfer gate FET12
When the input signal A applied to the gate electrode changes from high level to low level, the first transfer gate
It can be seen that the potential C of the drain electrode of the FET 12 cannot maintain the initial high level, and the potential has dropped. This is because the potential C is reduced by the input signal A due to the division ratio between the input capacitance of the input FET of the buffer circuit 13 and the gate-drain capacitance of the first transfer gate FET 12. As a result, there is a drawback that the lower the capacitance ratio, the lower the lower limit frequency becomes, the closer the upper limit frequency becomes, and the narrower the dividing operation range becomes.

SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem and to provide a dynamic frequency divider having an expanded frequency dividing operation frequency range except for a deterioration of an operation lower limit frequency.

[Means for solving the problem]

An input inverter circuit for inverting an input signal from an input terminal and a first transfer gate having an output terminal connected to a gate electrode are provided.
An FET, a buffer circuit including a drain electrode of the first transfer gate FET as an input terminal and including a first source follower FET, a source electrode connected to an output terminal of the buffer circuit, and a gate electrode connected to the input terminal. A second transfer gate FET, and an inverter circuit having a drain electrode of the second transfer gate FET as an input terminal and an output terminal connected to the source electrode of the first transfer gate FET and including a second source follower FET. Is formed on a semi-insulating substrate, the gate width of the first source follower FET is made larger than the gate width of the first transfer gate FET, and 3
It is characterized in that it is formed twice or less.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a dynamic frequency divider explaining one embodiment of the present invention. In the figure, the gate width of the buffer circuit 13 other than the input (first) source follower FET 4 including the first transfer gate FET 1 and the second transfer gate FET 2 is 50 μm.

The inventors of the present invention set the gate width of the FET 4 to 50 μm, 70 μm,
The lower limit operating frequency was sequentially increased to 100 μm and 120 μm, and the lower limit operating frequency was examined by computer analysis.

As a result, the lower limit operating frequency of this frequency divider was improved from 4.5GHz to 4.3GHz, 4.0GHz, 3.8GHz. The upper limit operating frequency at this time did not change. This is because the source follower circuit 4 employed in the buffer circuit has an impedance exchange function and a high input impedance is realized, so that even if the gate width of the FET 4 is increased, the input impedance does not change much. This is because the inverter circuit also has the second source follower FET (circuit) 5, so that the inverter circuit is more resistant to load fluctuations.

The lower limit operating frequency of the frequency divider is determined by whether or not the potential of the input terminal of the buffer circuit is sufficiently held, and is affected by an input signal which is voltage-divided by the capacitance of the FETC.

The gain Ga of the source follower circuit 4 during the operation of the dynamic frequency divider of this embodiment is about 0.7. Therefore, the input capacitance of the source follower circuit 4 is approximately equal to the source follower FE
It is (1-Ga) times Cgs (gate-source capacitance) of T, that is, 0.3 Cgs. This is a source follower
Even if the gate width of the FET is tripled, the input capacitance of the source follower circuit 4 is at most 0.9 Cgs and Cgs or less, which means that the upper limit frequency is not affected.

〔The invention's effect〕

As described above, the dynamic frequency divider of the present invention focuses on the potential change at the input terminal of the buffer circuit, and increases the ratio of the gate width of the source follower FET to the first transfer gate FET of the buffer circuit. By changing, without affecting other electrical characteristics,
There is an effect that only the operation lower limit frequency is reduced, and a wide frequency division operation frequency range can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a dynamic frequency divider according to one embodiment of the present invention, FIG. 2 is a circuit diagram of an example of a conventional dynamic frequency divider, and FIG. 3 is a buffer circuit input terminal of FIG. FIG. 4 is a waveform diagram showing a temporal change of a potential. 1,2 ... Transfer gate FET, 3 ... Input FET, 4,5 ...
... source follower circuit, 10 ... frequency divider input terminal, 11 ...
Frequency divider output terminal, 12, 14,… Transfer gate FET, 13
…… Buffer circuit, 15 …… Input inverter, 16 …… Inverter circuit, V _DD , V _SS …… Voltage power supply.

Claims (1)

(57) [Claims] 1. An input inverter circuit for inverting an input signal from an input terminal, and a first transfer gate FET having an output terminal of the input inverter circuit connected to a gate electrode.
A buffer circuit including a drain electrode of the first transfer gate FET as an input terminal and including a first source follower FET; a source electrode connected to an output terminal of the buffer circuit; and a gate electrode connected to the input terminal. A second transfer gate FET and the second transfer gate E
A dynamic frequency divider having a drain electrode of the FT as an input terminal, an output terminal connected to a source electrode of the first transfer gate FET, and an inverter circuit including a second source follower FET formed on a semi-insulating substrate. , The first
Wherein the gate width of the source follower FET is larger than the gate width of the first transfer gate FET and is not more than three times the gate width of the first transfer gate FET.