JPH03206720A - Dynamic frequency divider - Google Patents

Abstract

PURPOSE:To increase only the operating upper limit frequency and to realize a wide frequency division operating frequency range by revising a gate width of a switch FET in the decreasing direction and specifying its maximum value while taking load fluctuation to a buffer circuit into consideration. CONSTITUTION:The gate width of a switch FET 3 in an inverter circuit 16 is selected larger than the gate width of a source follower FET 4 of a buffer circuit 13 and less than three times of the gate width in the dynamic frequency divider in which an input inverter circuit 15, the 1st transfer gate FET 1, the buffer circuit 13, a 2nd transfer gate FET 2 and an inverter circuit 16 are formed on a semi-insulating substrate. Thus, the dynamic frequency divider is realized, where the frequency division operating upper limit frequency is expanded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic frequency divider that operates in a high frequency region, and particularly to a dynamic frequency divider formed on a GaAs substrate.

[Conventional technology]

2. Description of the Related Art Conventionally, in a dynamic frequency divider that operates in a high frequency region such as a microwave band, development has been carried out to realize simple frequency and high-speed operation.

FIG. 3 is a circuit diagram of an example of a conventional dynamic frequency divider. This dynamic frequency divider has a first transfer gate FETI2 whose gate electrode is connected to an input terminal 10, and a plurality of FETs connected between the drain electrode of this FET 12 and an output terminal 11 on a semi-insulating GaAs substrate.
a second transfer gate FET 14 whose source electrode is connected to the output side of this buffer circuit 13 and whose gate electrode is connected to the input terminal 10 via an input inverter 15;
The train electrode of the inverter circuit 16 is connected to the input and the output thereof to the source electrode of the first FET 12, respectively, and includes a plurality of FETs. The first and second transfer gates 1-F in this frequency divider
ET1214 has an inverter circuit 16 and a buffer circuit 13
It functions as a gate to divide the frequency of the clock signal etc. from the input terminal 10 and take it out to the output terminal 11.

The inverter circuit 1 receives a signal from an input terminal 10, for example, a clock signal from N-channel FETs 17 to 20 and a diode 2.
This circuit takes out an inverted output frequency-divided by 1.22. Further, the buffer circuit 13 is a circuit that delays a clock signal etc. from the input terminal 10 using N-channel FETs 23 and 24 and takes it out from the output terminal.

[Problem to be solved by the invention]

In the conventional dynamic frequency divider described above, when a signal from low to high is applied to the gate terminal of the second transargate FET 14, the inverter circuit 16 outputs a signal from high to low, and when it outputs a signal from low to low. There are two ways to output a high signal. As the input frequency increases and approaches the upper limit frequency, in the latter case, the delay in the inverter circuit output cannot be ignored when compared with the input frequency, and in severe cases, there is a drawback that the delay is only half the period of the input signal. , which determines the upper operating frequency of the frequency divider.

The purpose of the present invention is to solve such problems, focus on the fact that the upper limit operating frequency of frequency division is the signal delay caused by the inverter circuit, improve this part, and expand the upper limit frequency of frequency division. The object of the present invention is to provide a dynamic type frequency divider.

[Means to solve the problem]

The configuration of the present invention includes an input inverter circuit that inverts an input signal from an input terminal, and a first transfer gate F whose output end of the input inverter circuit is connected to a gate electrode.
ET, a buffer circuit including a source follower FET whose input terminal is the train electrode of the first transfer FET, and a second buffer circuit whose source electrode is connected to the output terminal of the buffer circuit and whose gate electrode is connected to the input terminal. an inverter circuit including a switch FET and a source-flat lower FET, whose input terminal is the train electrode of the second transfer gate FET and whose output terminal is connected to the source electrode of the first transfer gate FET. In the dynamic frequency divider formed on an insulating substrate, the gate width of the switch FET of the inverter circuit is larger than the gate width of the source follower FET of the buffer circuit and is not more than three times that width. It is characterized by

〔Example〕

Next, the present invention will be explained using the drawings.

FIG. 1 is a circuit diagram of a dynamic frequency divider illustrating an embodiment of the present invention. In the figure, the gate widths of the first transfer gate FET1 and the second transfer gate FET2 are 50 μm, and the gate widths of the FETs of the inverter circuit 16, buffer, and circuit 13 are 70 μm.

The inventors of the present invention have discovered that the switch F of the inverter circuit 16
The gate width of ET3 is 100μm, 130μm, 160μm
The upper limit operating frequency was investigated by computer analysis by increasing the number m sequentially.

FIG. 2 is a waveform diagram showing the analysis results. As a result of this analysis, when the gate width of the FET 3 was initially 70 μm, the output of the inverter circuit 16 began to lag significantly when the input frequency reached 9.0 GHz, and stopped operating normally at 9.3 GHz.

Next, set the gate width of FET3 to 100 μm, 130 μm,
When it was set to 160 μm, the frequency at which output delay began to occur gradually shifted to the high frequency region, and the upper limit operating frequency was 9.
Improved to 5GHz, 9.7GHz, and 9.8GHz.

Note that the lower limit operating frequency at this time is determined by the first transfer gate FETI and the buffer circuit 13, and therefore does not change.

The gain Ga of the source follower FET 4 during the operation of the dynamic frequency divider of this embodiment is approximately 0.7. Therefore,
The input capacitance of this source follower 4 is approximately (1) of Cgs (gate-source capacitance) of the source follower FET.
-Ga) times, that is, 0.3Cgs. This means that even if the gate width of the source follower FET is tripled, the input requirement of the source follower circuit 4 is at most 0.9 Cg.
s and Cgs or less, meaning that it does not affect the upper limit frequency.

〔Effect of the invention〕

As explained above, the dynamic frequency divider of the present invention focuses on the phase delay of the output signal of the switch FET of the inverter circuit, changes the gate width of the switch FET to a larger value, and reduces the load on the buffer circuit. By taking fluctuations into account and defining the maximum value, only the upper limit operating frequency can be raised without affecting other electrical characteristics, and a wide divided operating frequency range can be realized.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a dynamic type frequency divider explaining one embodiment of the present invention, Fig. 2 is a waveform diagram showing the results of computer analysis of the operation shown in Fig. 1, and Fig. 3 is a conventional dynamic type frequency divider. FIG. 2 is a block diagram of an example of a frequency divider. 1.2... Transargate FET, 3... Switch FET, 4, 5... Source follower FET, 10
...Frequency divider input terminal, 11...Frequency divider output terminal, 1
3... Buffer circuit, 15... Input inverter, 1
6... Inverter circuit, VDD, VSS... Voltage power supply.

Claims (1)

[Claims] an input inverter circuit that inverts an input signal from an input terminal; a first transfer gate FET in which an output terminal of the input inverter circuit is connected to a gate electrode;
a buffer circuit including a source follower FET whose input terminal is the drain electrode of the transfer gate FET; a second transfer gate FET whose source electrode is connected to the output terminal of the buffer circuit and whose gate electrode is connected to the input terminal; An inverter circuit including a switch FET and a source follower FET is formed on a semi-insulating substrate, with the drain electrode of the second transfer gate FET being an input terminal and the output terminal being connected to the source electrode of the first transfer gate FET. In the dynamic type frequency divider, the gate width of the switch FET of the inverter circuit is larger than the gate width of the source follower FET of the buffer circuit, and is less than three times the gate width of the source follower FET of the buffer circuit. Peripheral organs.