JP2584082B2 - High-speed interrupt processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor or microcomputer having a multi-register file structure, in which interrupt processing is assigned to a register file dedicated to interrupt processing or is not currently used. By assigning each interrupt factor to a register file, it is possible to push the stack,
The present invention relates to a high-speed interrupt device capable of realizing a high-speed response without a pop operation.

2. Description of the Related Art Conventionally, when processing an interrupt in a microprocessor or microcomputer having a multi-register file configuration, a register file for interrupt processing is provided, and interrupt processing is concentrated on the register file.

According to this method, the interrupt factor received first is processed without data push, so that it is possible to respond at high speed. However, the interrupt factor received thereafter is interrupted. Despite being accepted due to high priority, there was a data push or pop operation, and it was not possible to respond at high speed.

Although a method of providing a dedicated processing register for a part of the interrupt factor has been considered, since the priority of the interrupt varies depending on the user program, it has not been satisfactory for a general-purpose use method.

An object of the present invention is to solve the above-mentioned conventional problems, and to provide a high-speed interrupt processing device that realizes a high-speed response to an interrupt factor that requires high-speed processing and can universally respond to a user program. I have.

Means for Solving the Problems In order to solve this problem, a high-speed interrupt device of the present invention performs interrupt processing using a register file dedicated to interrupt processing or an empty register file in a microprocessor or microcomputer having a multi-register file configuration. In addition, it is configured such that it is possible to arbitrarily specify which register file is to be processed for each interrupt factor.

Operation With this configuration, it is possible to improve responsiveness to an interrupt factor requiring a high-speed interrupt response and to realize general-purpose hardware.

Examples Hereinafter, examples of the present invention will be described.

FIG. 1 shows an embodiment of a high-speed interrupt processing apparatus for designating a processing register file when an interrupt occurs according to the present invention.

In a microprocessor or a microcomputer having a multi-register file structure, register files 1 to 5 (hereinafter referred to as banks) are arbitrarily assigned to a normal task or an interrupt task by a user program. When allocating a bank for interrupt processing, a bank number is specified by a user program in a register 10 for specifying a bank for performing interrupt processing for each interrupt factor in a register file selection unit 6 (hereinafter, bank selection unit). Although FIG. 1 shows the registers for designating the processing banks of the interrupt factors 1 to 4, the number of registers is prepared by the number of interrupt factors. When an interrupt acknowledgment signal for identifying an interrupt factor is generated from the interrupt unit 7, the bank selecting unit 6 receives the signal, recognizes the interrupt factor, and selects a bank to be processed. For interrupt factors with a high interrupt priority, specify in the processing bank specification register 10 for each interrupt factor so that the interrupt processing bank is dedicated. For interrupt factors with a low priority, one bank is assigned with multiple interrupt factors. Specify to share. By not assigning a normal task to the bank that processes the interrupt factor with high priority, it becomes a completely dedicated bank for interrupt processing, and the micro ROM (not shown) pushes and pops data when an interrupt occurs. Instead, interrupt processing can be started immediately, and system responsiveness is improved.

FIG. 2 shows an embodiment of a high-speed interrupt processing apparatus according to the present invention which allocates processing to an empty register file or a register file currently being processed when an interrupt occurs.

The bank selection unit 8 includes an execution history register 9 for ascertaining the bank number currently operating as a system, and executing an interrupt process for each interrupt factor in an empty bank, or
It is composed of a priority specification register 11 for each interrupt factor, which specifies whether to execute the task in the currently executing bank. In the execution history register 9, "1" is set by hardware at a bit position corresponding to the bank to which the task is currently assigned. In the priority designation register 11 for each interrupt factor, "1" is set for a high priority interrupt according to whether or not it is necessary to respond at a high speed when an interrupt occurs for each interrupt factor by a user program. In FIG. 2, bits of this register are prepared for interrupt factors 1 to 4, but this register is prepared for all interrupt factors. When an interrupt acknowledgment signal capable of identifying an interrupt cause is generated from the interrupt unit 7, the bank selection unit 8 checks the contents of the priority designation register 11 for each interrupt cause and determines whether or not to perform an interrupt process in an empty bank. When interrupt processing is performed in an empty bank, the contents of the execution history register 9 are checked to find an empty bank from the bank numbers that are not movable, and the interrupt processing is assigned to the empty bank found. By assigning the interrupt processing that needs to be performed at high speed to an empty bank, the flexibility of the system is increased and the burden on the operating system is reduced. Since the interrupt processing assigned to the empty bank is performed in the dedicated bank, the interrupt response can be performed at high speed without data push and pop.

Advantageous Effects of the Invention As described above, according to the present invention, it is possible to avoid data push and pop with respect to an interrupt factor requiring high-speed response, and realize high-speed response of interrupt processing. The throughput of the normal processing can be improved. Further, since the processing register file is selected by hardware, the load on software can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention for designating a processing register file when an interrupt occurs, and FIG. 2 is an example of assigning processing to an empty register file or a register file currently being processed by a task when an interrupt occurs according to the present invention. It is a block diagram of an example. 1 to 5: register file (bank), 6, 8: register file selection section (bank selection section), 7: interrupt section, 9: execution history register, 10: processing bank designation register for each interrupt factor, 11 ... Priority designation register for each interrupt factor.

Claims (1)

(57) [Claims] 1. A high-speed interrupt processing apparatus in a multi-register file system comprising a plurality of banks, wherein a bank selection unit includes an execution history register for ascertaining a bank number currently operating as a system; A priority specification register for each interrupt factor for specifying whether to execute an interrupt process in an empty bank for each factor or in a bank currently executing a task, and when an interrupt acceptance signal is generated, the bank selection unit By checking the contents of the priority specification register for each interrupt factor, it is determined whether or not to execute an interrupt process in an empty bank. When performing an interrupt process in an empty bank, the contents of the execution history register are searched for an empty bank. A high-speed interrupt processing device, wherein an interrupt process is assigned to the empty bank.