JP2583702B2 - Manufacturing method of printed wiring board - Google Patents

Manufacturing method of printed wiring board

Info

Publication number
JP2583702B2
JP2583702B2 JP3252843A JP25284391A JP2583702B2 JP 2583702 B2 JP2583702 B2 JP 2583702B2 JP 3252843 A JP3252843 A JP 3252843A JP 25284391 A JP25284391 A JP 25284391A JP 2583702 B2 JP2583702 B2 JP 2583702B2
Authority
JP
Japan
Prior art keywords
solder resist
clearance
printed wiring
substrate
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP3252843A
Other languages
Japanese (ja)
Other versions
JPH0567853A (en
Inventor
英俊 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3252843A priority Critical patent/JP2583702B2/en
Publication of JPH0567853A publication Critical patent/JPH0567853A/en
Application granted granted Critical
Publication of JP2583702B2 publication Critical patent/JP2583702B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0073Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
    • H05K3/0082Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces characterised by the exposure method of radiation-sensitive masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks

Landscapes

  • Structure Of Printed Boards (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明はプリント配線板の製造
方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of printed wiring boards.
It is about the method .

【0002】[0002]

【従来の技術】図4,図5は従来のプリント配線板を示
す平面図、側面断面図であり、図において、6は基板、
1は基板6の第1の面に設けられた自動装着認識用ター
ゲットマーク(以下、単にマークと言う)、2は基板6
の両面(上記第1の面及びこの第1の面と反対側の第2
の面)に設けられた紫外線露光タイプのソルダレジスト
2aは上記マーク1の周囲に設けられたソルダレジスト
の無いクリアランス部、3はVカット線、4はVカット
線3から切断される捨て板部である。
2. Description of the Related Art FIGS. 4 and 5 are a plan view and a side sectional view, respectively, showing a conventional printed wiring board.
Reference numeral 1 denotes a target mark for automatic mounting recognition (hereinafter simply referred to as a mark) provided on a first surface of the substrate 6, and 2 denotes a substrate 6
(The first surface and the second surface opposite to the first surface)
The solder resist 2a of the ultraviolet exposure type provided on the surface (1) is a clearance portion having no solder resist provided around the mark 1, 3 is a V cut line, and 4 is a discard plate portion cut from the V cut line 3. It is.

【0003】図6は上記ソルダレジスト2の形成工程を
示す側面断面図であり、図において7a,7bは紫外線
の光源、8a,8bはソルダレジスト2をマスクする露
光用のフィルム、8cはフィルム8aに設けられ、クリ
アランス部2aをマスクするマスクパターン、2bはソ
ルダレジスト2の残留部である。
FIG. 6 is a side sectional view showing a step of forming the solder resist 2, wherein 7a and 7b are ultraviolet light sources, 8a and 8b are exposure films for masking the solder resist 2, and 8c is a film 8a. The mask pattern 2b for masking the clearance 2a is a remaining portion of the solder resist 2.

【0004】次に動作について説明する。図6(a)に
おいて、基板6の両面にソルダレジスト2を塗布した
後、基板6の上下両側にフィルム8a,8bを配し、光
源7a,7bにより両面同時露光を行う。露光後、現像
及び洗浄を行うことにより、ソルダレジスト2のマスク
パターン8cによる露光されない部分が除去される。
Next, the operation will be described. In FIG. 6A, after applying the solder resist 2 on both surfaces of the substrate 6, films 8a and 8b are arranged on both upper and lower sides of the substrate 6, and both surfaces are simultaneously exposed by the light sources 7a and 7b. After the exposure, by performing development and cleaning, a portion of the solder resist 2 that is not exposed by the mask pattern 8c is removed.

【0005】この場合、露光が適正に行われていれば、
上記マスクパターン8cにより露光されないソルダレジ
スト2が除去されて図4、図5のようにクリアランス部
2aが形成される。
In this case, if the exposure is properly performed,
The unexposed solder resist 2 is removed by the mask pattern 8c to form a clearance 2a as shown in FIGS .

【0006】これに対して上記両面同時露光を行う際、
図6(a)において、下側の光源7bの光が基板6を透
過すると、第1の面のソルダレジスト2を露光し、この
ため、図6(b)に示すようにマーク1の周囲にソルダ
レジスト2の残留部2bが形成され、上記クリアランス
部2aは形成されない。なお、マーク1は回路部品を自
動装着装置で装着を行う際の基準座標となるもので、銅
箔等から成る。また回路部品の装着後、捨て板部4はV
カット線3から切り離される。
On the other hand, when performing the double-sided simultaneous exposure,
In FIG. 6A, when the light from the lower light source 7b passes through the substrate 6, the solder resist 2 on the first surface is exposed, and therefore, as shown in FIG. The remaining portion 2b of the solder resist 2 is formed, and the clearance portion 2a is not formed. The mark 1 is a reference coordinate when the circuit component is mounted by the automatic mounting device, and is made of copper foil or the like. After the circuit components are mounted, the discard plate 4
It is cut off from the cut line 3.

【0007】[0007]

【発明が解決しようとする課題】従来のプリント配線板
のソルダレジスト2は上記の方法で形成されていたの
で、光源7a,7bにより両面同時露光を行うと、下側
の光源7bにより上側のソルダレジスト2が露光されて
しまい、クリアランス部2aを形成することができない
ことがあり、このためマーク1が不明瞭となり、自動装
着認識が困難になる等の問題点があった。
Since the solder resist 2 of the conventional printed wiring board is formed by the above-described method, when the double-sided simultaneous exposure is performed by the light sources 7a and 7b, the upper light source 7b is used by the lower light source 7b. In some cases, the resist 2 is exposed, and the clearance 2a cannot be formed. Therefore, the mark 1 becomes unclear, and there is a problem that automatic mounting recognition becomes difficult.

【0008】この発明は上記のような問題点を解決する
ためになされたもので、両面同時露光を行っても確実に
クリアランス部を形成することのできるプリント配線
の製造方法を得ることを目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and a printed wiring board capable of forming a clearance portion reliably even when two-sided simultaneous exposure is performed.
It is intended to obtain a manufacturing method of the.

【0009】[0009]

【課題を解決するための手段】この発明に係るプリント
配線板の製造方法は、基板の第1の面に自動装着認識用
ターゲットマークを設ける工程と、上記基板の上記第1
の面とは反対側の第2の面の上記自動装着認識用ターゲ
ットマークの周囲に形成すべきクリアランス部と対向す
る位置に、該クリアランス部と略同じ大きさを有し光を
マスクするパターンを形成する工程と、上記基板の上記
第1の面および上記第2の面に紫外線露光タイプのソル
ダレジストを塗布する工程と、両面同時露光を行う工程
とを備えるものである。
According to the present invention, there is provided a method of manufacturing a printed wiring board , comprising the steps of:
Providing a target mark; and forming the first mark on the substrate.
Target for automatic mounting recognition on a second surface opposite to the surface
Face the clearance to be formed around the
At a position that is approximately the same size as the clearance and has light
Forming a pattern to be masked; and
An ultraviolet exposure type solvent is provided on the first surface and the second surface.
Steps of applying resist and performing simultaneous exposure on both sides
Is provided .

【0010】[0010]

【作用】この発明に係るプリント配線板の製造方法で
は、基板の自動装着認識用ターゲットマークを形成した
第1の面とは反対側の第2の面の、自動装着認識用ター
ゲットマークの周囲に形成すべきクリアランス部と対向
する位置に、このクリアランス部と略同じ大きさを有し
光をマスクするパターンを形成しているので、両面同時
露光を行っても、第1の面に塗布されたソルダレジスト
のクリアランス部を形成すべき部分が下側の光源の光で
露光されることがないから、クリアランス部を確実に形
成することができる。
With the method for manufacturing a printed wiring board according to the present invention ,
Formed a target mark for automatic board placement recognition
An automatic mounting recognition target on a second surface opposite to the first surface;
Opposed to the clearance to be formed around the get mark
To have the same size as this clearance part
Since a pattern that masks light is formed,
Solder resist applied to the first surface even after exposure
The part where the clearance part should be formed is the light of the lower light source
Since there is no exposure, make sure the clearance
Can be achieved.

【0011】[0011]

【実施例】実施例1. 以下、この発明の一実施例を図について説明する。図1
〜3はこの発明の一実施例を示す図であり、図1〜3に
おいて、自動装着認識用ターゲットマーク1、紫外線露
光タイプのソルダレジスト2、クリアランス部2a、V
カット線3、捨て板部4、および基板6は、図4〜6に
示した従来例と同じものであるので説明を省略する。な
お、以下の説明において、自動装着認識用ターゲットマ
ークを単にマークとも言う。図1,図2において、5は
基板6の第2の面に設けられた光を遮へいするマスク用
のパターンで、銅箔等から成り、上記第2の面のクリア
ランス部2aと対向する位置に設けられ、上記マーク1
を含むクリアランス部2aと同一サイズ又は同一サイズ
より若干大きいサイズを有する。図3はソルダレジスト
2の形成工程を示す側面断面図である。
[Embodiment 1] An embodiment of the present invention will be described below with reference to the drawings. FIG.
1 to 3 are diagrams showing an embodiment of the present invention.
Target mark 1 for automatic mounting recognition, UV exposure
Optical type solder resist 2, clearance 2a, V
The cutting line 3, the discard plate 4, and the substrate 6 are shown in FIGS.
The description is omitted because it is the same as the conventional example shown. What
In the following explanation, the target
The mark is also called simply the mark. 1 and 2, reference numeral 5 denotes a mask pattern provided on the second surface of the substrate 6 for shielding light, which is made of copper foil or the like, and is located at a position facing the clearance 2a of the second surface. Provided and the above mark 1
Has the same size as or slightly larger than the same size as the clearance portion 2a. FIG. 3 is a side sectional view showing a step of forming the solder resist 2.

【0012】次に動作について説明する。図3(a)に
示すように、基板6の両面にソルダレジスト2を塗布し
た後、マーク1が設けられた基板6の上下両側に露光用
のフィルム8a,8bを配し、光源7a,7bにより両
面同時露光を行う。このとき、光源7bの光はパターン
5で遮ぎられるので、この光が基板6を透過して上側の
ソルダレジスト2が露光されることはない。光源7aの
光はフィルム8aのマスクパターン8cによりマスクさ
れて遮光されるから、基板6上側のソルダレジスト2の
マーク1の周囲は露光されない。
Next, the operation will be described. In FIG. 3 (a)
As shown, solder resist 2 is applied to both surfaces of substrate 6.
After exposure, the upper and lower sides of the substrate 6 on which the mark 1 is provided
Films 8a and 8b are arranged, and both light sources 7a and 7b are used.
Surface simultaneous exposure is performed. At this time, the light of the light source 7b is
5, this light transmits through the substrate 6 and
The solder resist 2 is not exposed. Of the light source 7a
The light is masked by the mask pattern 8c of the film 8a.
To shield the solder resist 2 from the solder resist 2 on the substrate 6
The area around the mark 1 is not exposed.

【0013】露光後、現像及び洗浄することにより、上
記マスクパターン8cでマスクされた部分のソルダレジ
スト2が除去されて、図3(b)及び図1,図2に示す
ようにクリアランス部2aが形成される。
After exposure, development and washing remove the solder resist 2 at the portion masked by the mask pattern 8c, and as shown in FIG. 3B, FIG. 1 and FIG. It is formed.

【0014】実施例2.なお、上記実施例1は両面プリ
ント配線板の捨て板部4に設けた自動装着認識用ターゲ
ットマークについて示したが、この発明は両面プリント
配線板の製品部内に設けた自動装着認識用ターゲットマ
ークについても適用できる。
Embodiment 2 FIG. Although the first embodiment shows the target mark for automatic mounting recognition provided on the discard plate portion 4 of the double-sided printed wiring board, the present invention relates to the target mark for automatic mounting recognition provided in the product part of the double-sided printed wiring board Can also be applied.

【0015】また、多層プリンタ配線板の捨て板部及び
製品部内に設けられた自動装着ターゲットマークの内層
にソルダレジストのクリアランス部と略同一サイズのマ
スク用のパターンを1層以上設けてもよい。
One or more mask patterns having substantially the same size as the clearance of the solder resist may be provided on the inner layer of the automatic mounting target mark provided in the discarded plate portion and the product portion of the multilayer printer wiring board.

【0016】[0016]

【発明の効果】以上のように、この発明によれば、プリ
ント配線板の製造方法において、基板の第1の面に自動
装着認識用ターゲットマークを設ける工程と、上記基板
の上記第1の面とは反対側の第2の面の上記自動装着認
識用ターゲットマークの周囲に形成すべきクリアランス
部と対向する位置に、該クリアランス部と略同じ大きさ
を有し光をマスクするパターンを形成する工程と、上記
基板の上記第1の面および上記第2の面に紫外線露光タ
イプのソルダレジストを塗布する工程と、両面同時露光
を行う工程とを備えるように構成したので、第1の面に
塗布されたソルダレジストのクリアランス部を形成すべ
き部分が下側の光源の光で露光されることがないから、
両面同時露光を行ってもクリアランス部を高精度に形成
できる効果がある。
As is evident from the foregoing description, according to the present invention, pre
In the method of manufacturing a printed circuit board, an automatic
Providing a target mark for mounting recognition;
The automatic mounting recognition of the second surface opposite to the first surface of the
Clearance to be formed around the recognition target mark
At the position facing the part, approximately the same size as the clearance part
Forming a pattern for masking light, comprising:
An ultraviolet light exposure tool is provided on the first surface and the second surface of the substrate.
Step of applying solder resist and simultaneous double-sided exposure
And the step of performing
Form the clearance area of the applied solder resist.
Since the exposed part is not exposed by the light of the lower light source,
Clearance is formed with high precision even when both sides are exposed simultaneously
There is an effect that can be done .

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の一実施例によるプリント配線板の自
動装着認識用ターゲットマーク部を示す平面図である。
FIG. 1 is a plan view showing a target mark part for automatic mounting recognition of a printed wiring board according to an embodiment of the present invention.

【図2】この発明の一実施例によるプリント配線板の自
動装着認識用ターゲットマーク部を示す側面断面図であ
る。
FIG. 2 is a side sectional view showing a target mark portion for automatic mounting recognition of a printed wiring board according to an embodiment of the present invention.

【図3】この発明の一実施例によるプリント配線板の自
動装着認識用ターゲットマーク部における紫外線露光タ
イプソルダレジストの形成工程を示す側面断面図であ
る。
FIG. 3 is a side sectional view showing a step of forming an ultraviolet exposure type solder resist in a target mark portion for automatic mounting recognition of a printed wiring board according to one embodiment of the present invention.

【図4】従来のプリント配線板の自動装着認識用ターゲ
ットマーク部の平面図である。
FIG. 4 is a plan view of a target mark section for automatic mounting recognition of a conventional printed wiring board.

【図5】従来のプリント配線板の自動装着認識用ターゲ
ットマーク部の側面断面図である。
FIG. 5 is a side sectional view of a target mark portion for automatic mounting recognition of a conventional printed wiring board.

【図6】従来のプリント配線板の自動装着認識ターゲッ
トマーク部における紫外線露光タイプソルダレジストの
形成工程を示す側面断面図である。
FIG. 6 is a side sectional view showing a process of forming a conventional ultraviolet exposure type solder resist at a target mark portion for automatic mounting recognition of a printed wiring board.

【符号の説明】[Explanation of symbols]

1 自動装着認識用ターゲットマーク 2 紫外線露光タイプのソルダレジスト 2a クリアランス部 5 マスク用のパターン 6 基板 DESCRIPTION OF SYMBOLS 1 Target mark for automatic mounting recognition 2 Ultraviolet exposure type solder resist 2a Clearance part 5 Pattern for mask 6 Substrate

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 基板の第1の面に自動装着認識用ターゲ
ットマークを設ける工程と、上記基板の上記第1の面と
は反対側の第2の面の上記自動装着認識用ターゲットマ
ークの周囲に形成すべきクリアランス部と対向する位置
に、該クリアランス部と略同じ大きさを有し光をマスク
するパターンを形成する工程と、上記基板の上記第1の
面および上記第2の面に紫外線露光タイプのソルダレジ
ストを塗布する工程と、両面同時露光を行う工程とを備
えたプリント配線板の製造方法。
1. A target for automatic mounting recognition on a first surface of a substrate.
Providing a set mark, and the first surface of the substrate.
Is the target mask for automatic mounting recognition on the second surface on the opposite side.
Position facing the clearance to be formed around the
A light mask having substantially the same size as the clearance portion
Forming a pattern to be formed on the substrate;
UV exposure type solder resist on the surface and the second surface
A process for applying a strike and a process for performing simultaneous exposure on both sides.
Method of manufacturing printed wiring boards.
JP3252843A 1991-09-05 1991-09-05 Manufacturing method of printed wiring board Expired - Lifetime JP2583702B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3252843A JP2583702B2 (en) 1991-09-05 1991-09-05 Manufacturing method of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3252843A JP2583702B2 (en) 1991-09-05 1991-09-05 Manufacturing method of printed wiring board

Publications (2)

Publication Number Publication Date
JPH0567853A JPH0567853A (en) 1993-03-19
JP2583702B2 true JP2583702B2 (en) 1997-02-19

Family

ID=17242960

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3252843A Expired - Lifetime JP2583702B2 (en) 1991-09-05 1991-09-05 Manufacturing method of printed wiring board

Country Status (1)

Country Link
JP (1) JP2583702B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0716087B2 (en) * 1988-08-29 1995-02-22 富士写真光機株式会社 Double sided printed circuit board

Also Published As

Publication number Publication date
JPH0567853A (en) 1993-03-19

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