JP2005217241A - Exposure system and manufacturing method of multilayer printed wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an exposure system used for manufacturing a multilayer printed wiring board capable of reducing the expansion and contraction and deformation of an alignment mark when manufacturing the printed wiring board of a multilayer structure with a build-up method, keeping the boundary part of the alignment mark clear, reducing erroneous recognition of a center position of the alignment mark, and superposing with good accuracy a circuit pattern position on the next layer with respect to a circuit pattern already formed; and to provide a manufacturing method of the multilayer printed wiring board. <P>SOLUTION: In the manufacturing method of a multilayer printed wiring board, a light shielding plate free to open and close is disposed in the vicinity just above or just under a mask mounting in the exposure system serving to form a circuit pattern. Further, the surrounding part of the alignment mark of a mask is shielded from exposure light by automatically closing a light shielding plate after the completion of alignment control upon exposure. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a multilayer printed wiring board by a build-up method in which a semiconductor element is mounted, and in particular, an exposure apparatus capable of accurately manufacturing the positional relationship between an inner layer circuit pattern and an outer layer circuit pattern and The present invention relates to a method for producing a used multilayer printed wiring board.

  In a printed wiring board having a multilayer structure, the inner layer circuit pattern between the layers must be aligned. For this reason, when a printed wiring board having a multilayer structure is manufactured by the build-up method, the pattern of the next layer is processed in accordance with the already formed inner layer pattern. That is, when the inner layer pattern is formed, a positional dimension error inevitably occurs. Conventionally, with the inner layer pattern (lower layer pattern) as a reference, the position of the outer layer pattern (next layer pattern) is aligned by the following method.

  First, in order to align the pattern of the outer layer on a part of the inner layer pattern, a reference alignment pattern is formed in advance, and the alignment pattern of the inner layer is read directly or with a backlight or the like, and the position of the alignment pattern is determined. recognize. Then, based on the recognized position, the processing is performed by adjusting the position data of the outer layer pattern. That is, this is a method of adjusting the position so that the alignment pattern of the inner layer and a predetermined location of the outer layer pattern, for example, the alignment pattern overlap (see Patent Documents 1 and 2).

The known literature is described below.
JP-A-10-61218 JP-A-11-261243

  However, in the conventional method, sufficient alignment accuracy of the inner and outer layer patterns may not be obtained. In the wiring layer material on the substrate surface, the boundary portion of the alignment pattern is blurred by a plurality of processing steps, or the surface is already roughened at the time of reading. For this reason, there are problems that the alignment pattern cannot be read and the center position of the pattern is erroneously recognized. There is also a method of creating a multilayer printed wiring board using a single alignment mark (for example, a through hole) formed by a mold, but the copper portion is exposed during resist pattern formation, and the periphery of the alignment mark during etching The copper is removed and the polyimide is exposed, and the alignment mark is exposed. From the second layer thereafter, it is necessary to perform alignment using the alignment mark. However, since polyimide has a slight water absorption, the polyimide is expanded and contracted through a subsequent wet process, and the alignment mark portion is polyimide, which causes deformation of the mark portion due to various process conveyances. In addition, since polyimide has light transparency, when the alignment mark is confirmed with transmitted light, there arises a problem that it is difficult to detect the edge of the alignment mark. As a result, the visibility of the alignment mark becomes difficult, the center position is misrecognized, there is a difference between the autoscale amount during exposure and the actual substrate expansion / contraction amount, and a deviation from the inner layer circuit pattern occurs. It was.

The present invention has been made in view of the above problems, and when a printed wiring board having a multilayer structure is manufactured by a build-up method, the expansion and contraction and deformation of the alignment mark are reduced, and the boundary portion is kept clear. An exposure apparatus used for manufacturing a multilayer printed wiring board that can reduce the misrecognition of the center position, that is, can accurately form the circuit pattern position of the next layer on the already formed circuit pattern, and To provide a method for producing a multilayer printed wiring board using the same.

  According to the first aspect of the present invention, a circuit pattern is formed by a method of manufacturing a multilayer printed wiring board in which an insulating layer and a conductor layer are laminated on a core substrate on which a circuit pattern is formed, and a circuit pattern and a via hole are formed. In an exposure apparatus, a work table on which a work substrate with an alignment mark is placed, a work table having a work substrate position sensor, an illumination light source chamber disposed so as to face directly above the work table, and an illumination light source chamber A mask exposure apparatus having an alignment control unit for adjusting a mutual position between a work table and a mask table, wherein a mask table for placing a photomask with an alignment mark is disposed at an intermediate position between the workpiece table and the work table unit A light-shielding plate that can be opened and closed is arranged immediately above or near the mask base, and alignment control is performed during exposure. After completion, by automatically closing the light shielding plate, an exposure apparatus characterized by shielding the alignment marks periphery of the mask from the exposure light.

  In the invention according to claim 2 of the present invention, the insulating layer and the conductor layer are laminated on the core substrate on which the circuit pattern is formed, the circuit pattern and the via hole are formed, and the insulating layer and the circuit pattern for lamination are alternately arranged. In the method of manufacturing a multilayer printed wiring board provided in a stacked manner, during exposure for forming a circuit pattern, a through hole in which a metal or copper conductor layer formed in the peripheral part of the work substrate in advance remains as an alignment mark. The method for producing a multilayer printed wiring board is characterized by the following.

  In the invention according to claim 3 of the present invention, during exposure for forming a circuit pattern, a light shielding plate provided in the exposure apparatus is inserted, and the resist around the alignment mark of the work substrate is not exposed, and the circuit 3. The method for producing a multilayer printed wiring board according to claim 2, wherein only the resist around the pattern is exposed to form a circuit pattern.

  The invention according to claim 4 of the present invention is the method for producing a multilayer printed wiring board according to claim 2 or 3, wherein the resist is a positive resist.

  Further, in the invention according to claim 5 of the present invention, the insulating layer and the conductor layer for stacking are narrower than the core substrate, and the through holes formed in the core substrate in advance after stacking are exposed from the surface of the work substrate. The method for producing a multilayer printed wiring board according to any one of claims 2 to 4, wherein:

  The invention according to claim 6 of the present invention is characterized in that the core substrate, the insulating layer for laminating, and the conductor layer are supplied by a long base material in the form of a film. A method for producing a multilayer printed wiring board according to claim 1.

In the method for manufacturing a multilayer printed wiring board according to the present invention, a light shielding plate is placed around the alignment mark (through hole) at the time of exposure and the periphery of the alignment mark is not exposed. Peripheral copper is not etched. Therefore, in the conductor wiring pattern of the inner layer circuit formed by sequentially stacking on the front and back of the core substrate and via forming to electrically connect the outer layer and the inner layer, copper remains in the vicinity of the alignment mark used in the second and subsequent layers. It becomes possible to align with. Therefore, compared to the method of patterning without putting a light shielding plate around the alignment mark at the time of exposure, the alignment mark is not visible and the problem of misrecognition of the mark center position caused by deformation of the polyimide around the alignment mark There is an effect that a multilayer printed wiring board corresponding to a fine wiring circuit pattern can be manufactured.

  Below, the manufacturing method of the multilayer printed wiring board by this invention is demonstrated based on the embodiment.

  FIG. 1 shows an exposure apparatus of the present invention. A work table 31 is first arranged from the lower side of the drawing. A work table 32 is disposed on the work table 31, and a work substrate to be carried in from the transfer line is placed thereon. After the exposure process, the operation of carrying it out again to the transfer line is repeated. In addition, the work substrate is in the form of a film and can be applied to a continuous production method or a single wafer production method. The work table unit is provided with a position sensor, and plays a role of visually recognizing a reference point on the work substrate and stopping at a predetermined position. The exposure apparatus of the present invention is arranged so as to face each other at a position immediately above a work substrate with alignment marks placed on the work table. An illumination light source chamber 71 is disposed on the upper side of the drawing. The illumination light source chamber part is a part in which a lamp of the illumination light source is arranged, and the irradiation light beam is formed by a lens or the like and projected toward the surface of the work substrate. Furthermore, the shutter part 72 which controls irradiation time is comprised. A mask base 41 for placing a photomask with an alignment mark is disposed immediately below the shutter portion. The alignment control unit 51 that adjusts the mutual position of the work table and the mask table serves to superimpose the alignment marks of the photomask on the basis of the alignment marks of the work substrate. The alignment control unit 51 is a part equipped with a system such as an image processing for visually recognizing the alignment light source and both alignment marks, and a part for driving the mask table or work table in the X-axis and Y-axis directions for position adjustment. It is. In the exposure apparatus of the present invention, a light shielding plate controller 33 is disposed in the vicinity of the mask table. The light shielding plate control unit 33 includes a light shielding plate 34 and has a role of moving horizontally in the direction of the optical axis parallel to the work substrate. At the time of exposure, after the alignment control is completed, the light shielding plate is automatically closed in the direction of the optical axis to shield the peripheral portion of the alignment mark of the mask from the exposure light, and then the shutter portion 72 is opened to irradiate the irradiation light. An exposure apparatus according to the present invention is characterized by performing an exposure process. Note that overall management of the exposure apparatus and the transport line is performed by the apparatus control unit 61.

  In the method for manufacturing a multilayer printed wiring board according to the present invention, first, a set of two or more alignment marks is formed on a core substrate composed of an insulating layer and a conductor layer forming a first layer circuit pattern. Next, a positive resist is applied to the entire surface of the substrate, and a first layer circuit pattern is formed using a set of alignment marks. Two alignment marks 3 are used during the first circuit pattern formation (first-layer circuit pattern formation), with the vertical direction being the substrate width direction and the horizontal direction being the substrate length direction. Thereafter, when the circuit pattern is formed twice (circuit pattern formation of the second layer), the two alignment marks 3 are used to sequentially repeat the multilayer.

Here, the first and second circuit pattern formation will be described by comparing FIG. 7 of the conventional manufacturing method and FIG. 2 of the manufacturing method of the present invention. There is no difference in the first exposure method in FIGS. 7A and 2A, and the second exposure method in FIGS. 7B and 2B is greatly different in its manufacturing method. There is. First, FIG. 8 is a view from above the core substrate on which a set of two alignment marks showing an example of the conventional printed circuit board shown in FIG. 7 is formed. As shown in FIG. 7A, it is during the first exposure, that is, when the first layer circuit pattern is formed. In the prior art, copper remains in the periphery of the alignment mark when the first layer circuit pattern is formed. The shape of the mark 3 is almost the same as that formed when the hole is formed by the mold. However, at the time of forming the second layer circuit pattern in which the laminated material 15 is laminated, the periphery of the alignment mark is exposed by irregular reflection from the surface of the metal layer and the resist is partially removed at the time of forming the first layer circuit pattern. Therefore, as shown in FIG. 7B, during the second exposure, that is, during the formation of the second-layer circuit pattern, the copper exposed from the resist layer around the alignment mark during the etching is etched, and the copper base The polyimide 16 is exposed. By passing through various processes, the shape of the alignment mark is further deformed, and there is a problem in that the accuracy of the exposure position is lowered due to erroneous recognition of the mark center position (see FIGS. 7A and 7B).

  On the other hand, in the exposure apparatus of the present invention, in order to prevent the deformation of the mark shape, a light shielding plate is inserted into the periphery of the alignment mark during exposure. FIG. 2 is a plan view from above of the core substrate on which one set of two alignment marks showing an example of the printed circuit board of the present invention is formed. The problem that the shape of the alignment mark is deformed by using the exposure apparatus of the present invention having the function of inserting the light shielding plate is solved. As shown in FIG. 2A, during the first exposure, that is, when the first layer circuit pattern is formed, in the method of the present invention, copper remains in the periphery of the alignment mark when the first layer circuit pattern is formed. The shape of the alignment mark 3 is substantially the same as that formed when a hole is formed by a mold. As shown in FIG. 2 (b), during the second exposure, that is, during the formation of the circuit pattern of the second layer, the exposure apparatus of the present invention inserts a light shielding plate around the alignment mark at the time of exposure, In order to shield or resist the resist layer of the part, the resist layer around the alignment mark is not developed, copper remains in the periphery of the alignment mark even during etching, and the shape of the alignment mark is maintained normally. The exposure position accuracy can be maintained by normally recognizing the mark center position. That is, the normal alignment mark can be used as a reference when forming the circuit patterns of the first layer and the second layer (see FIGS. 2A and 2B).

  Next, FIG. 3 is a plan view of an example for explaining the state of the photomask during exposure used in the present invention. FIG. 3A is a plan view of the photomask observed from above. In the photomask 7, in order to visually recognize the through hole alignment mark 3 of the work substrate located below, a polyimide window through which the visible light of the through hole alignment mark is transmitted is formed in the periphery of the mask alignment mark 17. At the time of alignment, alignment is performed with light having a wavelength at which the resist applied to the workpiece is not exposed. The through hole alignment mark 3 (indicated by a broken line in the figure) and the mask alignment mark 17 are completely overlapped to fix the position. Next, as shown in FIG. 3B, the light shielding plate 9 is inserted into the periphery of the alignment mark 17 during exposure. The size of the light shielding plate 9 is set to a size that can sufficiently shield the window through which the mark confirmation light passes, and the insertion position does not reach the mask circuit pattern. Next, an exposure process is performed. In the exposure process, after the alignment is completed, a light shielding plate is inserted at the time of exposure so that the second layer circuit pattern can use an alignment mark in which copper remains, and high exposure position accuracy can be achieved. Further, if necessary, the printed wiring board build-up process is repeated in the same manner to perform multilayering.

  The material and thickness of the light shielding plate 9 are not particularly limited, and the material is preferably a metal that completely shields exposure light such as iron, copper, stainless steel, and nickel. The thickness of the light shielding plate is not particularly limited.

  The shape of the alignment mark used as a positioning reference for conductor wiring pattern formation and via hole formation processing is not particularly limited, and the center portion or specific position portion of a circular shape, donut shape, square shape, well shape, etc. A shape that can be confirmed is preferred. A circular shape and a donut shape are particularly preferable.

  The method for forming the alignment mark is not particularly limited, and a photolithography method, a drilling method, and the like are conceivable.

In the photolithographic method, alignment mark formation by a photoresist, alignment mark formation by an additive method, a semi-additive method, or a subtractive method can be considered. In this method, it is possible to arbitrarily design the alignment mark shape. Further, depending on the process, the inner layer circuit wiring and the alignment mark can be formed at the same time, and there is an advantage that the number of processes can be reduced.

  As the drilling method, drilling, laser processing, punching with a mold, or the like can be considered. In this method, since the processed hole is used as an alignment mark, the shape is limited to a substantially circular shape. At this time, when a through hole is formed as an alignment mark, the same alignment mark can be confirmed from both sides of the core substrate. Therefore, when a build-up multilayer printed wiring board is formed on both sides, both sides can be easily aligned. Become. Judging from the formation accuracy of the alignment mark in particular, punching with a mold is optimal. At this time, it is desirable that a plurality of alignment marks necessary for one exposure and via hole positioning be simultaneously processed by punching using the same mold. Therefore, the through hole formed in the core substrate is formed as an alignment mark. Further, the shape and positional accuracy between alignment marks formed by simultaneous processing can be confirmed in advance by the accuracy of the mold, and can be formed with high repetitive processing accuracy.

  Further, an opening larger than the alignment mark of the core substrate is provided in the lamination film in advance, and the opening is laminated so as to coincide with the position of the alignment mark of the core substrate, and the alignment mark of the core substrate is laminated. There is also a method that allows confirmation in the opening. The same applies to the case where the multilayering process is repeated for three or more layers. In this method, the size of the film to be laminated with the base film can be made uniform, but some alignment is required at the time of lamination so that the alignment mark of the core substrate enters the opening of the film for lamination at the time of film lamination. At this time, the position of the alignment mark is not particularly limited, but is preferably outside the circuit pattern forming surface of the core substrate.

  In addition, the manufacturing method of the multilayer circuit wiring board by this invention is not limited to a sheet | seat board | substrate, It is applied also to the roll-to-roll continuous production method using a tape-shaped flexible substrate.

  In the manufacturing method in which the circuit pattern is formed on the stacked upper layers in the continuous production method, exposure and via hole processing positioning are performed based on the respective alignment marks on the core substrate.

  The range of the alignment mark can be changed according to the accuracy of the circuit wiring board to be manufactured. In the case of a high-definition circuit pattern, it can be dealt with by narrowing the processing pitch of the alignment mark.

  In via formation that electrically connects the conductor wiring pattern of the outer layer circuit and the inner layer pattern of the multilayer printed wiring board formed by stacking sequentially on the front and back of the core substrate, the alignment mark is a through-hole used when forming the circuit pattern, or Either of the alignment copper patterns formed in advance at the time of circuit formation can be used.

  An embodiment of the multilayer printed board and the manufacturing method according to the present invention will be described below with reference to the accompanying drawings.

  4, 5, and 6 are side cross-sectional views in the substrate width direction for explaining an embodiment of the method for manufacturing a multilayer printed board according to the present invention. In addition, the manufacturing method of the multilayer circuit wiring board based on this invention is not limited to a following example.

First, as shown in FIG. 4A, an alignment mark 3 that is a through hole having a diameter of 400 μmφ is formed on a substrate of polyimide 1 with a double-sided copper foil having a tape shape of 105 mm by punching using a mold. To do. The alignment marks are formed at equal intervals with a pitch of 90 mm in the length direction of the tape substrate, with two points formed at both ends of the tape-shaped substrate at an interval of 95 mm as a set. In the figure, a copper foil 2 is formed on the surface of the polyimide 1 substrate, and a copper foil 2a is formed on the back surface.

  Next, in FIG. 4B, after degreasing the polyimide substrate with double-sided copper foil, alignment is performed with reference to the alignment mark 3 formed on the edge of the substrate, and laser processing is performed from the upper surface of the substrate. A via hole 4 is formed by penetrating through the foil layer and the polyimide layer up to the boundary surface between the polyimide layer and the copper foil layer on the lower surface side.

  Next, FIG. 4 (c) shows that after the desmear treatment is performed on the inside of the via hole formed in the polyimide substrate with double-sided copper foil, electroless copper plating and electrolytic copper plating are performed to form a plating layer. After forming the conductive via 5 for electrically connecting the copper foil layer, chemical polishing is performed with a mixed solution of sulfuric acid and hydrogen peroxide solution to make the copper foil about 10 μm.

  Next, in FIG. 4D, after the positive photosensitive resin 6 is applied on both sides of the polyimide substrate with double-sided copper foil and dried, the photomask is aligned using the alignment mark 3 as a reference. However, the alignment mark confirmation light is emitted by light outside the used resist photosensitive wavelength range.

  Next, in FIG. 5A, the metal light shielding plate 9 attached to the exposure apparatus is put on the upper surface of the mask simultaneously with the end of alignment, and then the substrate is exposed.

  Next, in FIG. 5B, development is performed by dipping with a resist-dedicated developer, and an etching resist 10 is formed. After the work development, the resist remains on the alignment mark.

  Next, FIG.5 (c) removes the copper foil of an etching resist opening part by spray-spraying etching liquid through the etching resist 10 on the copper foil layer of both surfaces of the said polyimide substrate with a double-sided copper foil, and etching. After that, the etching resist is removed to form the circuit pattern 11.

  Next, FIG. 6 (a) shows the polyimide substrate with double-sided copper foil 1 having a circuit pattern formed on both sides as a core substrate, and the polyimide substrates 12 and 13 with tape-like single-sided copper foil on each side of the copper foil. Laminate through the adhesive with the side facing out. The polyimide substrate with single-sided copper foil to be laminated at this time has a width of 90 mm, and is bonded with a positional accuracy of ± 2 mm from the center in the width direction of the internal circuit wiring board so as not to cover the alignment mark 3 formed at the end of the core substrate. To. In the figure, a circuit pattern 11 is formed on the surface of polyimide 1, a circuit pattern 11a is formed on the back surface, and polyimides 12 and 12a with copper foils 13 and 13a are formed on both surfaces thereof.

  Next, FIG. 6 (b) shows vias on a single-sided copper foil-coated polyimide substrate laminated on both sides with reference to the alignment mark formed at the end of the inner layer circuit wiring board, as in the formation of the first layer circuit wiring board. The upper and lower two-layer printed wiring boards can be manufactured by performing formation and circuit formation, respectively. As described above, a multilayer printed wiring board having a four-layer structure is completed by the steps shown in FIGS.

  The present invention is not limited to the embodiments described above and shown in the drawings, and various modifications can be made without departing from the spirit of the present invention.

The printed wiring board has been described with respect to the case where the circuit pattern is two layers above and below the core substrate. However, the circuit pattern can be widely applied to a multilayer printed wiring board having three or four layers above and below the core substrate. it can.

It is a conceptual diagram explaining the exposure apparatus of this invention. It is a top view from the upper part of the core board | substrate with which 1 set of 2 alignment marks which show an example of the printed circuit board of this invention were formed. It is the top view which looked at an example of the photomask at the time of exposure used by this invention from upper direction. It is sectional drawing for demonstrating the manufacturing method of the printed circuit board of this invention. It is sectional drawing for demonstrating the manufacturing method of the printed circuit board of this invention. It is sectional drawing for demonstrating the manufacturing method of the printed circuit board of this invention. It is a top view from the upper part of a core board | substrate with which 1 set of 2 alignment marks which show an example of the printed circuit board of a prior art were formed.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Polyimide 2 ... Copper foil 3, 3a ... Alignment mark (through-hole)
4 ... Via hole 5 ... Conductive via 6 ... Photosensitive resist 7, 40 ... Photomask 8 ... Alignment confirmation light 9 ... Shading plate 10 ... Etching resist 11, 11a ... First layer circuit pattern 12, 12a ... Polyimide 13, 13a ... Copper Foil 14, 14a ... second layer circuit pattern 15 ... laminated film 16 ... polyimide 17 ... mask alignment mark 31 ... work table unit 32 ... work table 33 ... light shielding plate control unit 34 ... light shielding plate 41 ... mask table 51 ... alignment control unit 61 ... Device control unit 71 ... Illumination chamber unit 72 ... Shutter unit

Claims (6)

  In an exposure apparatus for forming a circuit pattern by a multilayer printed wiring board manufacturing method in which an insulating layer and a conductor layer are laminated on a core substrate on which a circuit pattern is formed, and a circuit pattern and a via hole are formed, a work substrate with an alignment mark is mounted. Aligning the work table with the work table and the work board position sensor to be placed, the illumination light source chamber part arranged to face the work table directly above, and the intermediate position between the illumination light source chamber part and the work table part A mask exposure apparatus having a mask table on which a photomask with a mark is placed and an alignment control unit that adjusts the mutual position of the work table and the mask table, wherein the mask exposure apparatus is directly above or near the mask table. A light-shielding plate that can be opened and closed is arranged at the time of exposure. It allows exposure apparatus characterized by shielding the alignment marks periphery of the mask from the exposure light.   A method of manufacturing a multilayer printed wiring board in which an insulating layer and a conductor layer are stacked on a core substrate on which a circuit pattern is formed, a circuit pattern and a via hole are formed, and an insulating layer and a circuit pattern for stacking are alternately stacked. In the multilayer printed wiring board, a through hole in which a metal or copper conductor layer formed in advance on the periphery of the work substrate remains as an alignment mark at the time of exposure for forming the circuit pattern. Manufacturing method.   At the time of exposure for forming the circuit pattern, the light shielding plate provided in the exposure apparatus is inserted to a predetermined position, and is not exposed to the resist around the alignment mark of the work substrate, but is exposed only to the resist around the circuit pattern. A method of manufacturing a multilayer printed wiring board according to claim 2, wherein a circuit pattern is formed.   4. The method for producing a multilayer printed wiring board according to claim 2, wherein the resist is a positive resist.   5. The insulating layer and conductor layer for lamination are narrower than the core substrate, and through holes previously formed in the core substrate are exposed from the work substrate surface even after lamination. The manufacturing method of the multilayer printed wiring board of any one of these.   The method for producing a multilayer printed wiring board according to any one of claims 2 to 5, wherein the core substrate, the insulating layer for lamination and the conductor layer are supplied by a long base material in the form of a film.

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