GB2213325A - A method of forming electrical conductors on an insulating substrate - Google Patents

A method of forming electrical conductors on an insulating substrate Download PDF

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Publication number
GB2213325A
GB2213325A GB8728372A GB8728372A GB2213325A GB 2213325 A GB2213325 A GB 2213325A GB 8728372 A GB8728372 A GB 8728372A GB 8728372 A GB8728372 A GB 8728372A GB 2213325 A GB2213325 A GB 2213325A
Authority
GB
United Kingdom
Prior art keywords
electrically conductive
areas
pattern
resist
electrical conductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB8728372A
Other versions
GB2213325B (en
GB8728372D0 (en
Inventor
Gillian Denise Kellet
Roy Charles Winter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Marconi Electronic Devices Ltd
Original Assignee
Marconi Electronic Devices Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marconi Electronic Devices Ltd filed Critical Marconi Electronic Devices Ltd
Priority to GB8728372A priority Critical patent/GB2213325B/en
Publication of GB8728372D0 publication Critical patent/GB8728372D0/en
Publication of GB2213325A publication Critical patent/GB2213325A/en
Application granted granted Critical
Publication of GB2213325B publication Critical patent/GB2213325B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

A method of forming a pattern of electrical conductors from a conductive layer on a substrate by burning away selected areas of a resist layer covering said conductive layer using a focussed laser beam (6) and then plating-up the conductive areas exposed. The plating is subsequently used as an etch resist when unwanted areas of the conductive layer are to be removed. <IMAGE>

Description

A method of forming electrical conductors The present invention relates to a method of forming electrical conductors.
In particular, although not exclusively, the invention is concerned with a method of forming patterns of electrical conductors on electrically insulating substrates for use in a tape automated bonding, or TAB, process.
In such a process each of a plurality of integrated circuits, formed on respective semiconductor chips, is first bonded so as to make a required set of electrical connections to a pattern of electrical conductors on a polyimide substrate, and the conductors of that pattern are then utilised to connect the integrated circuit to other circuits as required, for example by bonding to a further substrate such as a printed circuit board. The polyimide substrate is in the form of a tape, bearing a succession of conductor patterns to which respective ones of said integrated circuits may be bonded, and with sprocket holes along each edge, such that the indexing or positioning of the integrated circuits carried by the tape may readily be automated.
The photolithography and etching techniques which are presently used to produce the conductor patterns are subject to effects such as "wash" during photolithography and Sunder cut" during etching which limit the accuracy and definition which can be achieved.
The "wash" effect occurs during the exposure of the photoresist through the mask defining the pattern, when stray UV light from the exposure source may seep under the edges of the mask. Also the source may not produce a uniform level of exposure across the pattern.
According to one aspect of the present invention a method of forming a pattern of electrical conductors from an electrically conductive layer on a substantially electrically insulating substrate includes the steps of coating said electrically conductive layer with a resist material, removing selected areas of said resist material corresponding to said pattern by means of focussed radiation from a laser source, and plating the exposed surface of said electrically conductive layer with electrically conductive material.
The plating material may subsequently be used as an etch resist during the removal of the unwanted areas of said electrically conductive layer.
According to another aspect of the present invention a method of forming a pattern of electrical conductors on an electrically insulating substrate comprises applying over at least part of the area of said substrate a layer of electrically conductive material, coating said layer of electrically conductive material with a resist material, removing said resist material by means of focussed radiation from a laser source over areas corresponding to said pattern, said laser radiation being directed to said areas in accordance with a programme of X, Y movements defining said areas, and plating with electrically conductive material the areas of said layer of electrically conductive material from which said resist material has been removed.
The laser radiation may be directed onto said resist material through a mask corresponding to the pattern of electrical conductors to be formed. The plating material may subsequently be used as an etch resist in the removal of the unwanted areas of said layer of electrically conductive material. Said resist may be a photoresist, and this photoresist may be completely exposed prior to the removal over said areas corresponding to said pattern by means of said laser radiation.
A method of forming electrical conductors in accordance with the present invention will now be described by way of example with reference to the accompanying drawing, of which: Figure 1 shows diagrammatically a pattern of electrical conductors on a substrate, and Figure 2 shows in cross-section a part of: a pattern of electrical conductors on a substrate.
Referring first to Figure 1, in a tape automated bonding (TAB) process patterns of electrical conductors 1, referred to herein as beam leads 1, are formed on a 35mm wide film or tape 2 of polyimide material, which acts as a flexible electrically insulating substrate.
Initially the tape 2 carries a continuous strip layer of copper (not shown) from which the patterns of beam leads 1 are to be formed.
The tape 2 is provided with cutouts or windows 3, within which respective integrated circuit chips 4 may be positioned, and the inner ends of the beam leads 1 are arranged to project over these windows so as to enable electrical connection to be made to respective bonding pads (not shown) on the chips 4.
Referring now to Figure 2, once the beam lead patterns have been formed the surface of the tape is coated with a photoresist, which is then exposed all over using a UV light source. A pattern mask 5 and the tape 2 are positioned with respect to one another in a jig, and a laser source (not shown), which may for example be an Excimer laser, is then used to remove the exposed photoresist layer, through the mask 5, over areas corresponding to the pattern of conductors to be formed. It is found that the photoresist can be fully removed without charring the remaining resist or leaving organic debris at the interface between the photoresist and the copper.The focussed laser radiation, indicated by the arrows 6 directed through the mask 5, is moved over the areas of photoresist that are to be removed, in accordance with a programme of X, Y movements designed to cover the areas of resist to be removed.
The surface of the copper layer exposed by the removal of photoresist is then plated with an electrically conductive material.
If it is required that the edges of the plating be profiled, for example where bumps are required at the ends of beam leads 1 for compression bonding, the edges of the photoresist may be suitably shaped by tilting the laser beam, so that during the plating-up process the edges of the plating layer are constrained to follow the required profile.
The plating may be used subsequently as an etch resist, after the removal of the remaining photoresist.
It will be appreciated that the conductor pattern and any required profiling is defined by the programmed movement of the laser beam, permitting relaxed tolerances in the mask 5.

Claims (7)

CLAIMS.
1. A method of forming a pattern of electrical conductors from an electrically conductive layer on a substantially electrically insulating substrate including the steps of coating said electrically conductive layer with a resist material, removing selected areas of said resist material corresponding to said pattern by means of focussed radiation from a laser source, and plating the exposed surface of said electrically conductive layer with electrically conductive material.
2. A method in accordance with Claim 1 wherein the plating material is subsequently used as an etch resist during the removal of the unwanted areas of said electrically conductive layer.
3. A method of forming a pattern of electrical conductors on an electrically insulating substrate comprising applying over at least part of the area of said substrate a layer of electrically conductive material, coating said layer of electrically conductive material with a resist material, removing said resist material by means of focussed radiation from a laser source over areas corresponding to said pattern, said laser radiation being directed to said areas in accordance with a programme of X, Y movements defining said areas, and plating with electrically conductive material the areas of said layer of electrically conductive material from which said resist material has been removed.
4. A method in accordance with Claim 3 wherein said laser radiation is directed onto said resist material through a mask corresponding to the pattern of electrical conductors to be formed.
5. A method in accordance with Claim 3 or Claim 4 wherein the plating material is subsequently used as an etch resist in the removal of the unwanted areas of said layer of electrically conductive material.
6. A method in accordance with Claim 3, Claim 4 or Claim 5 wherein the resist is a photoresist, this photoresist being completely exposed prior to removal over said areas corresponding to said pattern by means of said laser radiation.
7. A method of forming electrical conductors substantially as hereinbefore described with reference to the accompanying drawing.
GB8728372A 1987-12-04 1987-12-04 A method of forming electrical conductors Expired - Fee Related GB2213325B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB8728372A GB2213325B (en) 1987-12-04 1987-12-04 A method of forming electrical conductors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8728372A GB2213325B (en) 1987-12-04 1987-12-04 A method of forming electrical conductors

Publications (3)

Publication Number Publication Date
GB8728372D0 GB8728372D0 (en) 1988-01-13
GB2213325A true GB2213325A (en) 1989-08-09
GB2213325B GB2213325B (en) 1992-01-02

Family

ID=10627985

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8728372A Expired - Fee Related GB2213325B (en) 1987-12-04 1987-12-04 A method of forming electrical conductors

Country Status (1)

Country Link
GB (1) GB2213325B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000004750A1 (en) * 1998-07-13 2000-01-27 Siemens S.A. Method for producing printed circuit boards with rough conducting structures and at least one area with fine conducting structures
DE10106399C1 (en) * 2001-02-12 2002-09-05 Siemens Ag Process for the production of circuit carriers with coarse conductor structures and at least one area with fine conductor structures

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1441781A (en) * 1972-11-30 1976-07-07 Ibm Electric circuit fabrication
EP0062300A2 (en) * 1981-04-06 1982-10-13 FRITZ WITTIG Herstellung gedruckter Schaltungen Process for making a circuit board
GB2098807A (en) * 1981-05-16 1982-11-24 Ferranti Ltd Method of making circuit elements in a film
GB2113477A (en) * 1981-12-31 1983-08-03 Hara J B O Method of producing printed circuits
GB2124037A (en) * 1982-07-19 1984-02-08 Gen Electric Co Plc Methods of forming patterns on substrates
WO1987000390A1 (en) * 1985-06-27 1987-01-15 Ncr Corporation Method of manufacturing printed circuit boards

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1441781A (en) * 1972-11-30 1976-07-07 Ibm Electric circuit fabrication
EP0062300A2 (en) * 1981-04-06 1982-10-13 FRITZ WITTIG Herstellung gedruckter Schaltungen Process for making a circuit board
GB2098807A (en) * 1981-05-16 1982-11-24 Ferranti Ltd Method of making circuit elements in a film
GB2113477A (en) * 1981-12-31 1983-08-03 Hara J B O Method of producing printed circuits
GB2124037A (en) * 1982-07-19 1984-02-08 Gen Electric Co Plc Methods of forming patterns on substrates
WO1987000390A1 (en) * 1985-06-27 1987-01-15 Ncr Corporation Method of manufacturing printed circuit boards

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000004750A1 (en) * 1998-07-13 2000-01-27 Siemens S.A. Method for producing printed circuit boards with rough conducting structures and at least one area with fine conducting structures
KR100384354B1 (en) * 1998-07-13 2003-05-22 지멘스 에스. 아. Method for producing printed circuit boards with rough conducting structures and at least one area with fine conducting structures
US6627091B1 (en) 1998-07-13 2003-09-30 Siemens Aktiengesellschaft Method for producing printed circuit boards with rough conducting structures and at least one area with fine conducting structures
DE10106399C1 (en) * 2001-02-12 2002-09-05 Siemens Ag Process for the production of circuit carriers with coarse conductor structures and at least one area with fine conductor structures
US6576402B2 (en) 2001-02-12 2003-06-10 Siemens Production & Logistics Systems Ag Method for producing wiring configurations having coarse conductor structures and at least one region having fine conductor structures

Also Published As

Publication number Publication date
GB2213325B (en) 1992-01-02
GB8728372D0 (en) 1988-01-13

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Legal Events

Date Code Title Description
732 Registration of transactions, instruments or events in the register (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19971204