JP2583602B2 - Debugging device in multiprocessor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention comprises a plurality of processors connected by a system bus each having a trace memory for storing trace information indicating a history of an execution program of the processor. The present invention relates to a debugging device in a multiprocessor system.

[Conventional technology]

FIG. 2 is a configuration diagram of a debugging device in a conventional multiprocessor system.
Is a processor composed of a CPU; 2-0 to 2-4 are trace memories provided in the processors 1-0 to 1-4 respectively; 4 is a system bus connecting the processors 1-0 to 1-4; −0 to 5-4 are the processors 1-0 to 1-
4 is a trace information output line connecting the trace memory 2 to each of the trace memories 2-0 to 2-4.

Next, the operation will be described. Each processor 1-0 to 1
Reference numeral -4 indicates that trace information indicating the history of each execution program is output to and stored in its own trace memories 2-0 to 2-4 via trace information output lines 5-0 to 5-4. When mutual trace information is stored between a plurality of processors, for example, the processor 1
−0 to the other processors 1-1 to 1-4 periodically transmit a message signal via the system bus 4, and each processor 1-1 to 1-4 sequentially receives the message signal. Then, its own trace memory 2
A synchronization signal mark indicating that the message signal has been received is written in -1 to 2-4. Thereby, each processor 1-
Mutual histories of execution programs among a plurality of processors 1-0 to 1-4 are known from synchronization signal marks included in trace information 1 to 1-4, and are used for debugging.

[Problems to be solved by the invention]

Since the debug device in the conventional multiprocessor system is configured as described above, a message signal for adding a synchronization signal mark to trace information is transmitted from a specific processor to each other processor via a system bus. In this case, due to the sequential transmission of the message signal to each processor and the occurrence of transmission congestion on the system bus, a time lag occurs between the synchronization signal marks added to the trace information of each processor. As a result, there has been a problem that the history of program execution in the entire multiprocessor system cannot be accurately known.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has been made in consideration of the above-mentioned problems. An object of the present invention is to obtain a debugging device in a processor system.

[Means for solving the problem]

According to the first aspect of the present invention, there is provided a debugging device in a multiprocessor system, comprising: an interrupt signal transmitting unit dedicated to transmitting an interrupt signal from a specific processor to another processor; Synchronous signal mark storage mechanism means for each processor to simultaneously store a synchronous signal mark as trace information in its own trace memory at the time of simultaneous reception of embedded signals.

Further, according to a second aspect of the present invention, there is provided a debugging apparatus for a multiprocessor system, comprising: an interrupt signal transmitting / receiving unit dedicated to an interrupt signal capable of transmitting / receiving an interrupt signal to / from each processor; When any processor transmits an interrupt signal by the means, other processors simultaneously receive the interrupt signal, and each processor simultaneously stores a synchronous signal mark in its own trace memory as trace information. And functional means.

[Action]

When one processor simultaneously transmits an interrupt signal to another processor by the interrupt signal transmitting / receiving means of the present invention, the other processor simultaneously receives the interrupt signal when receiving the interrupt signal.
The synchronization signal mark is stored together in each trace memory,
Enables accurate debugging.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 3 denotes an interrupt signal line as an interrupt signal transmitting / receiving means for allowing the processors 1-0 to 1-4 to mutually transmit and receive an interrupt signal. Thus, each processor that has received the interrupt signal at the same time,
The synchronization signal mark is stored as trace information by the synchronization signal mark storage function means provided in the own CPU.

Next, the operation will be described. When storing mutual trace information between the processors 1-0 to 1-4, for example, the processor 1-0 outputs an interrupt signal to the interrupt signal line 3 and outputs the other processors 1-1 to 1-4. For example, the data is periodically transmitted to 1-4. Therefore, the other processors 1-1 to 1-4 periodically receive this interrupt signal simultaneously with each of the processors 1-1 to 1-4.
Simultaneously stores a synchronization signal mark as trace information in its own trace memories 2-1 to 2-4.

Therefore, the synchronization signal marks having no time lag are stored and left in the trace memories 2-0 to 2-4 of the processors 1-0 to 1-4, respectively. There is no time lag in the history of the execution programs among the four programs, and synchronization can be ensured and reliable debugging can be performed.

In the above-described embodiment, a method of periodically transmitting an interrupt signal from a specific processor to each of the other processors and attaching a synchronization signal mark to each of the trace memories is adopted, but a message signal is transmitted to another guard. The same effect as that of the above embodiment can be obtained even if the processor that transmits the message transmits the interrupt signal as described above when transmitting the message.

〔The invention's effect〕

As described above, according to the first aspect of the present invention, the debug device in the multiprocessor system transmits an interrupt signal from a specific processor to each of the other processors, and each processor receives the interrupt signal simultaneously. At the same time, each processor is configured to simultaneously store the synchronization signal mark as its trace information in its own trace memory, so that when the mutual trace information is stored between the processors, the synchronization is maintained with the synchronization of each trace information. Therefore, there is an effect that the history of program execution of a plurality of processors based on the trace information can be accurately read at the time of debugging.

According to the second aspect of the present invention, since each processor is configured to be able to transmit an interrupt signal, the following effects are obtained in addition to the first aspect. That is, the faulty processor A may cause a fault due to itself, but may also cause a fault due to data transmitted from another processor B. In such a case, rather than the processor B sending an interrupt signal, the processor A
Transmits an interrupt signal at its own timing and synchronizes with each other, so that it is possible to accurately grasp its own program history and the state of another processor B.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of a conventional apparatus. 1-0 to 1-4 are processors, 2-0 to 2-4 are trace memories, 3 is interrupt signal transmitting / receiving means (interrupt signal lines), and 4 is a system bus. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. A debugging device in a multiprocessor system comprising a trace memory for storing trace information indicating a history of an execution program executed by a plurality of processors connected by a system bus. An interrupt signal transmitting means dedicated to the interrupt signal for transmitting an interrupt signal to the processor, and when each interrupt signal is simultaneously received by the interrupt signal transmitting means, each processor stores a synchronization signal mark in its own trace memory as trace information. A debug device in a multiprocessor system, comprising: a synchronous signal mark storage mechanism for simultaneously storing. 2. A debug device in a multiprocessor system comprising a trace memory for storing trace information indicating a history of an execution program executed by a plurality of processors connected by a system bus. An interrupt signal transmitting / receiving means dedicated to an interrupt signal capable of transmitting / receiving an interrupt signal, and when any processor transmits an interrupt signal by the interrupt signal transmitting / receiving means, the other processors transmit the interrupt signal. Synchronous signal mark storing function means for simultaneously receiving and simultaneously storing synchronous signal marks in its own trace memory as trace information, and a synchronous signal mark storing function means.